1 /*
2  * (C) Copyright 2006-2008
3  * Texas Instruments, <www.ti.com>
4  * Richard Woodruff <r-woodruff2@ti.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21 #ifndef _CLOCKS_OMAP3_H_
22 #define _CLOCKS_OMAP3_H_
23 
24 #define PLL_STOP		1	/* PER & IVA */
25 #define PLL_LOW_POWER_BYPASS	5	/* MPU, IVA & CORE */
26 #define PLL_FAST_RELOCK_BYPASS	6	/* CORE */
27 #define PLL_LOCK		7	/* MPU, IVA, CORE & PER */
28 
29 /*
30  * The following configurations are OPP and SysClk value independant
31  * and hence are defined here. All the other DPLL related values are
32  * tabulated in lowlevel_init.S.
33  */
34 
35 /* CORE DPLL */
36 #define CORE_M3X2	2	/* 332MHz : CM_CLKSEL1_EMU */
37 #define CORE_SSI_DIV	3	/* 221MHz : CM_CLKSEL_CORE */
38 #define CORE_FUSB_DIV	2	/* 41.5MHz: */
39 #define CORE_L4_DIV	2	/* 83MHz  : L4 */
40 #define CORE_L3_DIV	2	/* 166MHz : L3 {DDR} */
41 #define GFX_DIV		2	/* 83MHz  : CM_CLKSEL_GFX */
42 #define GFX_DIV_36X	5	/* 200MHz : CM_CLKSEL_GFX */
43 #define WKUP_RSM	2	/* 41.5MHz: CM_CLKSEL_WKUP */
44 
45 /* PER DPLL */
46 #define PER_M6X2	3	/* 288MHz: CM_CLKSEL1_EMU */
47 #define PER_M5X2	4	/* 216MHz: CM_CLKSEL_CAM */
48 #define PER_M4X2	2	/* 432MHz: CM_CLKSEL_DSS-dss1 */
49 #define PER_M3X2	16	/* 54MHz : CM_CLKSEL_DSS-tv */
50 
51 #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
52 
53 /* MPU DPLL */
54 
55 #define MPU_M_12_ES1		0x0FE
56 #define MPU_N_12_ES1		0x07
57 #define MPU_FSEL_12_ES1		0x05
58 #define MPU_M2_12_ES1		0x01
59 
60 #define MPU_M_12_ES2		0x0FA
61 #define MPU_N_12_ES2		0x05
62 #define MPU_FSEL_12_ES2		0x07
63 #define MPU_M2_ES2		0x01
64 
65 #define MPU_M_12		0x085
66 #define MPU_N_12		0x05
67 #define MPU_FSEL_12		0x07
68 #define MPU_M2_12		0x01
69 
70 #define MPU_M_13_ES1		0x17D
71 #define MPU_N_13_ES1		0x0C
72 #define MPU_FSEL_13_ES1		0x03
73 #define MPU_M2_13_ES1		0x01
74 
75 #define MPU_M_13_ES2		0x258
76 #define MPU_N_13_ES2		0x0C
77 #define MPU_FSEL_13_ES2		0x03
78 #define MPU_M2_13_ES2		0x01
79 
80 #define MPU_M_13		0x10A
81 #define MPU_N_13		0x0C
82 #define MPU_FSEL_13		0x03
83 #define MPU_M2_13		0x01
84 
85 #define MPU_M_19P2_ES1		0x179
86 #define MPU_N_19P2_ES1		0x12
87 #define MPU_FSEL_19P2_ES1	0x04
88 #define MPU_M2_19P2_ES1		0x01
89 
90 #define MPU_M_19P2_ES2		0x271
91 #define MPU_N_19P2_ES2		0x17
92 #define MPU_FSEL_19P2_ES2	0x03
93 #define MPU_M2_19P2_ES2		0x01
94 
95 #define MPU_M_19P2		0x14C
96 #define MPU_N_19P2		0x17
97 #define MPU_FSEL_19P2		0x03
98 #define MPU_M2_19P2		0x01
99 
100 #define MPU_M_26_ES1		0x17D
101 #define MPU_N_26_ES1		0x19
102 #define MPU_FSEL_26_ES1		0x03
103 #define MPU_M2_26_ES1		0x01
104 
105 #define MPU_M_26_ES2		0x0FA
106 #define MPU_N_26_ES2		0x0C
107 #define MPU_FSEL_26_ES2		0x07
108 #define MPU_M2_26_ES2		0x01
109 
110 #define MPU_M_26		0x085
111 #define MPU_N_26		0x0C
112 #define MPU_FSEL_26		0x07
113 #define MPU_M2_26		0x01
114 
115 #define MPU_M_38P4_ES1		0x1FA
116 #define MPU_N_38P4_ES1		0x32
117 #define MPU_FSEL_38P4_ES1	0x03
118 #define MPU_M2_38P4_ES1		0x01
119 
120 #define MPU_M_38P4_ES2		0x271
121 #define MPU_N_38P4_ES2		0x2F
122 #define MPU_FSEL_38P4_ES2	0x03
123 #define MPU_M2_38P4_ES2		0x01
124 
125 #define MPU_M_38P4		0x14C
126 #define MPU_N_38P4		0x2F
127 #define MPU_FSEL_38P4		0x03
128 #define MPU_M2_38P4		0x01
129 
130 /* IVA DPLL */
131 
132 #define IVA_M_12_ES1		0x07D
133 #define IVA_N_12_ES1		0x05
134 #define IVA_FSEL_12_ES1		0x07
135 #define IVA_M2_12_ES1		0x01
136 
137 #define IVA_M_12_ES2		0x0B4
138 #define IVA_N_12_ES2		0x05
139 #define IVA_FSEL_12_ES2		0x07
140 #define IVA_M2_12_ES2		0x01
141 
142 #define IVA_M_12		0x085
143 #define IVA_N_12		0x05
144 #define IVA_FSEL_12		0x07
145 #define IVA_M2_12		0x01
146 
147 #define IVA_M_13_ES1		0x0FA
148 #define IVA_N_13_ES1		0x0C
149 #define IVA_FSEL_13_ES1		0x03
150 #define IVA_M2_13_ES1		0x01
151 
152 #define IVA_M_13_ES2		0x168
153 #define IVA_N_13_ES2		0x0C
154 #define IVA_FSEL_13_ES2		0x03
155 #define IVA_M2_13_ES2		0x01
156 
157 #define IVA_M_13		0x10A
158 #define IVA_N_13		0x0C
159 #define IVA_FSEL_13		0x03
160 #define IVA_M2_13		0x01
161 
162 #define IVA_M_19P2_ES1		0x082
163 #define IVA_N_19P2_ES1		0x09
164 #define IVA_FSEL_19P2_ES1	0x07
165 #define IVA_M2_19P2_ES1		0x01
166 
167 #define IVA_M_19P2_ES2		0x0E1
168 #define IVA_N_19P2_ES2		0x0B
169 #define IVA_FSEL_19P2_ES2	0x06
170 #define IVA_M2_19P2_ES2		0x01
171 
172 #define IVA_M_19P2		0x14C
173 #define IVA_N_19P2		0x17
174 #define IVA_FSEL_19P2		0x03
175 #define IVA_M2_19P2		0x01
176 
177 #define IVA_M_26_ES1		0x07D
178 #define IVA_N_26_ES1		0x0C
179 #define IVA_FSEL_26_ES1		0x07
180 #define IVA_M2_26_ES1		0x01
181 
182 #define IVA_M_26_ES2		0x0B4
183 #define IVA_N_26_ES2		0x0C
184 #define IVA_FSEL_26_ES2		0x07
185 #define IVA_M2_26_ES2		0x01
186 
187 #define IVA_M_26		0x085
188 #define IVA_N_26		0x0C
189 #define IVA_FSEL_26		0x07
190 #define IVA_M2_26		0x01
191 
192 #define IVA_M_38P4_ES1		0x13F
193 #define IVA_N_38P4_ES1		0x30
194 #define IVA_FSEL_38P4_ES1	0x03
195 #define IVA_M2_38P4_ES1		0x01
196 
197 #define IVA_M_38P4_ES2		0x0E1
198 #define IVA_N_38P4_ES2		0x17
199 #define IVA_FSEL_38P4_ES2	0x06
200 #define IVA_M2_38P4_ES2		0x01
201 
202 #define IVA_M_38P4		0x14C
203 #define IVA_N_38P4		0x2F
204 #define IVA_FSEL_38P4		0x03
205 #define IVA_M2_38P4		0x01
206 
207 /* CORE DPLL */
208 
209 #define CORE_M_12		0xA6
210 #define CORE_N_12		0x05
211 #define CORE_FSEL_12		0x07
212 #define CORE_M2_12		0x01	/* M3 of 2 */
213 
214 #define CORE_M_12_ES1		0x19F
215 #define CORE_N_12_ES1		0x0E
216 #define CORE_FSL_12_ES1		0x03
217 #define CORE_M2_12_ES1		0x1	/* M3 of 2 */
218 
219 #define CORE_M_13		0x14C
220 #define CORE_N_13		0x0C
221 #define CORE_FSEL_13		0x03
222 #define CORE_M2_13		0x01	/* M3 of 2 */
223 
224 #define CORE_M_13_ES1		0x1B2
225 #define CORE_N_13_ES1		0x10
226 #define CORE_FSL_13_ES1		0x03
227 #define CORE_M2_13_ES1		0x01	/* M3 of 2 */
228 
229 #define CORE_M_19P2		0x19F
230 #define CORE_N_19P2		0x17
231 #define CORE_FSEL_19P2		0x03
232 #define CORE_M2_19P2		0x01	/* M3 of 2 */
233 
234 #define CORE_M_19P2_ES1		0x19F
235 #define CORE_N_19P2_ES1		0x17
236 #define CORE_FSL_19P2_ES1	0x03
237 #define CORE_M2_19P2_ES1	0x01	/* M3 of 2 */
238 
239 #define CORE_M_26		0xA6
240 #define CORE_N_26		0x0C
241 #define CORE_FSEL_26		0x07
242 #define CORE_M2_26		0x01	/* M3 of 2 */
243 
244 #define CORE_M_26_ES1		0x1B2
245 #define CORE_N_26_ES1		0x21
246 #define CORE_FSL_26_ES1		0x03
247 #define CORE_M2_26_ES1		0x01	/* M3 of 2 */
248 
249 #define CORE_M_38P4		0x19F
250 #define CORE_N_38P4		0x2F
251 #define CORE_FSEL_38P4		0x03
252 #define CORE_M2_38P4		0x01	/* M3 of 2 */
253 
254 #define CORE_M_38P4_ES1		0x19F
255 #define CORE_N_38P4_ES1		0x2F
256 #define CORE_FSL_38P4_ES1	0x03
257 #define CORE_M2_38P4_ES1	0x01	/* M3 of 2 */
258 
259 /* PER DPLL */
260 
261 #define PER_M_12		0xD8
262 #define PER_N_12		0x05
263 #define PER_FSEL_12		0x07
264 #define PER_M2_12		0x09
265 
266 #define PER_M_13		0x1B0
267 #define PER_N_13		0x0C
268 #define PER_FSEL_13		0x03
269 #define PER_M2_13		0x09
270 
271 #define PER_M_19P2		0xE1
272 #define PER_N_19P2		0x09
273 #define PER_FSEL_19P2		0x07
274 #define PER_M2_19P2		0x09
275 
276 #define PER_M_26		0xD8
277 #define PER_N_26		0x0C
278 #define PER_FSEL_26		0x07
279 #define PER_M2_26		0x09
280 
281 #define PER_M_38P4		0xE1
282 #define PER_N_38P4		0x13
283 #define PER_FSEL_38P4		0x07
284 #define PER_M2_38P4		0x09
285 
286 /* PER2 DPLL */
287 #define PER2_M_12		0x78
288 #define PER2_N_12		0x0B
289 #define PER2_FSEL_12		0x03
290 #define PER2_M2_12		0x01
291 
292 #define PER2_M_13		0x78
293 #define PER2_N_13		0x0C
294 #define PER2_FSEL_13		0x03
295 #define PER2_M2_13		0x01
296 
297 #define PER2_M_19P2		0x2EE
298 #define PER2_N_19P2		0x0B
299 #define PER2_FSEL_19P2		0x06
300 #define PER2_M2_19P2		0x0A
301 
302 #define PER2_M_26		0x78
303 #define PER2_N_26		0x0C
304 #define PER2_FSEL_26		0x03
305 #define PER2_M2_26		0x01
306 
307 #define PER2_M_38P4		0x2EE
308 #define PER2_N_38P4		0x0B
309 #define PER2_FSEL_38P4		0x06
310 #define PER2_M2_38P4		0x0A
311 
312 /* 36XX PER DPLL */
313 
314 #define PER_36XX_M_12		0x1B0
315 #define PER_36XX_N_12		0x05
316 #define PER_36XX_FSEL_12	0x07
317 #define PER_36XX_M2_12		0x09
318 
319 #define PER_36XX_M_13		0x360
320 #define PER_36XX_N_13		0x0C
321 #define PER_36XX_FSEL_13	0x03
322 #define PER_36XX_M2_13		0x09
323 
324 #define PER_36XX_M_19P2		0x1C2
325 #define PER_36XX_N_19P2		0x09
326 #define PER_36XX_FSEL_19P2	0x07
327 #define PER_36XX_M2_19P2	0x09
328 
329 #define PER_36XX_M_26		0x1B0
330 #define PER_36XX_N_26		0x0C
331 #define PER_36XX_FSEL_26	0x07
332 #define PER_36XX_M2_26		0x09
333 
334 #define PER_36XX_M_38P4		0x1C2
335 #define PER_36XX_N_38P4		0x13
336 #define PER_36XX_FSEL_38P4	0x07
337 #define PER_36XX_M2_38P4	0x09
338 
339 #endif	/* endif _CLOCKS_OMAP3_H_ */
340