1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2006-2008 3819833afSPeter Tyser * Texas Instruments, <www.ti.com> 4819833afSPeter Tyser * Richard Woodruff <r-woodruff2@ti.com> 5819833afSPeter Tyser * 6819833afSPeter Tyser * This program is free software; you can redistribute it and/or 7819833afSPeter Tyser * modify it under the terms of the GNU General Public License as 8819833afSPeter Tyser * published by the Free Software Foundation; either version 2 of 9819833afSPeter Tyser * the License, or (at your option) any later version. 10819833afSPeter Tyser * 11819833afSPeter Tyser * This program is distributed in the hope that it will be useful, 12819833afSPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 13819833afSPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 14819833afSPeter Tyser * GNU General Public License for more details. 15819833afSPeter Tyser * 16819833afSPeter Tyser * You should have received a copy of the GNU General Public License 17819833afSPeter Tyser * along with this program; if not, write to the Free Software 18819833afSPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19819833afSPeter Tyser * MA 02111-1307 USA 20819833afSPeter Tyser */ 21819833afSPeter Tyser #ifndef _CLOCKS_OMAP3_H_ 22819833afSPeter Tyser #define _CLOCKS_OMAP3_H_ 23819833afSPeter Tyser 24819833afSPeter Tyser #define PLL_STOP 1 /* PER & IVA */ 25819833afSPeter Tyser #define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ 26819833afSPeter Tyser #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ 27819833afSPeter Tyser #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ 28819833afSPeter Tyser 29819833afSPeter Tyser /* 30819833afSPeter Tyser * The following configurations are OPP and SysClk value independant 31819833afSPeter Tyser * and hence are defined here. All the other DPLL related values are 32819833afSPeter Tyser * tabulated in lowlevel_init.S. 33819833afSPeter Tyser */ 34819833afSPeter Tyser 35819833afSPeter Tyser /* CORE DPLL */ 36819833afSPeter Tyser #define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ 37819833afSPeter Tyser #define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ 38819833afSPeter Tyser #define CORE_FUSB_DIV 2 /* 41.5MHz: */ 39819833afSPeter Tyser #define CORE_L4_DIV 2 /* 83MHz : L4 */ 40819833afSPeter Tyser #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ 41819833afSPeter Tyser #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ 42*f4dac3e1SVaibhav Hiremath #define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */ 43819833afSPeter Tyser #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ 44819833afSPeter Tyser 45819833afSPeter Tyser /* PER DPLL */ 46819833afSPeter Tyser #define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ 47819833afSPeter Tyser #define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ 48819833afSPeter Tyser #define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ 49819833afSPeter Tyser #define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ 50819833afSPeter Tyser 51819833afSPeter Tyser #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) 52819833afSPeter Tyser 53819833afSPeter Tyser /* MPU DPLL */ 54819833afSPeter Tyser 55819833afSPeter Tyser #define MPU_M_12_ES1 0x0FE 56819833afSPeter Tyser #define MPU_N_12_ES1 0x07 57819833afSPeter Tyser #define MPU_FSEL_12_ES1 0x05 58819833afSPeter Tyser #define MPU_M2_12_ES1 0x01 59819833afSPeter Tyser 60819833afSPeter Tyser #define MPU_M_12_ES2 0x0FA 61819833afSPeter Tyser #define MPU_N_12_ES2 0x05 62819833afSPeter Tyser #define MPU_FSEL_12_ES2 0x07 63819833afSPeter Tyser #define MPU_M2_ES2 0x01 64819833afSPeter Tyser 65819833afSPeter Tyser #define MPU_M_12 0x085 66819833afSPeter Tyser #define MPU_N_12 0x05 67819833afSPeter Tyser #define MPU_FSEL_12 0x07 68819833afSPeter Tyser #define MPU_M2_12 0x01 69819833afSPeter Tyser 70819833afSPeter Tyser #define MPU_M_13_ES1 0x17D 71819833afSPeter Tyser #define MPU_N_13_ES1 0x0C 72819833afSPeter Tyser #define MPU_FSEL_13_ES1 0x03 73819833afSPeter Tyser #define MPU_M2_13_ES1 0x01 74819833afSPeter Tyser 75819833afSPeter Tyser #define MPU_M_13_ES2 0x1F4 76819833afSPeter Tyser #define MPU_N_13_ES2 0x0C 77819833afSPeter Tyser #define MPU_FSEL_13_ES2 0x03 78819833afSPeter Tyser #define MPU_M2_13_ES2 0x01 79819833afSPeter Tyser 80819833afSPeter Tyser #define MPU_M_13 0x10A 81819833afSPeter Tyser #define MPU_N_13 0x0C 82819833afSPeter Tyser #define MPU_FSEL_13 0x03 83819833afSPeter Tyser #define MPU_M2_13 0x01 84819833afSPeter Tyser 85819833afSPeter Tyser #define MPU_M_19P2_ES1 0x179 86819833afSPeter Tyser #define MPU_N_19P2_ES1 0x12 87819833afSPeter Tyser #define MPU_FSEL_19P2_ES1 0x04 88819833afSPeter Tyser #define MPU_M2_19P2_ES1 0x01 89819833afSPeter Tyser 90819833afSPeter Tyser #define MPU_M_19P2_ES2 0x271 91819833afSPeter Tyser #define MPU_N_19P2_ES2 0x17 92819833afSPeter Tyser #define MPU_FSEL_19P2_ES2 0x03 93819833afSPeter Tyser #define MPU_M2_19P2_ES2 0x01 94819833afSPeter Tyser 95819833afSPeter Tyser #define MPU_M_19P2 0x14C 96819833afSPeter Tyser #define MPU_N_19P2 0x17 97819833afSPeter Tyser #define MPU_FSEL_19P2 0x03 98819833afSPeter Tyser #define MPU_M2_19P2 0x01 99819833afSPeter Tyser 100819833afSPeter Tyser #define MPU_M_26_ES1 0x17D 101819833afSPeter Tyser #define MPU_N_26_ES1 0x19 102819833afSPeter Tyser #define MPU_FSEL_26_ES1 0x03 103819833afSPeter Tyser #define MPU_M2_26_ES1 0x01 104819833afSPeter Tyser 105819833afSPeter Tyser #define MPU_M_26_ES2 0x0FA 106819833afSPeter Tyser #define MPU_N_26_ES2 0x0C 107819833afSPeter Tyser #define MPU_FSEL_26_ES2 0x07 108819833afSPeter Tyser #define MPU_M2_26_ES2 0x01 109819833afSPeter Tyser 110819833afSPeter Tyser #define MPU_M_26 0x085 111819833afSPeter Tyser #define MPU_N_26 0x0C 112819833afSPeter Tyser #define MPU_FSEL_26 0x07 113819833afSPeter Tyser #define MPU_M2_26 0x01 114819833afSPeter Tyser 115819833afSPeter Tyser #define MPU_M_38P4_ES1 0x1FA 116819833afSPeter Tyser #define MPU_N_38P4_ES1 0x32 117819833afSPeter Tyser #define MPU_FSEL_38P4_ES1 0x03 118819833afSPeter Tyser #define MPU_M2_38P4_ES1 0x01 119819833afSPeter Tyser 120819833afSPeter Tyser #define MPU_M_38P4_ES2 0x271 121819833afSPeter Tyser #define MPU_N_38P4_ES2 0x2F 122819833afSPeter Tyser #define MPU_FSEL_38P4_ES2 0x03 123819833afSPeter Tyser #define MPU_M2_38P4_ES2 0x01 124819833afSPeter Tyser 125819833afSPeter Tyser #define MPU_M_38P4 0x14C 126819833afSPeter Tyser #define MPU_N_38P4 0x2F 127819833afSPeter Tyser #define MPU_FSEL_38P4 0x03 128819833afSPeter Tyser #define MPU_M2_38P4 0x01 129819833afSPeter Tyser 130819833afSPeter Tyser /* IVA DPLL */ 131819833afSPeter Tyser 132819833afSPeter Tyser #define IVA_M_12_ES1 0x07D 133819833afSPeter Tyser #define IVA_N_12_ES1 0x05 134819833afSPeter Tyser #define IVA_FSEL_12_ES1 0x07 135819833afSPeter Tyser #define IVA_M2_12_ES1 0x01 136819833afSPeter Tyser 137819833afSPeter Tyser #define IVA_M_12_ES2 0x0B4 138819833afSPeter Tyser #define IVA_N_12_ES2 0x05 139819833afSPeter Tyser #define IVA_FSEL_12_ES2 0x07 140819833afSPeter Tyser #define IVA_M2_12_ES2 0x01 141819833afSPeter Tyser 142819833afSPeter Tyser #define IVA_M_12 0x085 143819833afSPeter Tyser #define IVA_N_12 0x05 144819833afSPeter Tyser #define IVA_FSEL_12 0x07 145819833afSPeter Tyser #define IVA_M2_12 0x01 146819833afSPeter Tyser 147819833afSPeter Tyser #define IVA_M_13_ES1 0x0FA 148819833afSPeter Tyser #define IVA_N_13_ES1 0x0C 149819833afSPeter Tyser #define IVA_FSEL_13_ES1 0x03 150819833afSPeter Tyser #define IVA_M2_13_ES1 0x01 151819833afSPeter Tyser 152819833afSPeter Tyser #define IVA_M_13_ES2 0x168 153819833afSPeter Tyser #define IVA_N_13_ES2 0x0C 154819833afSPeter Tyser #define IVA_FSEL_13_ES2 0x03 155819833afSPeter Tyser #define IVA_M2_13_ES2 0x01 156819833afSPeter Tyser 157819833afSPeter Tyser #define IVA_M_13 0x10A 158819833afSPeter Tyser #define IVA_N_13 0x0C 159819833afSPeter Tyser #define IVA_FSEL_13 0x03 160819833afSPeter Tyser #define IVA_M2_13 0x01 161819833afSPeter Tyser 162819833afSPeter Tyser #define IVA_M_19P2_ES1 0x082 163819833afSPeter Tyser #define IVA_N_19P2_ES1 0x09 164819833afSPeter Tyser #define IVA_FSEL_19P2_ES1 0x07 165819833afSPeter Tyser #define IVA_M2_19P2_ES1 0x01 166819833afSPeter Tyser 167819833afSPeter Tyser #define IVA_M_19P2_ES2 0x0E1 168819833afSPeter Tyser #define IVA_N_19P2_ES2 0x0B 169819833afSPeter Tyser #define IVA_FSEL_19P2_ES2 0x06 170819833afSPeter Tyser #define IVA_M2_19P2_ES2 0x01 171819833afSPeter Tyser 172819833afSPeter Tyser #define IVA_M_19P2 0x14C 173819833afSPeter Tyser #define IVA_N_19P2 0x17 174819833afSPeter Tyser #define IVA_FSEL_19P2 0x03 175819833afSPeter Tyser #define IVA_M2_19P2 0x01 176819833afSPeter Tyser 177819833afSPeter Tyser #define IVA_M_26_ES1 0x07D 178819833afSPeter Tyser #define IVA_N_26_ES1 0x0C 179819833afSPeter Tyser #define IVA_FSEL_26_ES1 0x07 180819833afSPeter Tyser #define IVA_M2_26_ES1 0x01 181819833afSPeter Tyser 182819833afSPeter Tyser #define IVA_M_26_ES2 0x0B4 183819833afSPeter Tyser #define IVA_N_26_ES2 0x0C 184819833afSPeter Tyser #define IVA_FSEL_26_ES2 0x07 185819833afSPeter Tyser #define IVA_M2_26_ES2 0x01 186819833afSPeter Tyser 187819833afSPeter Tyser #define IVA_M_26 0x085 188819833afSPeter Tyser #define IVA_N_26 0x0C 189819833afSPeter Tyser #define IVA_FSEL_26 0x07 190819833afSPeter Tyser #define IVA_M2_26 0x01 191819833afSPeter Tyser 192819833afSPeter Tyser #define IVA_M_38P4_ES1 0x13F 193819833afSPeter Tyser #define IVA_N_38P4_ES1 0x30 194819833afSPeter Tyser #define IVA_FSEL_38P4_ES1 0x03 195819833afSPeter Tyser #define IVA_M2_38P4_ES1 0x01 196819833afSPeter Tyser 197819833afSPeter Tyser #define IVA_M_38P4_ES2 0x0E1 198819833afSPeter Tyser #define IVA_N_38P4_ES2 0x17 199819833afSPeter Tyser #define IVA_FSEL_38P4_ES2 0x06 200819833afSPeter Tyser #define IVA_M2_38P4_ES2 0x01 201819833afSPeter Tyser 202819833afSPeter Tyser #define IVA_M_38P4 0x14C 203819833afSPeter Tyser #define IVA_N_38P4 0x2F 204819833afSPeter Tyser #define IVA_FSEL_38P4 0x03 205819833afSPeter Tyser #define IVA_M2_38P4 0x01 206819833afSPeter Tyser 207819833afSPeter Tyser /* CORE DPLL */ 208819833afSPeter Tyser 209819833afSPeter Tyser #define CORE_M_12 0xA6 210819833afSPeter Tyser #define CORE_N_12 0x05 211819833afSPeter Tyser #define CORE_FSEL_12 0x07 212819833afSPeter Tyser #define CORE_M2_12 0x01 /* M3 of 2 */ 213819833afSPeter Tyser 214819833afSPeter Tyser #define CORE_M_12_ES1 0x19F 215819833afSPeter Tyser #define CORE_N_12_ES1 0x0E 216819833afSPeter Tyser #define CORE_FSL_12_ES1 0x03 217819833afSPeter Tyser #define CORE_M2_12_ES1 0x1 /* M3 of 2 */ 218819833afSPeter Tyser 219819833afSPeter Tyser #define CORE_M_13 0x14C 220819833afSPeter Tyser #define CORE_N_13 0x0C 221819833afSPeter Tyser #define CORE_FSEL_13 0x03 222819833afSPeter Tyser #define CORE_M2_13 0x01 /* M3 of 2 */ 223819833afSPeter Tyser 224819833afSPeter Tyser #define CORE_M_13_ES1 0x1B2 225819833afSPeter Tyser #define CORE_N_13_ES1 0x10 226819833afSPeter Tyser #define CORE_FSL_13_ES1 0x03 227819833afSPeter Tyser #define CORE_M2_13_ES1 0x01 /* M3 of 2 */ 228819833afSPeter Tyser 229819833afSPeter Tyser #define CORE_M_19P2 0x19F 230819833afSPeter Tyser #define CORE_N_19P2 0x17 231819833afSPeter Tyser #define CORE_FSEL_19P2 0x03 232819833afSPeter Tyser #define CORE_M2_19P2 0x01 /* M3 of 2 */ 233819833afSPeter Tyser 234819833afSPeter Tyser #define CORE_M_19P2_ES1 0x19F 235819833afSPeter Tyser #define CORE_N_19P2_ES1 0x17 236819833afSPeter Tyser #define CORE_FSL_19P2_ES1 0x03 237819833afSPeter Tyser #define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ 238819833afSPeter Tyser 239819833afSPeter Tyser #define CORE_M_26 0xA6 240819833afSPeter Tyser #define CORE_N_26 0x0C 241819833afSPeter Tyser #define CORE_FSEL_26 0x07 242819833afSPeter Tyser #define CORE_M2_26 0x01 /* M3 of 2 */ 243819833afSPeter Tyser 244819833afSPeter Tyser #define CORE_M_26_ES1 0x1B2 245819833afSPeter Tyser #define CORE_N_26_ES1 0x21 246819833afSPeter Tyser #define CORE_FSL_26_ES1 0x03 247819833afSPeter Tyser #define CORE_M2_26_ES1 0x01 /* M3 of 2 */ 248819833afSPeter Tyser 249819833afSPeter Tyser #define CORE_M_38P4 0x19F 250819833afSPeter Tyser #define CORE_N_38P4 0x2F 251819833afSPeter Tyser #define CORE_FSEL_38P4 0x03 252819833afSPeter Tyser #define CORE_M2_38P4 0x01 /* M3 of 2 */ 253819833afSPeter Tyser 254819833afSPeter Tyser #define CORE_M_38P4_ES1 0x19F 255819833afSPeter Tyser #define CORE_N_38P4_ES1 0x2F 256819833afSPeter Tyser #define CORE_FSL_38P4_ES1 0x03 257819833afSPeter Tyser #define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ 258819833afSPeter Tyser 259819833afSPeter Tyser /* PER DPLL */ 260819833afSPeter Tyser 261819833afSPeter Tyser #define PER_M_12 0xD8 262819833afSPeter Tyser #define PER_N_12 0x05 263819833afSPeter Tyser #define PER_FSEL_12 0x07 264819833afSPeter Tyser #define PER_M2_12 0x09 265819833afSPeter Tyser 266819833afSPeter Tyser #define PER_M_13 0x1B0 267819833afSPeter Tyser #define PER_N_13 0x0C 268819833afSPeter Tyser #define PER_FSEL_13 0x03 269819833afSPeter Tyser #define PER_M2_13 0x09 270819833afSPeter Tyser 271819833afSPeter Tyser #define PER_M_19P2 0xE1 272819833afSPeter Tyser #define PER_N_19P2 0x09 273819833afSPeter Tyser #define PER_FSEL_19P2 0x07 274819833afSPeter Tyser #define PER_M2_19P2 0x09 275819833afSPeter Tyser 276819833afSPeter Tyser #define PER_M_26 0xD8 277819833afSPeter Tyser #define PER_N_26 0x0C 278819833afSPeter Tyser #define PER_FSEL_26 0x07 279819833afSPeter Tyser #define PER_M2_26 0x09 280819833afSPeter Tyser 281819833afSPeter Tyser #define PER_M_38P4 0xE1 282819833afSPeter Tyser #define PER_N_38P4 0x13 283819833afSPeter Tyser #define PER_FSEL_38P4 0x07 284819833afSPeter Tyser #define PER_M2_38P4 0x09 285819833afSPeter Tyser 2867b89795fSAlexander Holler /* PER2 DPLL */ 2877b89795fSAlexander Holler #define PER2_M_12 0x78 2887b89795fSAlexander Holler #define PER2_N_12 0x0B 2897b89795fSAlexander Holler #define PER2_FSEL_12 0x03 2907b89795fSAlexander Holler #define PER2_M2_12 0x01 2917b89795fSAlexander Holler 2927b89795fSAlexander Holler #define PER2_M_13 0x78 2937b89795fSAlexander Holler #define PER2_N_13 0x0C 2947b89795fSAlexander Holler #define PER2_FSEL_13 0x03 2957b89795fSAlexander Holler #define PER2_M2_13 0x01 2967b89795fSAlexander Holler 2977b89795fSAlexander Holler #define PER2_M_19P2 0x2EE 2987b89795fSAlexander Holler #define PER2_N_19P2 0x0B 2997b89795fSAlexander Holler #define PER2_FSEL_19P2 0x06 3007b89795fSAlexander Holler #define PER2_M2_19P2 0x0A 3017b89795fSAlexander Holler 3027b89795fSAlexander Holler #define PER2_M_26 0x78 3037b89795fSAlexander Holler #define PER2_N_26 0x0C 3047b89795fSAlexander Holler #define PER2_FSEL_26 0x03 3057b89795fSAlexander Holler #define PER2_M2_26 0x01 3067b89795fSAlexander Holler 3077b89795fSAlexander Holler #define PER2_M_38P4 0x2EE 3087b89795fSAlexander Holler #define PER2_N_38P4 0x0B 3097b89795fSAlexander Holler #define PER2_FSEL_38P4 0x06 3107b89795fSAlexander Holler #define PER2_M2_38P4 0x0A 3117b89795fSAlexander Holler 3127c281c98SSteve Sakoman /* 36XX PER DPLL */ 3137c281c98SSteve Sakoman 3147c281c98SSteve Sakoman #define PER_36XX_M_12 0x1B0 3157c281c98SSteve Sakoman #define PER_36XX_N_12 0x05 3167c281c98SSteve Sakoman #define PER_36XX_FSEL_12 0x07 3177c281c98SSteve Sakoman #define PER_36XX_M2_12 0x09 3187c281c98SSteve Sakoman 3197c281c98SSteve Sakoman #define PER_36XX_M_13 0x360 3207c281c98SSteve Sakoman #define PER_36XX_N_13 0x0C 3217c281c98SSteve Sakoman #define PER_36XX_FSEL_13 0x03 3227c281c98SSteve Sakoman #define PER_36XX_M2_13 0x09 3237c281c98SSteve Sakoman 3247c281c98SSteve Sakoman #define PER_36XX_M_19P2 0x1C2 3257c281c98SSteve Sakoman #define PER_36XX_N_19P2 0x09 3267c281c98SSteve Sakoman #define PER_36XX_FSEL_19P2 0x07 3277c281c98SSteve Sakoman #define PER_36XX_M2_19P2 0x09 3287c281c98SSteve Sakoman 3297c281c98SSteve Sakoman #define PER_36XX_M_26 0x1B0 3307c281c98SSteve Sakoman #define PER_36XX_N_26 0x0C 3317c281c98SSteve Sakoman #define PER_36XX_FSEL_26 0x07 3327c281c98SSteve Sakoman #define PER_36XX_M2_26 0x09 3337c281c98SSteve Sakoman 3347c281c98SSteve Sakoman #define PER_36XX_M_38P4 0x1C2 3357c281c98SSteve Sakoman #define PER_36XX_N_38P4 0x13 3367c281c98SSteve Sakoman #define PER_36XX_FSEL_38P4 0x07 3377c281c98SSteve Sakoman #define PER_36XX_M2_38P4 0x09 3387c281c98SSteve Sakoman 339819833afSPeter Tyser #endif /* endif _CLOCKS_OMAP3_H_ */ 340