1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2819833afSPeter Tyser /* 3819833afSPeter Tyser * (C) Copyright 2006-2008 4819833afSPeter Tyser * Texas Instruments, <www.ti.com> 5819833afSPeter Tyser * Richard Woodruff <r-woodruff2@ti.com> 6819833afSPeter Tyser */ 7819833afSPeter Tyser #ifndef _CLOCKS_OMAP3_H_ 8819833afSPeter Tyser #define _CLOCKS_OMAP3_H_ 9819833afSPeter Tyser 10819833afSPeter Tyser #define PLL_STOP 1 /* PER & IVA */ 11819833afSPeter Tyser #define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ 12819833afSPeter Tyser #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ 13819833afSPeter Tyser #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ 14819833afSPeter Tyser 15819833afSPeter Tyser /* 16819833afSPeter Tyser * The following configurations are OPP and SysClk value independant 17819833afSPeter Tyser * and hence are defined here. All the other DPLL related values are 18819833afSPeter Tyser * tabulated in lowlevel_init.S. 19819833afSPeter Tyser */ 20819833afSPeter Tyser 21819833afSPeter Tyser /* CORE DPLL */ 22819833afSPeter Tyser #define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ 23819833afSPeter Tyser #define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ 24819833afSPeter Tyser #define CORE_FUSB_DIV 2 /* 41.5MHz: */ 25819833afSPeter Tyser #define CORE_L4_DIV 2 /* 83MHz : L4 */ 26819833afSPeter Tyser #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ 27819833afSPeter Tyser #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ 28f4dac3e1SVaibhav Hiremath #define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */ 29819833afSPeter Tyser #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ 30819833afSPeter Tyser 31819833afSPeter Tyser /* PER DPLL */ 32819833afSPeter Tyser #define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ 33819833afSPeter Tyser #define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ 34819833afSPeter Tyser #define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ 35819833afSPeter Tyser #define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ 36819833afSPeter Tyser 37819833afSPeter Tyser #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) 38819833afSPeter Tyser 39819833afSPeter Tyser /* MPU DPLL */ 40819833afSPeter Tyser 41819833afSPeter Tyser #define MPU_M_12_ES1 0x0FE 42819833afSPeter Tyser #define MPU_N_12_ES1 0x07 43819833afSPeter Tyser #define MPU_FSEL_12_ES1 0x05 44819833afSPeter Tyser #define MPU_M2_12_ES1 0x01 45819833afSPeter Tyser 46819833afSPeter Tyser #define MPU_M_12_ES2 0x0FA 47819833afSPeter Tyser #define MPU_N_12_ES2 0x05 48819833afSPeter Tyser #define MPU_FSEL_12_ES2 0x07 49819833afSPeter Tyser #define MPU_M2_ES2 0x01 50819833afSPeter Tyser 51819833afSPeter Tyser #define MPU_M_12 0x085 52819833afSPeter Tyser #define MPU_N_12 0x05 53819833afSPeter Tyser #define MPU_FSEL_12 0x07 54819833afSPeter Tyser #define MPU_M2_12 0x01 55819833afSPeter Tyser 56819833afSPeter Tyser #define MPU_M_13_ES1 0x17D 57819833afSPeter Tyser #define MPU_N_13_ES1 0x0C 58819833afSPeter Tyser #define MPU_FSEL_13_ES1 0x03 59819833afSPeter Tyser #define MPU_M2_13_ES1 0x01 60819833afSPeter Tyser 61c8e5ba80SSchuyler Patton #define MPU_M_13_ES2 0x258 62819833afSPeter Tyser #define MPU_N_13_ES2 0x0C 63819833afSPeter Tyser #define MPU_FSEL_13_ES2 0x03 64819833afSPeter Tyser #define MPU_M2_13_ES2 0x01 65819833afSPeter Tyser 66819833afSPeter Tyser #define MPU_M_13 0x10A 67819833afSPeter Tyser #define MPU_N_13 0x0C 68819833afSPeter Tyser #define MPU_FSEL_13 0x03 69819833afSPeter Tyser #define MPU_M2_13 0x01 70819833afSPeter Tyser 71819833afSPeter Tyser #define MPU_M_19P2_ES1 0x179 72819833afSPeter Tyser #define MPU_N_19P2_ES1 0x12 73819833afSPeter Tyser #define MPU_FSEL_19P2_ES1 0x04 74819833afSPeter Tyser #define MPU_M2_19P2_ES1 0x01 75819833afSPeter Tyser 76819833afSPeter Tyser #define MPU_M_19P2_ES2 0x271 77819833afSPeter Tyser #define MPU_N_19P2_ES2 0x17 78819833afSPeter Tyser #define MPU_FSEL_19P2_ES2 0x03 79819833afSPeter Tyser #define MPU_M2_19P2_ES2 0x01 80819833afSPeter Tyser 81819833afSPeter Tyser #define MPU_M_19P2 0x14C 82819833afSPeter Tyser #define MPU_N_19P2 0x17 83819833afSPeter Tyser #define MPU_FSEL_19P2 0x03 84819833afSPeter Tyser #define MPU_M2_19P2 0x01 85819833afSPeter Tyser 86819833afSPeter Tyser #define MPU_M_26_ES1 0x17D 87819833afSPeter Tyser #define MPU_N_26_ES1 0x19 88819833afSPeter Tyser #define MPU_FSEL_26_ES1 0x03 89819833afSPeter Tyser #define MPU_M2_26_ES1 0x01 90819833afSPeter Tyser 91819833afSPeter Tyser #define MPU_M_26_ES2 0x0FA 92819833afSPeter Tyser #define MPU_N_26_ES2 0x0C 93819833afSPeter Tyser #define MPU_FSEL_26_ES2 0x07 94819833afSPeter Tyser #define MPU_M2_26_ES2 0x01 95819833afSPeter Tyser 96819833afSPeter Tyser #define MPU_M_26 0x085 97819833afSPeter Tyser #define MPU_N_26 0x0C 98819833afSPeter Tyser #define MPU_FSEL_26 0x07 99819833afSPeter Tyser #define MPU_M2_26 0x01 100819833afSPeter Tyser 101819833afSPeter Tyser #define MPU_M_38P4_ES1 0x1FA 102819833afSPeter Tyser #define MPU_N_38P4_ES1 0x32 103819833afSPeter Tyser #define MPU_FSEL_38P4_ES1 0x03 104819833afSPeter Tyser #define MPU_M2_38P4_ES1 0x01 105819833afSPeter Tyser 106819833afSPeter Tyser #define MPU_M_38P4_ES2 0x271 107819833afSPeter Tyser #define MPU_N_38P4_ES2 0x2F 108819833afSPeter Tyser #define MPU_FSEL_38P4_ES2 0x03 109819833afSPeter Tyser #define MPU_M2_38P4_ES2 0x01 110819833afSPeter Tyser 111819833afSPeter Tyser #define MPU_M_38P4 0x14C 112819833afSPeter Tyser #define MPU_N_38P4 0x2F 113819833afSPeter Tyser #define MPU_FSEL_38P4 0x03 114819833afSPeter Tyser #define MPU_M2_38P4 0x01 115819833afSPeter Tyser 116819833afSPeter Tyser /* IVA DPLL */ 117819833afSPeter Tyser 118819833afSPeter Tyser #define IVA_M_12_ES1 0x07D 119819833afSPeter Tyser #define IVA_N_12_ES1 0x05 120819833afSPeter Tyser #define IVA_FSEL_12_ES1 0x07 121819833afSPeter Tyser #define IVA_M2_12_ES1 0x01 122819833afSPeter Tyser 123819833afSPeter Tyser #define IVA_M_12_ES2 0x0B4 124819833afSPeter Tyser #define IVA_N_12_ES2 0x05 125819833afSPeter Tyser #define IVA_FSEL_12_ES2 0x07 126819833afSPeter Tyser #define IVA_M2_12_ES2 0x01 127819833afSPeter Tyser 128819833afSPeter Tyser #define IVA_M_12 0x085 129819833afSPeter Tyser #define IVA_N_12 0x05 130819833afSPeter Tyser #define IVA_FSEL_12 0x07 131819833afSPeter Tyser #define IVA_M2_12 0x01 132819833afSPeter Tyser 133819833afSPeter Tyser #define IVA_M_13_ES1 0x0FA 134819833afSPeter Tyser #define IVA_N_13_ES1 0x0C 135819833afSPeter Tyser #define IVA_FSEL_13_ES1 0x03 136819833afSPeter Tyser #define IVA_M2_13_ES1 0x01 137819833afSPeter Tyser 138819833afSPeter Tyser #define IVA_M_13_ES2 0x168 139819833afSPeter Tyser #define IVA_N_13_ES2 0x0C 140819833afSPeter Tyser #define IVA_FSEL_13_ES2 0x03 141819833afSPeter Tyser #define IVA_M2_13_ES2 0x01 142819833afSPeter Tyser 143819833afSPeter Tyser #define IVA_M_13 0x10A 144819833afSPeter Tyser #define IVA_N_13 0x0C 145819833afSPeter Tyser #define IVA_FSEL_13 0x03 146819833afSPeter Tyser #define IVA_M2_13 0x01 147819833afSPeter Tyser 148819833afSPeter Tyser #define IVA_M_19P2_ES1 0x082 149819833afSPeter Tyser #define IVA_N_19P2_ES1 0x09 150819833afSPeter Tyser #define IVA_FSEL_19P2_ES1 0x07 151819833afSPeter Tyser #define IVA_M2_19P2_ES1 0x01 152819833afSPeter Tyser 153819833afSPeter Tyser #define IVA_M_19P2_ES2 0x0E1 154819833afSPeter Tyser #define IVA_N_19P2_ES2 0x0B 155819833afSPeter Tyser #define IVA_FSEL_19P2_ES2 0x06 156819833afSPeter Tyser #define IVA_M2_19P2_ES2 0x01 157819833afSPeter Tyser 158819833afSPeter Tyser #define IVA_M_19P2 0x14C 159819833afSPeter Tyser #define IVA_N_19P2 0x17 160819833afSPeter Tyser #define IVA_FSEL_19P2 0x03 161819833afSPeter Tyser #define IVA_M2_19P2 0x01 162819833afSPeter Tyser 163819833afSPeter Tyser #define IVA_M_26_ES1 0x07D 164819833afSPeter Tyser #define IVA_N_26_ES1 0x0C 165819833afSPeter Tyser #define IVA_FSEL_26_ES1 0x07 166819833afSPeter Tyser #define IVA_M2_26_ES1 0x01 167819833afSPeter Tyser 168819833afSPeter Tyser #define IVA_M_26_ES2 0x0B4 169819833afSPeter Tyser #define IVA_N_26_ES2 0x0C 170819833afSPeter Tyser #define IVA_FSEL_26_ES2 0x07 171819833afSPeter Tyser #define IVA_M2_26_ES2 0x01 172819833afSPeter Tyser 173819833afSPeter Tyser #define IVA_M_26 0x085 174819833afSPeter Tyser #define IVA_N_26 0x0C 175819833afSPeter Tyser #define IVA_FSEL_26 0x07 176819833afSPeter Tyser #define IVA_M2_26 0x01 177819833afSPeter Tyser 178819833afSPeter Tyser #define IVA_M_38P4_ES1 0x13F 179819833afSPeter Tyser #define IVA_N_38P4_ES1 0x30 180819833afSPeter Tyser #define IVA_FSEL_38P4_ES1 0x03 181819833afSPeter Tyser #define IVA_M2_38P4_ES1 0x01 182819833afSPeter Tyser 183819833afSPeter Tyser #define IVA_M_38P4_ES2 0x0E1 184819833afSPeter Tyser #define IVA_N_38P4_ES2 0x17 185819833afSPeter Tyser #define IVA_FSEL_38P4_ES2 0x06 186819833afSPeter Tyser #define IVA_M2_38P4_ES2 0x01 187819833afSPeter Tyser 188819833afSPeter Tyser #define IVA_M_38P4 0x14C 189819833afSPeter Tyser #define IVA_N_38P4 0x2F 190819833afSPeter Tyser #define IVA_FSEL_38P4 0x03 191819833afSPeter Tyser #define IVA_M2_38P4 0x01 192819833afSPeter Tyser 193819833afSPeter Tyser /* CORE DPLL */ 194819833afSPeter Tyser 195819833afSPeter Tyser #define CORE_M_12 0xA6 196819833afSPeter Tyser #define CORE_N_12 0x05 197819833afSPeter Tyser #define CORE_FSEL_12 0x07 198819833afSPeter Tyser #define CORE_M2_12 0x01 /* M3 of 2 */ 199819833afSPeter Tyser 200819833afSPeter Tyser #define CORE_M_12_ES1 0x19F 201819833afSPeter Tyser #define CORE_N_12_ES1 0x0E 202819833afSPeter Tyser #define CORE_FSL_12_ES1 0x03 203819833afSPeter Tyser #define CORE_M2_12_ES1 0x1 /* M3 of 2 */ 204819833afSPeter Tyser 205819833afSPeter Tyser #define CORE_M_13 0x14C 206819833afSPeter Tyser #define CORE_N_13 0x0C 207819833afSPeter Tyser #define CORE_FSEL_13 0x03 208819833afSPeter Tyser #define CORE_M2_13 0x01 /* M3 of 2 */ 209819833afSPeter Tyser 210819833afSPeter Tyser #define CORE_M_13_ES1 0x1B2 211819833afSPeter Tyser #define CORE_N_13_ES1 0x10 212819833afSPeter Tyser #define CORE_FSL_13_ES1 0x03 213819833afSPeter Tyser #define CORE_M2_13_ES1 0x01 /* M3 of 2 */ 214819833afSPeter Tyser 215819833afSPeter Tyser #define CORE_M_19P2 0x19F 216819833afSPeter Tyser #define CORE_N_19P2 0x17 217819833afSPeter Tyser #define CORE_FSEL_19P2 0x03 218819833afSPeter Tyser #define CORE_M2_19P2 0x01 /* M3 of 2 */ 219819833afSPeter Tyser 220819833afSPeter Tyser #define CORE_M_19P2_ES1 0x19F 221819833afSPeter Tyser #define CORE_N_19P2_ES1 0x17 222819833afSPeter Tyser #define CORE_FSL_19P2_ES1 0x03 223819833afSPeter Tyser #define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ 224819833afSPeter Tyser 225819833afSPeter Tyser #define CORE_M_26 0xA6 226819833afSPeter Tyser #define CORE_N_26 0x0C 227819833afSPeter Tyser #define CORE_FSEL_26 0x07 228819833afSPeter Tyser #define CORE_M2_26 0x01 /* M3 of 2 */ 229819833afSPeter Tyser 230819833afSPeter Tyser #define CORE_M_26_ES1 0x1B2 231819833afSPeter Tyser #define CORE_N_26_ES1 0x21 232819833afSPeter Tyser #define CORE_FSL_26_ES1 0x03 233819833afSPeter Tyser #define CORE_M2_26_ES1 0x01 /* M3 of 2 */ 234819833afSPeter Tyser 235819833afSPeter Tyser #define CORE_M_38P4 0x19F 236819833afSPeter Tyser #define CORE_N_38P4 0x2F 237819833afSPeter Tyser #define CORE_FSEL_38P4 0x03 238819833afSPeter Tyser #define CORE_M2_38P4 0x01 /* M3 of 2 */ 239819833afSPeter Tyser 240819833afSPeter Tyser #define CORE_M_38P4_ES1 0x19F 241819833afSPeter Tyser #define CORE_N_38P4_ES1 0x2F 242819833afSPeter Tyser #define CORE_FSL_38P4_ES1 0x03 243819833afSPeter Tyser #define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ 244819833afSPeter Tyser 245819833afSPeter Tyser /* PER DPLL */ 246819833afSPeter Tyser 247819833afSPeter Tyser #define PER_M_12 0xD8 248819833afSPeter Tyser #define PER_N_12 0x05 249819833afSPeter Tyser #define PER_FSEL_12 0x07 250819833afSPeter Tyser #define PER_M2_12 0x09 251819833afSPeter Tyser 252819833afSPeter Tyser #define PER_M_13 0x1B0 253819833afSPeter Tyser #define PER_N_13 0x0C 254819833afSPeter Tyser #define PER_FSEL_13 0x03 255819833afSPeter Tyser #define PER_M2_13 0x09 256819833afSPeter Tyser 257819833afSPeter Tyser #define PER_M_19P2 0xE1 258819833afSPeter Tyser #define PER_N_19P2 0x09 259819833afSPeter Tyser #define PER_FSEL_19P2 0x07 260819833afSPeter Tyser #define PER_M2_19P2 0x09 261819833afSPeter Tyser 262819833afSPeter Tyser #define PER_M_26 0xD8 263819833afSPeter Tyser #define PER_N_26 0x0C 264819833afSPeter Tyser #define PER_FSEL_26 0x07 265819833afSPeter Tyser #define PER_M2_26 0x09 266819833afSPeter Tyser 267819833afSPeter Tyser #define PER_M_38P4 0xE1 268819833afSPeter Tyser #define PER_N_38P4 0x13 269819833afSPeter Tyser #define PER_FSEL_38P4 0x07 270819833afSPeter Tyser #define PER_M2_38P4 0x09 271819833afSPeter Tyser 2727b89795fSAlexander Holler /* PER2 DPLL */ 2737b89795fSAlexander Holler #define PER2_M_12 0x78 2747b89795fSAlexander Holler #define PER2_N_12 0x0B 2757b89795fSAlexander Holler #define PER2_FSEL_12 0x03 2767b89795fSAlexander Holler #define PER2_M2_12 0x01 2777b89795fSAlexander Holler 2787b89795fSAlexander Holler #define PER2_M_13 0x78 2797b89795fSAlexander Holler #define PER2_N_13 0x0C 2807b89795fSAlexander Holler #define PER2_FSEL_13 0x03 2817b89795fSAlexander Holler #define PER2_M2_13 0x01 2827b89795fSAlexander Holler 2837b89795fSAlexander Holler #define PER2_M_19P2 0x2EE 2847b89795fSAlexander Holler #define PER2_N_19P2 0x0B 2857b89795fSAlexander Holler #define PER2_FSEL_19P2 0x06 2867b89795fSAlexander Holler #define PER2_M2_19P2 0x0A 2877b89795fSAlexander Holler 2887b89795fSAlexander Holler #define PER2_M_26 0x78 2897b89795fSAlexander Holler #define PER2_N_26 0x0C 2907b89795fSAlexander Holler #define PER2_FSEL_26 0x03 2917b89795fSAlexander Holler #define PER2_M2_26 0x01 2927b89795fSAlexander Holler 2937b89795fSAlexander Holler #define PER2_M_38P4 0x2EE 2947b89795fSAlexander Holler #define PER2_N_38P4 0x0B 2957b89795fSAlexander Holler #define PER2_FSEL_38P4 0x06 2967b89795fSAlexander Holler #define PER2_M2_38P4 0x0A 2977b89795fSAlexander Holler 2987c281c98SSteve Sakoman /* 36XX PER DPLL */ 2997c281c98SSteve Sakoman 3007c281c98SSteve Sakoman #define PER_36XX_M_12 0x1B0 3017c281c98SSteve Sakoman #define PER_36XX_N_12 0x05 3027c281c98SSteve Sakoman #define PER_36XX_FSEL_12 0x07 3037c281c98SSteve Sakoman #define PER_36XX_M2_12 0x09 3047c281c98SSteve Sakoman 3057c281c98SSteve Sakoman #define PER_36XX_M_13 0x360 3067c281c98SSteve Sakoman #define PER_36XX_N_13 0x0C 3077c281c98SSteve Sakoman #define PER_36XX_FSEL_13 0x03 3087c281c98SSteve Sakoman #define PER_36XX_M2_13 0x09 3097c281c98SSteve Sakoman 3107c281c98SSteve Sakoman #define PER_36XX_M_19P2 0x1C2 3117c281c98SSteve Sakoman #define PER_36XX_N_19P2 0x09 3127c281c98SSteve Sakoman #define PER_36XX_FSEL_19P2 0x07 3137c281c98SSteve Sakoman #define PER_36XX_M2_19P2 0x09 3147c281c98SSteve Sakoman 3157c281c98SSteve Sakoman #define PER_36XX_M_26 0x1B0 3167c281c98SSteve Sakoman #define PER_36XX_N_26 0x0C 3177c281c98SSteve Sakoman #define PER_36XX_FSEL_26 0x07 3187c281c98SSteve Sakoman #define PER_36XX_M2_26 0x09 3197c281c98SSteve Sakoman 3207c281c98SSteve Sakoman #define PER_36XX_M_38P4 0x1C2 3217c281c98SSteve Sakoman #define PER_36XX_N_38P4 0x13 3227c281c98SSteve Sakoman #define PER_36XX_FSEL_38P4 0x07 3237c281c98SSteve Sakoman #define PER_36XX_M2_38P4 0x09 3247c281c98SSteve Sakoman 325a704a6d6SNaumann Andreas /* 36XX PER2 DPLL */ 326a704a6d6SNaumann Andreas 327a704a6d6SNaumann Andreas #define PER2_36XX_M_12 0x50 328a704a6d6SNaumann Andreas #define PER2_36XX_N_12 0x00 329a704a6d6SNaumann Andreas #define PER2_36XX_M2_12 0x08 330a704a6d6SNaumann Andreas 331a704a6d6SNaumann Andreas #define PER2_36XX_M_13 0x1BB 332a704a6d6SNaumann Andreas #define PER2_36XX_N_13 0x05 333a704a6d6SNaumann Andreas #define PER2_36XX_M2_13 0x08 334a704a6d6SNaumann Andreas 335a704a6d6SNaumann Andreas #define PER2_36XX_M_19P2 0x32 336a704a6d6SNaumann Andreas #define PER2_36XX_N_19P2 0x00 337a704a6d6SNaumann Andreas #define PER2_36XX_M2_19P2 0x08 338a704a6d6SNaumann Andreas 339a704a6d6SNaumann Andreas #define PER2_36XX_M_26 0x1BB 340a704a6d6SNaumann Andreas #define PER2_36XX_N_26 0x0B 341a704a6d6SNaumann Andreas #define PER2_36XX_M2_26 0x08 342a704a6d6SNaumann Andreas 343a704a6d6SNaumann Andreas #define PER2_36XX_M_38P4 0x19 344a704a6d6SNaumann Andreas #define PER2_36XX_N_38P4 0x00 345a704a6d6SNaumann Andreas #define PER2_36XX_M2_38P4 0x08 346a704a6d6SNaumann Andreas 347819833afSPeter Tyser #endif /* endif _CLOCKS_OMAP3_H_ */ 348