1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2006-2008 3819833afSPeter Tyser * Texas Instruments, <www.ti.com> 4819833afSPeter Tyser * Richard Woodruff <r-woodruff2@ti.com> 5819833afSPeter Tyser * 6819833afSPeter Tyser * This program is free software; you can redistribute it and/or 7819833afSPeter Tyser * modify it under the terms of the GNU General Public License as 8819833afSPeter Tyser * published by the Free Software Foundation; either version 2 of 9819833afSPeter Tyser * the License, or (at your option) any later version. 10819833afSPeter Tyser * 11819833afSPeter Tyser * This program is distributed in the hope that it will be useful, 12819833afSPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 13819833afSPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 14819833afSPeter Tyser * GNU General Public License for more details. 15819833afSPeter Tyser * 16819833afSPeter Tyser * You should have received a copy of the GNU General Public License 17819833afSPeter Tyser * along with this program; if not, write to the Free Software 18819833afSPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19819833afSPeter Tyser * MA 02111-1307 USA 20819833afSPeter Tyser */ 21819833afSPeter Tyser #ifndef _CLOCKS_OMAP3_H_ 22819833afSPeter Tyser #define _CLOCKS_OMAP3_H_ 23819833afSPeter Tyser 24819833afSPeter Tyser #define PLL_STOP 1 /* PER & IVA */ 25819833afSPeter Tyser #define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ 26819833afSPeter Tyser #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ 27819833afSPeter Tyser #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ 28819833afSPeter Tyser 29819833afSPeter Tyser /* 30819833afSPeter Tyser * The following configurations are OPP and SysClk value independant 31819833afSPeter Tyser * and hence are defined here. All the other DPLL related values are 32819833afSPeter Tyser * tabulated in lowlevel_init.S. 33819833afSPeter Tyser */ 34819833afSPeter Tyser 35819833afSPeter Tyser /* CORE DPLL */ 36819833afSPeter Tyser #define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ 37819833afSPeter Tyser #define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ 38819833afSPeter Tyser #define CORE_FUSB_DIV 2 /* 41.5MHz: */ 39819833afSPeter Tyser #define CORE_L4_DIV 2 /* 83MHz : L4 */ 40819833afSPeter Tyser #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ 41819833afSPeter Tyser #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ 42819833afSPeter Tyser #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ 43819833afSPeter Tyser 44819833afSPeter Tyser /* PER DPLL */ 45819833afSPeter Tyser #define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ 46819833afSPeter Tyser #define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ 47819833afSPeter Tyser #define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ 48819833afSPeter Tyser #define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ 49819833afSPeter Tyser 50819833afSPeter Tyser #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) 51819833afSPeter Tyser 52819833afSPeter Tyser /* MPU DPLL */ 53819833afSPeter Tyser 54819833afSPeter Tyser #define MPU_M_12_ES1 0x0FE 55819833afSPeter Tyser #define MPU_N_12_ES1 0x07 56819833afSPeter Tyser #define MPU_FSEL_12_ES1 0x05 57819833afSPeter Tyser #define MPU_M2_12_ES1 0x01 58819833afSPeter Tyser 59819833afSPeter Tyser #define MPU_M_12_ES2 0x0FA 60819833afSPeter Tyser #define MPU_N_12_ES2 0x05 61819833afSPeter Tyser #define MPU_FSEL_12_ES2 0x07 62819833afSPeter Tyser #define MPU_M2_ES2 0x01 63819833afSPeter Tyser 64819833afSPeter Tyser #define MPU_M_12 0x085 65819833afSPeter Tyser #define MPU_N_12 0x05 66819833afSPeter Tyser #define MPU_FSEL_12 0x07 67819833afSPeter Tyser #define MPU_M2_12 0x01 68819833afSPeter Tyser 69819833afSPeter Tyser #define MPU_M_13_ES1 0x17D 70819833afSPeter Tyser #define MPU_N_13_ES1 0x0C 71819833afSPeter Tyser #define MPU_FSEL_13_ES1 0x03 72819833afSPeter Tyser #define MPU_M2_13_ES1 0x01 73819833afSPeter Tyser 74819833afSPeter Tyser #define MPU_M_13_ES2 0x1F4 75819833afSPeter Tyser #define MPU_N_13_ES2 0x0C 76819833afSPeter Tyser #define MPU_FSEL_13_ES2 0x03 77819833afSPeter Tyser #define MPU_M2_13_ES2 0x01 78819833afSPeter Tyser 79819833afSPeter Tyser #define MPU_M_13 0x10A 80819833afSPeter Tyser #define MPU_N_13 0x0C 81819833afSPeter Tyser #define MPU_FSEL_13 0x03 82819833afSPeter Tyser #define MPU_M2_13 0x01 83819833afSPeter Tyser 84819833afSPeter Tyser #define MPU_M_19P2_ES1 0x179 85819833afSPeter Tyser #define MPU_N_19P2_ES1 0x12 86819833afSPeter Tyser #define MPU_FSEL_19P2_ES1 0x04 87819833afSPeter Tyser #define MPU_M2_19P2_ES1 0x01 88819833afSPeter Tyser 89819833afSPeter Tyser #define MPU_M_19P2_ES2 0x271 90819833afSPeter Tyser #define MPU_N_19P2_ES2 0x17 91819833afSPeter Tyser #define MPU_FSEL_19P2_ES2 0x03 92819833afSPeter Tyser #define MPU_M2_19P2_ES2 0x01 93819833afSPeter Tyser 94819833afSPeter Tyser #define MPU_M_19P2 0x14C 95819833afSPeter Tyser #define MPU_N_19P2 0x17 96819833afSPeter Tyser #define MPU_FSEL_19P2 0x03 97819833afSPeter Tyser #define MPU_M2_19P2 0x01 98819833afSPeter Tyser 99819833afSPeter Tyser #define MPU_M_26_ES1 0x17D 100819833afSPeter Tyser #define MPU_N_26_ES1 0x19 101819833afSPeter Tyser #define MPU_FSEL_26_ES1 0x03 102819833afSPeter Tyser #define MPU_M2_26_ES1 0x01 103819833afSPeter Tyser 104819833afSPeter Tyser #define MPU_M_26_ES2 0x0FA 105819833afSPeter Tyser #define MPU_N_26_ES2 0x0C 106819833afSPeter Tyser #define MPU_FSEL_26_ES2 0x07 107819833afSPeter Tyser #define MPU_M2_26_ES2 0x01 108819833afSPeter Tyser 109819833afSPeter Tyser #define MPU_M_26 0x085 110819833afSPeter Tyser #define MPU_N_26 0x0C 111819833afSPeter Tyser #define MPU_FSEL_26 0x07 112819833afSPeter Tyser #define MPU_M2_26 0x01 113819833afSPeter Tyser 114819833afSPeter Tyser #define MPU_M_38P4_ES1 0x1FA 115819833afSPeter Tyser #define MPU_N_38P4_ES1 0x32 116819833afSPeter Tyser #define MPU_FSEL_38P4_ES1 0x03 117819833afSPeter Tyser #define MPU_M2_38P4_ES1 0x01 118819833afSPeter Tyser 119819833afSPeter Tyser #define MPU_M_38P4_ES2 0x271 120819833afSPeter Tyser #define MPU_N_38P4_ES2 0x2F 121819833afSPeter Tyser #define MPU_FSEL_38P4_ES2 0x03 122819833afSPeter Tyser #define MPU_M2_38P4_ES2 0x01 123819833afSPeter Tyser 124819833afSPeter Tyser #define MPU_M_38P4 0x14C 125819833afSPeter Tyser #define MPU_N_38P4 0x2F 126819833afSPeter Tyser #define MPU_FSEL_38P4 0x03 127819833afSPeter Tyser #define MPU_M2_38P4 0x01 128819833afSPeter Tyser 129819833afSPeter Tyser /* IVA DPLL */ 130819833afSPeter Tyser 131819833afSPeter Tyser #define IVA_M_12_ES1 0x07D 132819833afSPeter Tyser #define IVA_N_12_ES1 0x05 133819833afSPeter Tyser #define IVA_FSEL_12_ES1 0x07 134819833afSPeter Tyser #define IVA_M2_12_ES1 0x01 135819833afSPeter Tyser 136819833afSPeter Tyser #define IVA_M_12_ES2 0x0B4 137819833afSPeter Tyser #define IVA_N_12_ES2 0x05 138819833afSPeter Tyser #define IVA_FSEL_12_ES2 0x07 139819833afSPeter Tyser #define IVA_M2_12_ES2 0x01 140819833afSPeter Tyser 141819833afSPeter Tyser #define IVA_M_12 0x085 142819833afSPeter Tyser #define IVA_N_12 0x05 143819833afSPeter Tyser #define IVA_FSEL_12 0x07 144819833afSPeter Tyser #define IVA_M2_12 0x01 145819833afSPeter Tyser 146819833afSPeter Tyser #define IVA_M_13_ES1 0x0FA 147819833afSPeter Tyser #define IVA_N_13_ES1 0x0C 148819833afSPeter Tyser #define IVA_FSEL_13_ES1 0x03 149819833afSPeter Tyser #define IVA_M2_13_ES1 0x01 150819833afSPeter Tyser 151819833afSPeter Tyser #define IVA_M_13_ES2 0x168 152819833afSPeter Tyser #define IVA_N_13_ES2 0x0C 153819833afSPeter Tyser #define IVA_FSEL_13_ES2 0x03 154819833afSPeter Tyser #define IVA_M2_13_ES2 0x01 155819833afSPeter Tyser 156819833afSPeter Tyser #define IVA_M_13 0x10A 157819833afSPeter Tyser #define IVA_N_13 0x0C 158819833afSPeter Tyser #define IVA_FSEL_13 0x03 159819833afSPeter Tyser #define IVA_M2_13 0x01 160819833afSPeter Tyser 161819833afSPeter Tyser #define IVA_M_19P2_ES1 0x082 162819833afSPeter Tyser #define IVA_N_19P2_ES1 0x09 163819833afSPeter Tyser #define IVA_FSEL_19P2_ES1 0x07 164819833afSPeter Tyser #define IVA_M2_19P2_ES1 0x01 165819833afSPeter Tyser 166819833afSPeter Tyser #define IVA_M_19P2_ES2 0x0E1 167819833afSPeter Tyser #define IVA_N_19P2_ES2 0x0B 168819833afSPeter Tyser #define IVA_FSEL_19P2_ES2 0x06 169819833afSPeter Tyser #define IVA_M2_19P2_ES2 0x01 170819833afSPeter Tyser 171819833afSPeter Tyser #define IVA_M_19P2 0x14C 172819833afSPeter Tyser #define IVA_N_19P2 0x17 173819833afSPeter Tyser #define IVA_FSEL_19P2 0x03 174819833afSPeter Tyser #define IVA_M2_19P2 0x01 175819833afSPeter Tyser 176819833afSPeter Tyser #define IVA_M_26_ES1 0x07D 177819833afSPeter Tyser #define IVA_N_26_ES1 0x0C 178819833afSPeter Tyser #define IVA_FSEL_26_ES1 0x07 179819833afSPeter Tyser #define IVA_M2_26_ES1 0x01 180819833afSPeter Tyser 181819833afSPeter Tyser #define IVA_M_26_ES2 0x0B4 182819833afSPeter Tyser #define IVA_N_26_ES2 0x0C 183819833afSPeter Tyser #define IVA_FSEL_26_ES2 0x07 184819833afSPeter Tyser #define IVA_M2_26_ES2 0x01 185819833afSPeter Tyser 186819833afSPeter Tyser #define IVA_M_26 0x085 187819833afSPeter Tyser #define IVA_N_26 0x0C 188819833afSPeter Tyser #define IVA_FSEL_26 0x07 189819833afSPeter Tyser #define IVA_M2_26 0x01 190819833afSPeter Tyser 191819833afSPeter Tyser #define IVA_M_38P4_ES1 0x13F 192819833afSPeter Tyser #define IVA_N_38P4_ES1 0x30 193819833afSPeter Tyser #define IVA_FSEL_38P4_ES1 0x03 194819833afSPeter Tyser #define IVA_M2_38P4_ES1 0x01 195819833afSPeter Tyser 196819833afSPeter Tyser #define IVA_M_38P4_ES2 0x0E1 197819833afSPeter Tyser #define IVA_N_38P4_ES2 0x17 198819833afSPeter Tyser #define IVA_FSEL_38P4_ES2 0x06 199819833afSPeter Tyser #define IVA_M2_38P4_ES2 0x01 200819833afSPeter Tyser 201819833afSPeter Tyser #define IVA_M_38P4 0x14C 202819833afSPeter Tyser #define IVA_N_38P4 0x2F 203819833afSPeter Tyser #define IVA_FSEL_38P4 0x03 204819833afSPeter Tyser #define IVA_M2_38P4 0x01 205819833afSPeter Tyser 206819833afSPeter Tyser /* CORE DPLL */ 207819833afSPeter Tyser 208819833afSPeter Tyser #define CORE_M_12 0xA6 209819833afSPeter Tyser #define CORE_N_12 0x05 210819833afSPeter Tyser #define CORE_FSEL_12 0x07 211819833afSPeter Tyser #define CORE_M2_12 0x01 /* M3 of 2 */ 212819833afSPeter Tyser 213819833afSPeter Tyser #define CORE_M_12_ES1 0x19F 214819833afSPeter Tyser #define CORE_N_12_ES1 0x0E 215819833afSPeter Tyser #define CORE_FSL_12_ES1 0x03 216819833afSPeter Tyser #define CORE_M2_12_ES1 0x1 /* M3 of 2 */ 217819833afSPeter Tyser 218819833afSPeter Tyser #define CORE_M_13 0x14C 219819833afSPeter Tyser #define CORE_N_13 0x0C 220819833afSPeter Tyser #define CORE_FSEL_13 0x03 221819833afSPeter Tyser #define CORE_M2_13 0x01 /* M3 of 2 */ 222819833afSPeter Tyser 223819833afSPeter Tyser #define CORE_M_13_ES1 0x1B2 224819833afSPeter Tyser #define CORE_N_13_ES1 0x10 225819833afSPeter Tyser #define CORE_FSL_13_ES1 0x03 226819833afSPeter Tyser #define CORE_M2_13_ES1 0x01 /* M3 of 2 */ 227819833afSPeter Tyser 228819833afSPeter Tyser #define CORE_M_19P2 0x19F 229819833afSPeter Tyser #define CORE_N_19P2 0x17 230819833afSPeter Tyser #define CORE_FSEL_19P2 0x03 231819833afSPeter Tyser #define CORE_M2_19P2 0x01 /* M3 of 2 */ 232819833afSPeter Tyser 233819833afSPeter Tyser #define CORE_M_19P2_ES1 0x19F 234819833afSPeter Tyser #define CORE_N_19P2_ES1 0x17 235819833afSPeter Tyser #define CORE_FSL_19P2_ES1 0x03 236819833afSPeter Tyser #define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ 237819833afSPeter Tyser 238819833afSPeter Tyser #define CORE_M_26 0xA6 239819833afSPeter Tyser #define CORE_N_26 0x0C 240819833afSPeter Tyser #define CORE_FSEL_26 0x07 241819833afSPeter Tyser #define CORE_M2_26 0x01 /* M3 of 2 */ 242819833afSPeter Tyser 243819833afSPeter Tyser #define CORE_M_26_ES1 0x1B2 244819833afSPeter Tyser #define CORE_N_26_ES1 0x21 245819833afSPeter Tyser #define CORE_FSL_26_ES1 0x03 246819833afSPeter Tyser #define CORE_M2_26_ES1 0x01 /* M3 of 2 */ 247819833afSPeter Tyser 248819833afSPeter Tyser #define CORE_M_38P4 0x19F 249819833afSPeter Tyser #define CORE_N_38P4 0x2F 250819833afSPeter Tyser #define CORE_FSEL_38P4 0x03 251819833afSPeter Tyser #define CORE_M2_38P4 0x01 /* M3 of 2 */ 252819833afSPeter Tyser 253819833afSPeter Tyser #define CORE_M_38P4_ES1 0x19F 254819833afSPeter Tyser #define CORE_N_38P4_ES1 0x2F 255819833afSPeter Tyser #define CORE_FSL_38P4_ES1 0x03 256819833afSPeter Tyser #define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ 257819833afSPeter Tyser 258819833afSPeter Tyser /* PER DPLL */ 259819833afSPeter Tyser 260819833afSPeter Tyser #define PER_M_12 0xD8 261819833afSPeter Tyser #define PER_N_12 0x05 262819833afSPeter Tyser #define PER_FSEL_12 0x07 263819833afSPeter Tyser #define PER_M2_12 0x09 264819833afSPeter Tyser 265819833afSPeter Tyser #define PER_M_13 0x1B0 266819833afSPeter Tyser #define PER_N_13 0x0C 267819833afSPeter Tyser #define PER_FSEL_13 0x03 268819833afSPeter Tyser #define PER_M2_13 0x09 269819833afSPeter Tyser 270819833afSPeter Tyser #define PER_M_19P2 0xE1 271819833afSPeter Tyser #define PER_N_19P2 0x09 272819833afSPeter Tyser #define PER_FSEL_19P2 0x07 273819833afSPeter Tyser #define PER_M2_19P2 0x09 274819833afSPeter Tyser 275819833afSPeter Tyser #define PER_M_26 0xD8 276819833afSPeter Tyser #define PER_N_26 0x0C 277819833afSPeter Tyser #define PER_FSEL_26 0x07 278819833afSPeter Tyser #define PER_M2_26 0x09 279819833afSPeter Tyser 280819833afSPeter Tyser #define PER_M_38P4 0xE1 281819833afSPeter Tyser #define PER_N_38P4 0x13 282819833afSPeter Tyser #define PER_FSEL_38P4 0x07 283819833afSPeter Tyser #define PER_M2_38P4 0x09 284819833afSPeter Tyser 285*7b89795fSAlexander Holler /* PER2 DPLL */ 286*7b89795fSAlexander Holler #define PER2_M_12 0x78 287*7b89795fSAlexander Holler #define PER2_N_12 0x0B 288*7b89795fSAlexander Holler #define PER2_FSEL_12 0x03 289*7b89795fSAlexander Holler #define PER2_M2_12 0x01 290*7b89795fSAlexander Holler 291*7b89795fSAlexander Holler #define PER2_M_13 0x78 292*7b89795fSAlexander Holler #define PER2_N_13 0x0C 293*7b89795fSAlexander Holler #define PER2_FSEL_13 0x03 294*7b89795fSAlexander Holler #define PER2_M2_13 0x01 295*7b89795fSAlexander Holler 296*7b89795fSAlexander Holler #define PER2_M_19P2 0x2EE 297*7b89795fSAlexander Holler #define PER2_N_19P2 0x0B 298*7b89795fSAlexander Holler #define PER2_FSEL_19P2 0x06 299*7b89795fSAlexander Holler #define PER2_M2_19P2 0x0A 300*7b89795fSAlexander Holler 301*7b89795fSAlexander Holler #define PER2_M_26 0x78 302*7b89795fSAlexander Holler #define PER2_N_26 0x0C 303*7b89795fSAlexander Holler #define PER2_FSEL_26 0x03 304*7b89795fSAlexander Holler #define PER2_M2_26 0x01 305*7b89795fSAlexander Holler 306*7b89795fSAlexander Holler #define PER2_M_38P4 0x2EE 307*7b89795fSAlexander Holler #define PER2_N_38P4 0x0B 308*7b89795fSAlexander Holler #define PER2_FSEL_38P4 0x06 309*7b89795fSAlexander Holler #define PER2_M2_38P4 0x0A 310*7b89795fSAlexander Holler 3117c281c98SSteve Sakoman /* 36XX PER DPLL */ 3127c281c98SSteve Sakoman 3137c281c98SSteve Sakoman #define PER_36XX_M_12 0x1B0 3147c281c98SSteve Sakoman #define PER_36XX_N_12 0x05 3157c281c98SSteve Sakoman #define PER_36XX_FSEL_12 0x07 3167c281c98SSteve Sakoman #define PER_36XX_M2_12 0x09 3177c281c98SSteve Sakoman 3187c281c98SSteve Sakoman #define PER_36XX_M_13 0x360 3197c281c98SSteve Sakoman #define PER_36XX_N_13 0x0C 3207c281c98SSteve Sakoman #define PER_36XX_FSEL_13 0x03 3217c281c98SSteve Sakoman #define PER_36XX_M2_13 0x09 3227c281c98SSteve Sakoman 3237c281c98SSteve Sakoman #define PER_36XX_M_19P2 0x1C2 3247c281c98SSteve Sakoman #define PER_36XX_N_19P2 0x09 3257c281c98SSteve Sakoman #define PER_36XX_FSEL_19P2 0x07 3267c281c98SSteve Sakoman #define PER_36XX_M2_19P2 0x09 3277c281c98SSteve Sakoman 3287c281c98SSteve Sakoman #define PER_36XX_M_26 0x1B0 3297c281c98SSteve Sakoman #define PER_36XX_N_26 0x0C 3307c281c98SSteve Sakoman #define PER_36XX_FSEL_26 0x07 3317c281c98SSteve Sakoman #define PER_36XX_M2_26 0x09 3327c281c98SSteve Sakoman 3337c281c98SSteve Sakoman #define PER_36XX_M_38P4 0x1C2 3347c281c98SSteve Sakoman #define PER_36XX_N_38P4 0x13 3357c281c98SSteve Sakoman #define PER_36XX_FSEL_38P4 0x07 3367c281c98SSteve Sakoman #define PER_36XX_M2_38P4 0x09 3377c281c98SSteve Sakoman 338819833afSPeter Tyser #endif /* endif _CLOCKS_OMAP3_H_ */ 339