1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a7e9c513SAjay Kumar Gupta /* 3a7e9c513SAjay Kumar Gupta * am35x_def.h - TI's AM35x specific definitions. 4a7e9c513SAjay Kumar Gupta * 5a7e9c513SAjay Kumar Gupta * Based on arch/arm/include/asm/arch-omap3/cpu.h 6a7e9c513SAjay Kumar Gupta * 7a7e9c513SAjay Kumar Gupta * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> 8a7e9c513SAjay Kumar Gupta * 9a7e9c513SAjay Kumar Gupta * Copyright (c) 2010 Texas Instruments Incorporated 10a7e9c513SAjay Kumar Gupta */ 11a7e9c513SAjay Kumar Gupta 12a7e9c513SAjay Kumar Gupta #ifndef _AM35X_DEF_H_ 13a7e9c513SAjay Kumar Gupta #define _AM35X_DEF_H_ 14a7e9c513SAjay Kumar Gupta 15a7e9c513SAjay Kumar Gupta #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 16a7e9c513SAjay Kumar Gupta #include <asm/types.h> 17a7e9c513SAjay Kumar Gupta #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 18a7e9c513SAjay Kumar Gupta 19a7e9c513SAjay Kumar Gupta #ifndef __KERNEL_STRICT_NAMES 20a7e9c513SAjay Kumar Gupta #ifndef __ASSEMBLY__ 21a7e9c513SAjay Kumar Gupta 22272165f6SIlya Yanok /* LVL_INTR_CLEAR bits */ 23272165f6SIlya Yanok #define USBOTGSS_INT_CLR (1 << 4) 24272165f6SIlya Yanok 25b9e65a79SIlya Yanok /* IP_SW_RESET bits */ 26272165f6SIlya Yanok #define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */ 27b9e65a79SIlya Yanok #define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ 28b9e65a79SIlya Yanok 29272165f6SIlya Yanok /* DEVCONF2 bits */ 30272165f6SIlya Yanok #define CONF2_PHY_GPIOMODE (1 << 23) 31272165f6SIlya Yanok #define CONF2_OTGMODE (3 << 14) 32272165f6SIlya Yanok #define CONF2_NO_OVERRIDE (0 << 14) 33272165f6SIlya Yanok #define CONF2_FORCE_HOST (1 << 14) 34272165f6SIlya Yanok #define CONF2_FORCE_DEVICE (2 << 14) 35272165f6SIlya Yanok #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) 36272165f6SIlya Yanok #define CONF2_SESENDEN (1 << 13) 37272165f6SIlya Yanok #define CONF2_VBDTCTEN (1 << 12) 38272165f6SIlya Yanok #define CONF2_REFFREQ_24MHZ (2 << 8) 39272165f6SIlya Yanok #define CONF2_REFFREQ_26MHZ (7 << 8) 40272165f6SIlya Yanok #define CONF2_REFFREQ_13MHZ (6 << 8) 41272165f6SIlya Yanok #define CONF2_REFFREQ (0xf << 8) 42272165f6SIlya Yanok #define CONF2_PHYCLKGD (1 << 7) 43272165f6SIlya Yanok #define CONF2_VBUSSENSE (1 << 6) 44272165f6SIlya Yanok #define CONF2_PHY_PLLON (1 << 5) 45272165f6SIlya Yanok #define CONF2_RESET (1 << 4) 46272165f6SIlya Yanok #define CONF2_PHYPWRDN (1 << 3) 47272165f6SIlya Yanok #define CONF2_OTGPWRDN (1 << 2) 48272165f6SIlya Yanok #define CONF2_DATPOL (1 << 1) 49272165f6SIlya Yanok 50a7e9c513SAjay Kumar Gupta /* General register mappings of system control module */ 51a7e9c513SAjay Kumar Gupta #define AM35X_SCM_GEN_BASE 0x48002270 52a7e9c513SAjay Kumar Gupta struct am35x_scm_general { 53a7e9c513SAjay Kumar Gupta u32 res1[0xC4]; /* 0x000 - 0x30C */ 54a7e9c513SAjay Kumar Gupta u32 devconf2; /* 0x310 */ 55a7e9c513SAjay Kumar Gupta u32 devconf3; /* 0x314 */ 56a7e9c513SAjay Kumar Gupta u32 res2[0x2]; /* 0x318 - 0x31C */ 57a7e9c513SAjay Kumar Gupta u32 cba_priority; /* 0x320 */ 58a7e9c513SAjay Kumar Gupta u32 lvl_intr_clr; /* 0x324 */ 59a7e9c513SAjay Kumar Gupta u32 ip_sw_reset; /* 0x328 */ 60a7e9c513SAjay Kumar Gupta u32 ipss_clk_ctrl; /* 0x32C */ 61a7e9c513SAjay Kumar Gupta }; 62a7e9c513SAjay Kumar Gupta #define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE) 63a7e9c513SAjay Kumar Gupta 64272165f6SIlya Yanok #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 65272165f6SIlya Yanok 66a7e9c513SAjay Kumar Gupta #endif /*__ASSEMBLY__ */ 67a7e9c513SAjay Kumar Gupta #endif /* __KERNEL_STRICT_NAMES */ 68a7e9c513SAjay Kumar Gupta 69a7e9c513SAjay Kumar Gupta #endif /* _AM35X_DEF_H_ */ 70