1a7e9c513SAjay Kumar Gupta /* 2a7e9c513SAjay Kumar Gupta * am35x_def.h - TI's AM35x specific definitions. 3a7e9c513SAjay Kumar Gupta * 4a7e9c513SAjay Kumar Gupta * Based on arch/arm/include/asm/arch-omap3/cpu.h 5a7e9c513SAjay Kumar Gupta * 6a7e9c513SAjay Kumar Gupta * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> 7a7e9c513SAjay Kumar Gupta * 8a7e9c513SAjay Kumar Gupta * Copyright (c) 2010 Texas Instruments Incorporated 9a7e9c513SAjay Kumar Gupta * 10a7e9c513SAjay Kumar Gupta * This program is free software; you can redistribute it and/or modify 11a7e9c513SAjay Kumar Gupta * it under the terms of the GNU General Public License as published by 12a7e9c513SAjay Kumar Gupta * the Free Software Foundation; either version 2 of the License, or 13a7e9c513SAjay Kumar Gupta * (at your option) any later version. 14a7e9c513SAjay Kumar Gupta * 15a7e9c513SAjay Kumar Gupta * This program is distributed in the hope that it will be useful, 16a7e9c513SAjay Kumar Gupta * but WITHOUT ANY WARRANTY; without even the implied warranty of 17a7e9c513SAjay Kumar Gupta * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18a7e9c513SAjay Kumar Gupta * GNU General Public License for more details. 19a7e9c513SAjay Kumar Gupta * 20a7e9c513SAjay Kumar Gupta * You should have received a copy of the GNU General Public License 21a7e9c513SAjay Kumar Gupta * along with this program; if not, write to the Free Software 22a7e9c513SAjay Kumar Gupta * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23a7e9c513SAjay Kumar Gupta */ 24a7e9c513SAjay Kumar Gupta 25a7e9c513SAjay Kumar Gupta #ifndef _AM35X_DEF_H_ 26a7e9c513SAjay Kumar Gupta #define _AM35X_DEF_H_ 27a7e9c513SAjay Kumar Gupta 28a7e9c513SAjay Kumar Gupta #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 29a7e9c513SAjay Kumar Gupta #include <asm/types.h> 30a7e9c513SAjay Kumar Gupta #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 31a7e9c513SAjay Kumar Gupta 32a7e9c513SAjay Kumar Gupta #ifndef __KERNEL_STRICT_NAMES 33a7e9c513SAjay Kumar Gupta #ifndef __ASSEMBLY__ 34a7e9c513SAjay Kumar Gupta 35*272165f6SIlya Yanok /* LVL_INTR_CLEAR bits */ 36*272165f6SIlya Yanok #define USBOTGSS_INT_CLR (1 << 4) 37*272165f6SIlya Yanok 38b9e65a79SIlya Yanok /* IP_SW_RESET bits */ 39*272165f6SIlya Yanok #define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */ 40b9e65a79SIlya Yanok #define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ 41b9e65a79SIlya Yanok 42*272165f6SIlya Yanok /* DEVCONF2 bits */ 43*272165f6SIlya Yanok #define CONF2_PHY_GPIOMODE (1 << 23) 44*272165f6SIlya Yanok #define CONF2_OTGMODE (3 << 14) 45*272165f6SIlya Yanok #define CONF2_NO_OVERRIDE (0 << 14) 46*272165f6SIlya Yanok #define CONF2_FORCE_HOST (1 << 14) 47*272165f6SIlya Yanok #define CONF2_FORCE_DEVICE (2 << 14) 48*272165f6SIlya Yanok #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) 49*272165f6SIlya Yanok #define CONF2_SESENDEN (1 << 13) 50*272165f6SIlya Yanok #define CONF2_VBDTCTEN (1 << 12) 51*272165f6SIlya Yanok #define CONF2_REFFREQ_24MHZ (2 << 8) 52*272165f6SIlya Yanok #define CONF2_REFFREQ_26MHZ (7 << 8) 53*272165f6SIlya Yanok #define CONF2_REFFREQ_13MHZ (6 << 8) 54*272165f6SIlya Yanok #define CONF2_REFFREQ (0xf << 8) 55*272165f6SIlya Yanok #define CONF2_PHYCLKGD (1 << 7) 56*272165f6SIlya Yanok #define CONF2_VBUSSENSE (1 << 6) 57*272165f6SIlya Yanok #define CONF2_PHY_PLLON (1 << 5) 58*272165f6SIlya Yanok #define CONF2_RESET (1 << 4) 59*272165f6SIlya Yanok #define CONF2_PHYPWRDN (1 << 3) 60*272165f6SIlya Yanok #define CONF2_OTGPWRDN (1 << 2) 61*272165f6SIlya Yanok #define CONF2_DATPOL (1 << 1) 62*272165f6SIlya Yanok 63a7e9c513SAjay Kumar Gupta /* General register mappings of system control module */ 64a7e9c513SAjay Kumar Gupta #define AM35X_SCM_GEN_BASE 0x48002270 65a7e9c513SAjay Kumar Gupta struct am35x_scm_general { 66a7e9c513SAjay Kumar Gupta u32 res1[0xC4]; /* 0x000 - 0x30C */ 67a7e9c513SAjay Kumar Gupta u32 devconf2; /* 0x310 */ 68a7e9c513SAjay Kumar Gupta u32 devconf3; /* 0x314 */ 69a7e9c513SAjay Kumar Gupta u32 res2[0x2]; /* 0x318 - 0x31C */ 70a7e9c513SAjay Kumar Gupta u32 cba_priority; /* 0x320 */ 71a7e9c513SAjay Kumar Gupta u32 lvl_intr_clr; /* 0x324 */ 72a7e9c513SAjay Kumar Gupta u32 ip_sw_reset; /* 0x328 */ 73a7e9c513SAjay Kumar Gupta u32 ipss_clk_ctrl; /* 0x32C */ 74a7e9c513SAjay Kumar Gupta }; 75a7e9c513SAjay Kumar Gupta #define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE) 76a7e9c513SAjay Kumar Gupta 77*272165f6SIlya Yanok #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 78*272165f6SIlya Yanok 79a7e9c513SAjay Kumar Gupta #endif /*__ASSEMBLY__ */ 80a7e9c513SAjay Kumar Gupta #endif /* __KERNEL_STRICT_NAMES */ 81a7e9c513SAjay Kumar Gupta 82a7e9c513SAjay Kumar Gupta #endif /* _AM35X_DEF_H_ */ 83