1 /*
2  * Freescale i.MX23/i.MX28 specific functions
3  *
4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __SYS_PROTO_H__
11 #define __SYS_PROTO_H__
12 
13 #include <asm/imx-common/regs-common.h>
14 
15 int mxs_reset_block(struct mxs_register_32 *reg);
16 int mxs_wait_mask_set(struct mxs_register_32 *reg,
17 		       uint32_t mask,
18 		       unsigned int timeout);
19 int mxs_wait_mask_clr(struct mxs_register_32 *reg,
20 		       uint32_t mask,
21 		       unsigned int timeout);
22 
23 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
24 
25 #ifdef CONFIG_SPL_BUILD
26 
27 #if defined(CONFIG_MX23)
28 #include <asm/arch/iomux-mx23.h>
29 #elif defined(CONFIG_MX28)
30 #include <asm/arch/iomux-mx28.h>
31 #endif
32 
33 void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
34 			 const iomux_cfg_t *iomux_setup,
35 			 const unsigned int iomux_size);
36 #endif
37 
38 struct mxs_pair {
39 	uint8_t	boot_pads;
40 	uint8_t boot_mask;
41 	const char *mode;
42 };
43 
44 static const struct mxs_pair mxs_boot_modes[] = {
45 #if defined(CONFIG_MX23)
46 	{ 0x00, 0x0f, "USB" },
47 	{ 0x01, 0x1f, "I2C, master" },
48 	{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
49 	{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
50 	{ 0x04, 0x1f, "NAND" },
51 	{ 0x06, 0x1f, "JTAG" },
52 	{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
53 	{ 0x09, 0x1f, "SSP SD/MMC #0" },
54 	{ 0x0a, 0x1f, "SSP SD/MMC #1" },
55 	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
56 #elif defined(CONFIG_MX28)
57 	{ 0x00, 0x0f, "USB #0" },
58 	{ 0x01, 0x1f, "I2C #0, master, 3V3" },
59 	{ 0x11, 0x1f, "I2C #0, master, 1V8" },
60 	{ 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
61 	{ 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
62 	{ 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
63 	{ 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
64 	{ 0x04, 0x1f, "NAND, 3V3" },
65 	{ 0x14, 0x1f, "NAND, 1V8" },
66 	{ 0x06, 0x1f, "JTAG" },
67 	{ 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
68 	{ 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
69 	{ 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
70 	{ 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
71 	{ 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
72 	{ 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
73 	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
74 #endif
75 };
76 
77 #define MXS_BM_USB			0x00
78 #define MXS_BM_I2C_MASTER_3V3		0x01
79 #define MXS_BM_I2C_MASTER_1V8		0x11
80 #define MXS_BM_SPI2_MASTER_3V3_NOR	0x02
81 #define MXS_BM_SPI2_MASTER_1V8_NOR	0x12
82 #define MXS_BM_SPI3_MASTER_3V3_NOR	0x03
83 #define MXS_BM_SPI3_MASTER_1V8_NOR	0x13
84 #define MXS_BM_NAND_3V3			0x04
85 #define MXS_BM_NAND_1V8			0x14
86 #define MXS_BM_JTAG			0x06
87 #define MXS_BM_SPI3_MASTER_3V3_EEPROM	0x08
88 #define MXS_BM_SPI3_MASTER_1V8_EEPROM	0x18
89 #define MXS_BM_SDMMC0_3V3		0x09
90 #define MXS_BM_SDMMC0_1V8		0x19
91 #define MXS_BM_SDMMC1_3V3		0x0a
92 #define MXS_BM_SDMMC1_1V8		0x1a
93 
94 struct mxs_spl_data {
95 	uint8_t		boot_mode_idx;
96 	uint32_t	mem_dram_size;
97 };
98 
99 int mxs_dram_init(void);
100 
101 #endif	/* __SYS_PROTO_H__ */
102