1 /* 2 * Freescale MXS UARTAPP Register Definitions 3 * 4 * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com> 5 * 6 * Based on code from LTIB: 7 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __ARCH_ARM___MXS_UARTAPP_H 13 #define __ARCH_ARM___MXS_UARTAPP_H 14 15 #include <asm/mach-imx/regs-common.h> 16 17 #ifndef __ASSEMBLY__ 18 struct mxs_uartapp_regs { 19 mxs_reg_32(hw_uartapp_ctrl0) 20 mxs_reg_32(hw_uartapp_ctrl1) 21 mxs_reg_32(hw_uartapp_ctrl2) 22 mxs_reg_32(hw_uartapp_linectrl) 23 mxs_reg_32(hw_uartapp_linectrl2) 24 mxs_reg_32(hw_uartapp_intr) 25 mxs_reg_32(hw_uartapp_data) 26 mxs_reg_32(hw_uartapp_stat) 27 mxs_reg_32(hw_uartapp_debug) 28 mxs_reg_32(hw_uartapp_version) 29 mxs_reg_32(hw_uartapp_autobaud) 30 }; 31 #endif 32 33 #define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) 34 #define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) 35 #define UARTAPP_CTRL0_RUN_MASK (1 << 29) 36 #define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) 37 #define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) 38 #define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 39 #define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) 40 #define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 41 #define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF 42 43 #define UARTAPP_CTRL1_RUN_MASK (1 << 28) 44 45 #define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 46 #define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF 47 48 #define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) 49 #define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) 50 #define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) 51 #define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) 52 #define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) 53 #define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) 54 #define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) 55 #define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) 56 #define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 57 #define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) 58 59 #define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) 60 #define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) 61 #define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) 62 #define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) 63 #define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) 64 #define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) 65 #define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) 66 #define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) 67 #define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 68 #define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) 69 #define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) 70 #define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) 71 #define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) 72 #define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) 73 #define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) 74 #define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) 75 #define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) 76 #define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) 77 #define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) 78 #define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) 79 #define UARTAPP_CTRL2_OUT2_MASK (1 << 13) 80 #define UARTAPP_CTRL2_OUT1_MASK (1 << 12) 81 #define UARTAPP_CTRL2_RTS_MASK (1 << 11) 82 #define UARTAPP_CTRL2_DTR_MASK (1 << 10) 83 #define UARTAPP_CTRL2_RXE_MASK (1 << 9) 84 #define UARTAPP_CTRL2_TXE_MASK (1 << 8) 85 #define UARTAPP_CTRL2_LBE_MASK (1 << 7) 86 #define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) 87 88 #define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) 89 #define UARTAPP_CTRL2_SIREN_MASK (1 << 1) 90 #define UARTAPP_CTRL2_UARTEN_MASK 0x01 91 92 #define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 93 #define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) 94 #define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 95 96 #define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 97 #define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) 98 #define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F 99 100 #define UARTAPP_LINECTRL_SPS_MASK (1 << 7) 101 #define UARTAPP_LINECTRL_WLEN_OFFSET 5 102 #define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) 103 #define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) 104 #define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) 105 #define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) 106 #define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) 107 108 #define UARTAPP_LINECTRL_FEN_MASK (1 << 4) 109 #define UARTAPP_LINECTRL_STP2_MASK (1 << 3) 110 #define UARTAPP_LINECTRL_EPS_MASK (1 << 2) 111 #define UARTAPP_LINECTRL_PEN_MASK (1 << 1) 112 #define UARTAPP_LINECTRL_BRK_MASK 1 113 114 #define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 115 #define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) 116 #define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 117 118 #define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 119 #define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) 120 #define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F 121 122 #define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) 123 #define UARTAPP_LINECTRL2_WLEN_OFFSET 5 124 #define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) 125 #define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) 126 #define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) 127 #define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) 128 #define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) 129 130 #define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) 131 #define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) 132 #define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) 133 #define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) 134 135 #define UARTAPP_INTR_ABDIEN_MASK (1 << 27) 136 #define UARTAPP_INTR_OEIEN_MASK (1 << 26) 137 #define UARTAPP_INTR_BEIEN_MASK (1 << 25) 138 #define UARTAPP_INTR_PEIEN_MASK (1 << 24) 139 #define UARTAPP_INTR_FEIEN_MASK (1 << 23) 140 #define UARTAPP_INTR_RTIEN_MASK (1 << 22) 141 #define UARTAPP_INTR_TXIEN_MASK (1 << 21) 142 #define UARTAPP_INTR_RXIEN_MASK (1 << 20) 143 #define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) 144 #define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) 145 #define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) 146 #define UARTAPP_INTR_RIMIEN_MASK (1 << 16) 147 148 #define UARTAPP_INTR_ABDIS_MASK (1 << 11) 149 #define UARTAPP_INTR_OEIS_MASK (1 << 10) 150 #define UARTAPP_INTR_BEIS_MASK (1 << 9) 151 #define UARTAPP_INTR_PEIS_MASK (1 << 8) 152 #define UARTAPP_INTR_FEIS_MASK (1 << 7) 153 #define UARTAPP_INTR_RTIS_MASK (1 << 6) 154 #define UARTAPP_INTR_TXIS_MASK (1 << 5) 155 #define UARTAPP_INTR_RXIS_MASK (1 << 4) 156 #define UARTAPP_INTR_DSRMIS_MASK (1 << 3) 157 #define UARTAPP_INTR_DCDMIS_MASK (1 << 2) 158 #define UARTAPP_INTR_CTSMIS_MASK (1 << 1) 159 #define UARTAPP_INTR_RIMIS_MASK 0x1 160 161 #define UARTAPP_DATA_DATA_OFFSET 0 162 #define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF 163 #define UARTAPP_STAT_PRESENT_MASK (1 << 31) 164 #define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) 165 #define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) 166 167 #define UARTAPP_STAT_HISPEED_MASK (1 << 30) 168 #define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) 169 #define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) 170 171 #define UARTAPP_STAT_BUSY_MASK (1 << 29) 172 #define UARTAPP_STAT_CTS_MASK (1 << 28) 173 #define UARTAPP_STAT_TXFE_MASK (1 << 27) 174 #define UARTAPP_STAT_RXFF_MASK (1 << 26) 175 #define UARTAPP_STAT_TXFF_MASK (1 << 25) 176 #define UARTAPP_STAT_RXFE_MASK (1 << 24) 177 #define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 178 #define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) 179 180 #define UARTAPP_STAT_OERR_MASK (1 << 19) 181 #define UARTAPP_STAT_BERR_MASK (1 << 18) 182 #define UARTAPP_STAT_PERR_MASK (1 << 17) 183 #define UARTAPP_STAT_FERR_MASK (1 << 16) 184 #define UARTAPP_STAT_RXCOUNT_OFFSET 0 185 #define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF 186 187 #define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 188 #define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) 189 190 #define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 191 #define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) 192 193 #define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) 194 #define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) 195 #define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) 196 #define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) 197 #define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) 198 #define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 199 200 #define UARTAPP_VERSION_MAJOR_OFFSET 24 201 #define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) 202 203 #define UARTAPP_VERSION_MINOR_OFFSET 16 204 #define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) 205 206 #define UARTAPP_VERSION_STEP_OFFSET 0 207 #define UARTAPP_VERSION_STEP_MASK 0xFFFF 208 209 #define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 210 #define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) 211 212 #define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 213 #define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) 214 215 #define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) 216 #define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) 217 #define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) 218 #define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) 219 #define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 220 #endif /* __ARCH_ARM___UARTAPP_H */ 221