1 /* 2 * Freescale i.MX28 TIMROT Register Definitions 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * Based on code from LTIB: 7 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 */ 24 25 #ifndef __MX28_REGS_TIMROT_H__ 26 #define __MX28_REGS_TIMROT_H__ 27 28 #include <asm/arch/regs-common.h> 29 30 #ifndef __ASSEMBLY__ 31 struct mxs_timrot_regs { 32 mxs_reg_32(hw_timrot_rotctrl) 33 mxs_reg_32(hw_timrot_rotcount) 34 mxs_reg_32(hw_timrot_timctrl0) 35 mxs_reg_32(hw_timrot_running_count0) 36 mxs_reg_32(hw_timrot_fixed_count0) 37 mxs_reg_32(hw_timrot_match_count0) 38 mxs_reg_32(hw_timrot_timctrl1) 39 mxs_reg_32(hw_timrot_running_count1) 40 mxs_reg_32(hw_timrot_fixed_count1) 41 mxs_reg_32(hw_timrot_match_count1) 42 mxs_reg_32(hw_timrot_timctrl2) 43 mxs_reg_32(hw_timrot_running_count2) 44 mxs_reg_32(hw_timrot_fixed_count2) 45 mxs_reg_32(hw_timrot_match_count2) 46 mxs_reg_32(hw_timrot_timctrl3) 47 mxs_reg_32(hw_timrot_running_count3) 48 mxs_reg_32(hw_timrot_fixed_count3) 49 mxs_reg_32(hw_timrot_match_count3) 50 mxs_reg_32(hw_timrot_version) 51 }; 52 #endif 53 54 #define TIMROT_ROTCTRL_SFTRST (1 << 31) 55 #define TIMROT_ROTCTRL_CLKGATE (1 << 30) 56 #define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) 57 #define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) 58 #define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) 59 #define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) 60 #define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) 61 #define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) 62 #define TIMROT_ROTCTRL_STATE_OFFSET 22 63 #define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) 64 #define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 65 #define TIMROT_ROTCTRL_RELATIVE (1 << 12) 66 #define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) 67 #define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 68 #define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) 69 #define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) 70 #define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) 71 #define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) 72 #define TIMROT_ROTCTRL_POLARITY_B (1 << 9) 73 #define TIMROT_ROTCTRL_POLARITY_A (1 << 8) 74 #define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) 75 #define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 76 #define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) 77 #define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) 78 #define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) 79 #define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) 80 #define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) 81 #define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) 82 #define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) 83 #define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) 84 #define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) 85 #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) 86 #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) 87 #define TIMROT_ROTCTRL_SELECT_A_MASK 0xf 88 #define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 89 #define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 90 #define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 91 #define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 92 #define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 93 #define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 94 #define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 95 #define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 96 #define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 97 #define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 98 #define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 99 #define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa 100 101 #define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff 102 #define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 103 104 #define TIMROT_TIMCTRLn_IRQ (1 << 15) 105 #define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) 106 #define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) 107 #define TIMROT_TIMCTRLn_POLARITY (1 << 8) 108 #define TIMROT_TIMCTRLn_UPDATE (1 << 7) 109 #define TIMROT_TIMCTRLn_RELOAD (1 << 6) 110 #define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) 111 #define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 112 #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) 113 #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) 114 #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) 115 #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) 116 #define TIMROT_TIMCTRLn_SELECT_MASK 0xf 117 #define TIMROT_TIMCTRLn_SELECT_OFFSET 0 118 #define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 119 #define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 120 #define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 121 #define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 122 #define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 123 #define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 124 #define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 125 #define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 126 #define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 127 #define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 128 #define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa 129 #define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb 130 #define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc 131 #define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd 132 #define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe 133 #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf 134 135 #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff 136 #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 137 138 #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff 139 #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 140 141 #define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff 142 #define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 143 144 #define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) 145 #define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 146 #define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) 147 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) 148 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) 149 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) 150 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) 151 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) 152 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) 153 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) 154 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) 155 #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) 156 #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) 157 #define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) 158 #define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) 159 #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) 160 #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) 161 #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) 162 #define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) 163 164 #define TIMROT_VERSION_MAJOR_MASK (0xff << 24) 165 #define TIMROT_VERSION_MAJOR_OFFSET 24 166 #define TIMROT_VERSION_MINOR_MASK (0xff << 16) 167 #define TIMROT_VERSION_MINOR_OFFSET 16 168 #define TIMROT_VERSION_STEP_MASK 0xffff 169 #define TIMROT_VERSION_STEP_OFFSET 0 170 171 #endif /* __MX28_REGS_TIMROT_H__ */ 172