1 /*
2  * Freescale i.MX28 SSP Register Definitions
3  *
4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * Based on code from LTIB:
7  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
22  *
23  */
24 
25 #ifndef __MX28_REGS_SSP_H__
26 #define __MX28_REGS_SSP_H__
27 
28 #include <asm/imx-common/regs-common.h>
29 
30 #ifndef	__ASSEMBLY__
31 #if defined(CONFIG_MX23)
32 struct mxs_ssp_regs {
33 	mxs_reg_32(hw_ssp_ctrl0)
34 	mxs_reg_32(hw_ssp_cmd0)
35 	mxs_reg_32(hw_ssp_cmd1)
36 	mxs_reg_32(hw_ssp_compref)
37 	mxs_reg_32(hw_ssp_compmask)
38 	mxs_reg_32(hw_ssp_timing)
39 	mxs_reg_32(hw_ssp_ctrl1)
40 	mxs_reg_32(hw_ssp_data)
41 	mxs_reg_32(hw_ssp_sdresp0)
42 	mxs_reg_32(hw_ssp_sdresp1)
43 	mxs_reg_32(hw_ssp_sdresp2)
44 	mxs_reg_32(hw_ssp_sdresp3)
45 	mxs_reg_32(hw_ssp_status)
46 
47 	uint32_t	reserved1[12];
48 
49 	mxs_reg_32(hw_ssp_debug)
50 	mxs_reg_32(hw_ssp_version)
51 };
52 #elif defined(CONFIG_MX28)
53 struct mxs_ssp_regs {
54 	mxs_reg_32(hw_ssp_ctrl0)
55 	mxs_reg_32(hw_ssp_cmd0)
56 	mxs_reg_32(hw_ssp_cmd1)
57 	mxs_reg_32(hw_ssp_xfer_size)
58 	mxs_reg_32(hw_ssp_block_size)
59 	mxs_reg_32(hw_ssp_compref)
60 	mxs_reg_32(hw_ssp_compmask)
61 	mxs_reg_32(hw_ssp_timing)
62 	mxs_reg_32(hw_ssp_ctrl1)
63 	mxs_reg_32(hw_ssp_data)
64 	mxs_reg_32(hw_ssp_sdresp0)
65 	mxs_reg_32(hw_ssp_sdresp1)
66 	mxs_reg_32(hw_ssp_sdresp2)
67 	mxs_reg_32(hw_ssp_sdresp3)
68 	mxs_reg_32(hw_ssp_ddr_ctrl)
69 	mxs_reg_32(hw_ssp_dll_ctrl)
70 	mxs_reg_32(hw_ssp_status)
71 	mxs_reg_32(hw_ssp_dll_sts)
72 	mxs_reg_32(hw_ssp_debug)
73 	mxs_reg_32(hw_ssp_version)
74 };
75 #endif
76 
77 static inline int mxs_ssp_bus_id_valid(int bus)
78 {
79 #if defined(CONFIG_MX23)
80 	const unsigned int mxs_ssp_chan_count = 2;
81 #elif defined(CONFIG_MX28)
82 	const unsigned int mxs_ssp_chan_count = 4;
83 #endif
84 
85 	if (bus >= mxs_ssp_chan_count)
86 		return 0;
87 
88 	if (bus < 0)
89 		return 0;
90 
91 	return 1;
92 }
93 
94 static inline int mxs_ssp_clock_by_bus(unsigned int clock)
95 {
96 #if defined(CONFIG_MX23)
97 	return 0;
98 #elif defined(CONFIG_MX28)
99 	return clock;
100 #endif
101 }
102 
103 static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
104 {
105 	switch (port) {
106 	case 0:
107 		return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
108 	case 1:
109 		return (struct mxs_ssp_regs *)MXS_SSP1_BASE;
110 #ifdef CONFIG_MX28
111 	case 2:
112 		return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
113 	case 3:
114 		return (struct mxs_ssp_regs *)MXS_SSP3_BASE;
115 #endif
116 	default:
117 		return NULL;
118 	}
119 }
120 #endif
121 
122 #define	SSP_CTRL0_SFTRST			(1 << 31)
123 #define	SSP_CTRL0_CLKGATE			(1 << 30)
124 #define	SSP_CTRL0_RUN				(1 << 29)
125 #define	SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)
126 #define	SSP_CTRL0_LOCK_CS			(1 << 27)
127 #define	SSP_CTRL0_IGNORE_CRC			(1 << 26)
128 #define	SSP_CTRL0_READ				(1 << 25)
129 #define	SSP_CTRL0_DATA_XFER			(1 << 24)
130 #define	SSP_CTRL0_BUS_WIDTH_MASK		(0x3 << 22)
131 #define	SSP_CTRL0_BUS_WIDTH_OFFSET		22
132 #define	SSP_CTRL0_BUS_WIDTH_ONE_BIT		(0x0 << 22)
133 #define	SSP_CTRL0_BUS_WIDTH_FOUR_BIT		(0x1 << 22)
134 #define	SSP_CTRL0_BUS_WIDTH_EIGHT_BIT		(0x2 << 22)
135 #define	SSP_CTRL0_WAIT_FOR_IRQ			(1 << 21)
136 #define	SSP_CTRL0_WAIT_FOR_CMD			(1 << 20)
137 #define	SSP_CTRL0_LONG_RESP			(1 << 19)
138 #define	SSP_CTRL0_CHECK_RESP			(1 << 18)
139 #define	SSP_CTRL0_GET_RESP			(1 << 17)
140 #define	SSP_CTRL0_ENABLE			(1 << 16)
141 
142 #ifdef CONFIG_MX23
143 #define	SSP_CTRL0_XFER_COUNT_OFFSET		0
144 #define	SSP_CTRL0_XFER_COUNT_MASK		0xffff
145 #endif
146 
147 #define	SSP_CMD0_SOFT_TERMINATE			(1 << 26)
148 #define	SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
149 #define	SSP_CMD0_PRIM_BOOT_OP_EN		(1 << 24)
150 #define	SSP_CMD0_BOOT_ACK_EN			(1 << 23)
151 #define	SSP_CMD0_SLOW_CLKING_EN			(1 << 22)
152 #define	SSP_CMD0_CONT_CLKING_EN			(1 << 21)
153 #define	SSP_CMD0_APPEND_8CYC			(1 << 20)
154 #if defined(CONFIG_MX23)
155 #define	SSP_CMD0_BLOCK_SIZE_MASK		(0xf << 16)
156 #define	SSP_CMD0_BLOCK_SIZE_OFFSET		16
157 #define	SSP_CMD0_BLOCK_COUNT_MASK		(0xff << 8)
158 #define	SSP_CMD0_BLOCK_COUNT_OFFSET		8
159 #endif
160 #define	SSP_CMD0_CMD_MASK			0xff
161 #define	SSP_CMD0_CMD_OFFSET			0
162 #define	SSP_CMD0_CMD_MMC_GO_IDLE_STATE		0x00
163 #define	SSP_CMD0_CMD_MMC_SEND_OP_COND		0x01
164 #define	SSP_CMD0_CMD_MMC_ALL_SEND_CID		0x02
165 #define	SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR	0x03
166 #define	SSP_CMD0_CMD_MMC_SET_DSR		0x04
167 #define	SSP_CMD0_CMD_MMC_RESERVED_5		0x05
168 #define	SSP_CMD0_CMD_MMC_SWITCH			0x06
169 #define	SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD	0x07
170 #define	SSP_CMD0_CMD_MMC_SEND_EXT_CSD		0x08
171 #define	SSP_CMD0_CMD_MMC_SEND_CSD		0x09
172 #define	SSP_CMD0_CMD_MMC_SEND_CID		0x0a
173 #define	SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP	0x0b
174 #define	SSP_CMD0_CMD_MMC_STOP_TRANSMISSION	0x0c
175 #define	SSP_CMD0_CMD_MMC_SEND_STATUS		0x0d
176 #define	SSP_CMD0_CMD_MMC_BUSTEST_R		0x0e
177 #define	SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE	0x0f
178 #define	SSP_CMD0_CMD_MMC_SET_BLOCKLEN		0x10
179 #define	SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK	0x11
180 #define	SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK	0x12
181 #define	SSP_CMD0_CMD_MMC_BUSTEST_W		0x13
182 #define	SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP	0x14
183 #define	SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT	0x17
184 #define	SSP_CMD0_CMD_MMC_WRITE_BLOCK		0x18
185 #define	SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK	0x19
186 #define	SSP_CMD0_CMD_MMC_PROGRAM_CID		0x1a
187 #define	SSP_CMD0_CMD_MMC_PROGRAM_CSD		0x1b
188 #define	SSP_CMD0_CMD_MMC_SET_WRITE_PROT		0x1c
189 #define	SSP_CMD0_CMD_MMC_CLR_WRITE_PROT		0x1d
190 #define	SSP_CMD0_CMD_MMC_SEND_WRITE_PROT	0x1e
191 #define	SSP_CMD0_CMD_MMC_ERASE_GROUP_START	0x23
192 #define	SSP_CMD0_CMD_MMC_ERASE_GROUP_END	0x24
193 #define	SSP_CMD0_CMD_MMC_ERASE			0x26
194 #define	SSP_CMD0_CMD_MMC_FAST_IO		0x27
195 #define	SSP_CMD0_CMD_MMC_GO_IRQ_STATE		0x28
196 #define	SSP_CMD0_CMD_MMC_LOCK_UNLOCK		0x2a
197 #define	SSP_CMD0_CMD_MMC_APP_CMD		0x37
198 #define	SSP_CMD0_CMD_MMC_GEN_CMD		0x38
199 #define	SSP_CMD0_CMD_SD_GO_IDLE_STATE		0x00
200 #define	SSP_CMD0_CMD_SD_ALL_SEND_CID		0x02
201 #define	SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR	0x03
202 #define	SSP_CMD0_CMD_SD_SET_DSR			0x04
203 #define	SSP_CMD0_CMD_SD_IO_SEND_OP_COND		0x05
204 #define	SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD	0x07
205 #define	SSP_CMD0_CMD_SD_SEND_CSD		0x09
206 #define	SSP_CMD0_CMD_SD_SEND_CID		0x0a
207 #define	SSP_CMD0_CMD_SD_STOP_TRANSMISSION	0x0c
208 #define	SSP_CMD0_CMD_SD_SEND_STATUS		0x0d
209 #define	SSP_CMD0_CMD_SD_GO_INACTIVE_STATE	0x0f
210 #define	SSP_CMD0_CMD_SD_SET_BLOCKLEN		0x10
211 #define	SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK	0x11
212 #define	SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK	0x12
213 #define	SSP_CMD0_CMD_SD_WRITE_BLOCK		0x18
214 #define	SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK	0x19
215 #define	SSP_CMD0_CMD_SD_PROGRAM_CSD		0x1b
216 #define	SSP_CMD0_CMD_SD_SET_WRITE_PROT		0x1c
217 #define	SSP_CMD0_CMD_SD_CLR_WRITE_PROT		0x1d
218 #define	SSP_CMD0_CMD_SD_SEND_WRITE_PROT		0x1e
219 #define	SSP_CMD0_CMD_SD_ERASE_WR_BLK_START	0x20
220 #define	SSP_CMD0_CMD_SD_ERASE_WR_BLK_END	0x21
221 #define	SSP_CMD0_CMD_SD_ERASE_GROUP_START	0x23
222 #define	SSP_CMD0_CMD_SD_ERASE_GROUP_END		0x24
223 #define	SSP_CMD0_CMD_SD_ERASE			0x26
224 #define	SSP_CMD0_CMD_SD_LOCK_UNLOCK		0x2a
225 #define	SSP_CMD0_CMD_SD_IO_RW_DIRECT		0x34
226 #define	SSP_CMD0_CMD_SD_IO_RW_EXTENDED		0x35
227 #define	SSP_CMD0_CMD_SD_APP_CMD			0x37
228 #define	SSP_CMD0_CMD_SD_GEN_CMD			0x38
229 
230 #define	SSP_CMD1_CMD_ARG_MASK			0xffffffff
231 #define	SSP_CMD1_CMD_ARG_OFFSET			0
232 
233 #if defined(CONFIG_MX28)
234 #define	SSP_XFER_SIZE_XFER_COUNT_MASK		0xffffffff
235 #define	SSP_XFER_SIZE_XFER_COUNT_OFFSET		0
236 
237 #define	SSP_BLOCK_SIZE_BLOCK_COUNT_MASK		(0xffffff << 4)
238 #define	SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET	4
239 #define	SSP_BLOCK_SIZE_BLOCK_SIZE_MASK		0xf
240 #define	SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET	0
241 #endif
242 
243 #define	SSP_COMPREF_REFERENCE_MASK		0xffffffff
244 #define	SSP_COMPREF_REFERENCE_OFFSET		0
245 
246 #define	SSP_COMPMASK_MASK_MASK			0xffffffff
247 #define	SSP_COMPMASK_MASK_OFFSET		0
248 
249 #define	SSP_TIMING_TIMEOUT_MASK			(0xffff << 16)
250 #define	SSP_TIMING_TIMEOUT_OFFSET		16
251 #define	SSP_TIMING_CLOCK_DIVIDE_MASK		(0xff << 8)
252 #define	SSP_TIMING_CLOCK_DIVIDE_OFFSET		8
253 #define	SSP_TIMING_CLOCK_RATE_MASK		0xff
254 #define	SSP_TIMING_CLOCK_RATE_OFFSET		0
255 
256 #define	SSP_CTRL1_SDIO_IRQ			(1 << 31)
257 #define	SSP_CTRL1_SDIO_IRQ_EN			(1 << 30)
258 #define	SSP_CTRL1_RESP_ERR_IRQ			(1 << 29)
259 #define	SSP_CTRL1_RESP_ERR_IRQ_EN		(1 << 28)
260 #define	SSP_CTRL1_RESP_TIMEOUT_IRQ		(1 << 27)
261 #define	SSP_CTRL1_RESP_TIMEOUT_IRQ_EN		(1 << 26)
262 #define	SSP_CTRL1_DATA_TIMEOUT_IRQ		(1 << 25)
263 #define	SSP_CTRL1_DATA_TIMEOUT_IRQ_EN		(1 << 24)
264 #define	SSP_CTRL1_DATA_CRC_IRQ			(1 << 23)
265 #define	SSP_CTRL1_DATA_CRC_IRQ_EN		(1 << 22)
266 #define	SSP_CTRL1_FIFO_UNDERRUN_IRQ		(1 << 21)
267 #define	SSP_CTRL1_FIFO_UNDERRUN_EN		(1 << 20)
268 #define	SSP_CTRL1_CEATA_CCS_ERR_IRQ		(1 << 19)
269 #define	SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN		(1 << 18)
270 #define	SSP_CTRL1_RECV_TIMEOUT_IRQ		(1 << 17)
271 #define	SSP_CTRL1_RECV_TIMEOUT_IRQ_EN		(1 << 16)
272 #define	SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)
273 #define	SSP_CTRL1_FIFO_OVERRUN_IRQ_EN		(1 << 14)
274 #define	SSP_CTRL1_DMA_ENABLE			(1 << 13)
275 #define	SSP_CTRL1_CEATA_CCS_ERR_EN		(1 << 12)
276 #define	SSP_CTRL1_SLAVE_OUT_DISABLE		(1 << 11)
277 #define	SSP_CTRL1_PHASE				(1 << 10)
278 #define	SSP_CTRL1_POLARITY			(1 << 9)
279 #define	SSP_CTRL1_SLAVE_MODE			(1 << 8)
280 #define	SSP_CTRL1_WORD_LENGTH_MASK		(0xf << 4)
281 #define	SSP_CTRL1_WORD_LENGTH_OFFSET		4
282 #define	SSP_CTRL1_WORD_LENGTH_RESERVED0		(0x0 << 4)
283 #define	SSP_CTRL1_WORD_LENGTH_RESERVED1		(0x1 << 4)
284 #define	SSP_CTRL1_WORD_LENGTH_RESERVED2		(0x2 << 4)
285 #define	SSP_CTRL1_WORD_LENGTH_FOUR_BITS		(0x3 << 4)
286 #define	SSP_CTRL1_WORD_LENGTH_EIGHT_BITS	(0x7 << 4)
287 #define	SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS	(0xf << 4)
288 #define	SSP_CTRL1_SSP_MODE_MASK			0xf
289 #define	SSP_CTRL1_SSP_MODE_OFFSET		0
290 #define	SSP_CTRL1_SSP_MODE_SPI			0x0
291 #define	SSP_CTRL1_SSP_MODE_SSI			0x1
292 #define	SSP_CTRL1_SSP_MODE_SD_MMC		0x3
293 #define	SSP_CTRL1_SSP_MODE_MS			0x4
294 
295 #define	SSP_DATA_DATA_MASK			0xffffffff
296 #define	SSP_DATA_DATA_OFFSET			0
297 
298 #define	SSP_SDRESP0_RESP0_MASK			0xffffffff
299 #define	SSP_SDRESP0_RESP0_OFFSET		0
300 
301 #define	SSP_SDRESP1_RESP1_MASK			0xffffffff
302 #define	SSP_SDRESP1_RESP1_OFFSET		0
303 
304 #define	SSP_SDRESP2_RESP2_MASK			0xffffffff
305 #define	SSP_SDRESP2_RESP2_OFFSET		0
306 
307 #define	SSP_SDRESP3_RESP3_MASK			0xffffffff
308 #define	SSP_SDRESP3_RESP3_OFFSET		0
309 
310 #define	SSP_DDR_CTRL_DMA_BURST_TYPE_MASK	(0x3 << 30)
311 #define	SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET	30
312 #define	SSP_DDR_CTRL_NIBBLE_POS			(1 << 1)
313 #define	SSP_DDR_CTRL_TXCLK_DELAY_TYPE		(1 << 0)
314 
315 #define	SSP_DLL_CTRL_REF_UPDATE_INT_MASK	(0xf << 28)
316 #define	SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET	28
317 #define	SSP_DLL_CTRL_SLV_UPDATE_INT_MASK	(0xff << 20)
318 #define	SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET	20
319 #define	SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK	(0x3f << 10)
320 #define	SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET	10
321 #define	SSP_DLL_CTRL_SLV_OVERRIDE		(1 << 9)
322 #define	SSP_DLL_CTRL_GATE_UPDATE		(1 << 7)
323 #define	SSP_DLL_CTRL_SLV_DLY_TARGET_MASK	(0xf << 3)
324 #define	SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET	3
325 #define	SSP_DLL_CTRL_SLV_FORCE_UPD		(1 << 2)
326 #define	SSP_DLL_CTRL_RESET			(1 << 1)
327 #define	SSP_DLL_CTRL_ENABLE			(1 << 0)
328 
329 #define	SSP_STATUS_PRESENT			(1 << 31)
330 #define	SSP_STATUS_MS_PRESENT			(1 << 30)
331 #define	SSP_STATUS_SD_PRESENT			(1 << 29)
332 #define	SSP_STATUS_CARD_DETECT			(1 << 28)
333 #define	SSP_STATUS_DMABURST			(1 << 22)
334 #define	SSP_STATUS_DMASENSE			(1 << 21)
335 #define	SSP_STATUS_DMATERM			(1 << 20)
336 #define	SSP_STATUS_DMAREQ			(1 << 19)
337 #define	SSP_STATUS_DMAEND			(1 << 18)
338 #define	SSP_STATUS_SDIO_IRQ			(1 << 17)
339 #define	SSP_STATUS_RESP_CRC_ERR			(1 << 16)
340 #define	SSP_STATUS_RESP_ERR			(1 << 15)
341 #define	SSP_STATUS_RESP_TIMEOUT			(1 << 14)
342 #define	SSP_STATUS_DATA_CRC_ERR			(1 << 13)
343 #define	SSP_STATUS_TIMEOUT			(1 << 12)
344 #define	SSP_STATUS_RECV_TIMEOUT_STAT		(1 << 11)
345 #define	SSP_STATUS_CEATA_CCS_ERR		(1 << 10)
346 #define	SSP_STATUS_FIFO_OVRFLW			(1 << 9)
347 #define	SSP_STATUS_FIFO_FULL			(1 << 8)
348 #define	SSP_STATUS_FIFO_EMPTY			(1 << 5)
349 #define	SSP_STATUS_FIFO_UNDRFLW			(1 << 4)
350 #define	SSP_STATUS_CMD_BUSY			(1 << 3)
351 #define	SSP_STATUS_DATA_BUSY			(1 << 2)
352 #define	SSP_STATUS_BUSY				(1 << 0)
353 
354 #define	SSP_DLL_STS_REF_SEL_MASK		(0x3f << 8)
355 #define	SSP_DLL_STS_REF_SEL_OFFSET		8
356 #define	SSP_DLL_STS_SLV_SEL_MASK		(0x3f << 2)
357 #define	SSP_DLL_STS_SLV_SEL_OFFSET		2
358 #define	SSP_DLL_STS_REF_LOCK			(1 << 1)
359 #define	SSP_DLL_STS_SLV_LOCK			(1 << 0)
360 
361 #define	SSP_DEBUG_DATACRC_ERR_MASK		(0xf << 28)
362 #define	SSP_DEBUG_DATACRC_ERR_OFFSET		28
363 #define	SSP_DEBUG_DATA_STALL			(1 << 27)
364 #define	SSP_DEBUG_DAT_SM_MASK			(0x7 << 24)
365 #define	SSP_DEBUG_DAT_SM_OFFSET			24
366 #define	SSP_DEBUG_DAT_SM_DSM_IDLE		(0x0 << 24)
367 #define	SSP_DEBUG_DAT_SM_DSM_WORD		(0x2 << 24)
368 #define	SSP_DEBUG_DAT_SM_DSM_CRC1		(0x3 << 24)
369 #define	SSP_DEBUG_DAT_SM_DSM_CRC2		(0x4 << 24)
370 #define	SSP_DEBUG_DAT_SM_DSM_END		(0x5 << 24)
371 #define	SSP_DEBUG_MSTK_SM_MASK			(0xf << 20)
372 #define	SSP_DEBUG_MSTK_SM_OFFSET		20
373 #define	SSP_DEBUG_MSTK_SM_MSTK_IDLE		(0x0 << 20)
374 #define	SSP_DEBUG_MSTK_SM_MSTK_CKON		(0x1 << 20)
375 #define	SSP_DEBUG_MSTK_SM_MSTK_BS1		(0x2 << 20)
376 #define	SSP_DEBUG_MSTK_SM_MSTK_TPC		(0x3 << 20)
377 #define	SSP_DEBUG_MSTK_SM_MSTK_BS2		(0x4 << 20)
378 #define	SSP_DEBUG_MSTK_SM_MSTK_HDSHK		(0x5 << 20)
379 #define	SSP_DEBUG_MSTK_SM_MSTK_BS3		(0x6 << 20)
380 #define	SSP_DEBUG_MSTK_SM_MSTK_RW		(0x7 << 20)
381 #define	SSP_DEBUG_MSTK_SM_MSTK_CRC1		(0x8 << 20)
382 #define	SSP_DEBUG_MSTK_SM_MSTK_CRC2		(0x9 << 20)
383 #define	SSP_DEBUG_MSTK_SM_MSTK_BS0		(0xa << 20)
384 #define	SSP_DEBUG_MSTK_SM_MSTK_END1		(0xb << 20)
385 #define	SSP_DEBUG_MSTK_SM_MSTK_END2W		(0xc << 20)
386 #define	SSP_DEBUG_MSTK_SM_MSTK_END2R		(0xd << 20)
387 #define	SSP_DEBUG_MSTK_SM_MSTK_DONE		(0xe << 20)
388 #define	SSP_DEBUG_CMD_OE			(1 << 19)
389 #define	SSP_DEBUG_DMA_SM_MASK			(0x7 << 16)
390 #define	SSP_DEBUG_DMA_SM_OFFSET			16
391 #define	SSP_DEBUG_DMA_SM_DMA_IDLE		(0x0 << 16)
392 #define	SSP_DEBUG_DMA_SM_DMA_DMAREQ		(0x1 << 16)
393 #define	SSP_DEBUG_DMA_SM_DMA_DMAACK		(0x2 << 16)
394 #define	SSP_DEBUG_DMA_SM_DMA_STALL		(0x3 << 16)
395 #define	SSP_DEBUG_DMA_SM_DMA_BUSY		(0x4 << 16)
396 #define	SSP_DEBUG_DMA_SM_DMA_DONE		(0x5 << 16)
397 #define	SSP_DEBUG_DMA_SM_DMA_COUNT		(0x6 << 16)
398 #define	SSP_DEBUG_MMC_SM_MASK			(0xf << 12)
399 #define	SSP_DEBUG_MMC_SM_OFFSET			12
400 #define	SSP_DEBUG_MMC_SM_MMC_IDLE		(0x0 << 12)
401 #define	SSP_DEBUG_MMC_SM_MMC_CMD		(0x1 << 12)
402 #define	SSP_DEBUG_MMC_SM_MMC_TRC		(0x2 << 12)
403 #define	SSP_DEBUG_MMC_SM_MMC_RESP		(0x3 << 12)
404 #define	SSP_DEBUG_MMC_SM_MMC_RPRX		(0x4 << 12)
405 #define	SSP_DEBUG_MMC_SM_MMC_TX			(0x5 << 12)
406 #define	SSP_DEBUG_MMC_SM_MMC_CTOK		(0x6 << 12)
407 #define	SSP_DEBUG_MMC_SM_MMC_RX			(0x7 << 12)
408 #define	SSP_DEBUG_MMC_SM_MMC_CCS		(0x8 << 12)
409 #define	SSP_DEBUG_MMC_SM_MMC_PUP		(0x9 << 12)
410 #define	SSP_DEBUG_MMC_SM_MMC_WAIT		(0xa << 12)
411 #define	SSP_DEBUG_CMD_SM_MASK			(0x3 << 10)
412 #define	SSP_DEBUG_CMD_SM_OFFSET			10
413 #define	SSP_DEBUG_CMD_SM_CSM_IDLE		(0x0 << 10)
414 #define	SSP_DEBUG_CMD_SM_CSM_INDEX		(0x1 << 10)
415 #define	SSP_DEBUG_CMD_SM_CSM_ARG		(0x2 << 10)
416 #define	SSP_DEBUG_CMD_SM_CSM_CRC		(0x3 << 10)
417 #define	SSP_DEBUG_SSP_CMD			(1 << 9)
418 #define	SSP_DEBUG_SSP_RESP			(1 << 8)
419 #define	SSP_DEBUG_SSP_RXD_MASK			0xff
420 #define	SSP_DEBUG_SSP_RXD_OFFSET		0
421 
422 #define	SSP_VERSION_MAJOR_MASK			(0xff << 24)
423 #define	SSP_VERSION_MAJOR_OFFSET		24
424 #define	SSP_VERSION_MINOR_MASK			(0xff << 16)
425 #define	SSP_VERSION_MINOR_OFFSET		16
426 #define	SSP_VERSION_STEP_MASK			0xffff
427 #define	SSP_VERSION_STEP_OFFSET			0
428 
429 #endif /* __MX28_REGS_SSP_H__ */
430