1 /*
2  * Freescale i.MX28 Power Controller Register Definitions
3  *
4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
19  *
20  */
21 
22 #ifndef __MX28_REGS_POWER_H__
23 #define __MX28_REGS_POWER_H__
24 
25 #include <asm/imx-common/regs-common.h>
26 
27 #ifndef	__ASSEMBLY__
28 struct mxs_power_regs {
29 	mxs_reg_32(hw_power_ctrl)
30 	mxs_reg_32(hw_power_5vctrl)
31 	mxs_reg_32(hw_power_minpwr)
32 	mxs_reg_32(hw_power_charge)
33 	uint32_t	hw_power_vdddctrl;
34 	uint32_t	reserved_vddd[3];
35 	uint32_t	hw_power_vddactrl;
36 	uint32_t	reserved_vdda[3];
37 	uint32_t	hw_power_vddioctrl;
38 	uint32_t	reserved_vddio[3];
39 	uint32_t	hw_power_vddmemctrl;
40 	uint32_t	reserved_vddmem[3];
41 	uint32_t	hw_power_dcdc4p2;
42 	uint32_t	reserved_dcdc4p2[3];
43 	uint32_t	hw_power_misc;
44 	uint32_t	reserved_misc[3];
45 	uint32_t	hw_power_dclimits;
46 	uint32_t	reserved_dclimits[3];
47 	mxs_reg_32(hw_power_loopctrl)
48 	uint32_t	hw_power_sts;
49 	uint32_t	reserved_sts[3];
50 	mxs_reg_32(hw_power_speed)
51 	uint32_t	hw_power_battmonitor;
52 	uint32_t	reserved_battmonitor[3];
53 
54 	uint32_t	reserved[4];
55 
56 	mxs_reg_32(hw_power_reset)
57 	mxs_reg_32(hw_power_debug)
58 	mxs_reg_32(hw_power_thermal)
59 	mxs_reg_32(hw_power_usb1ctrl)
60 	mxs_reg_32(hw_power_special)
61 	mxs_reg_32(hw_power_version)
62 	mxs_reg_32(hw_power_anaclkctrl)
63 	mxs_reg_32(hw_power_refctrl)
64 };
65 #endif
66 
67 #define	POWER_CTRL_PSWITCH_MID_TRAN			(1 << 27)
68 #define	POWER_CTRL_DCDC4P2_BO_IRQ			(1 << 24)
69 #define	POWER_CTRL_ENIRQ_DCDC4P2_BO			(1 << 23)
70 #define	POWER_CTRL_VDD5V_DROOP_IRQ			(1 << 22)
71 #define	POWER_CTRL_ENIRQ_VDD5V_DROOP			(1 << 21)
72 #define	POWER_CTRL_PSWITCH_IRQ				(1 << 20)
73 #define	POWER_CTRL_PSWITCH_IRQ_SRC			(1 << 19)
74 #define	POWER_CTRL_POLARITY_PSWITCH			(1 << 18)
75 #define	POWER_CTRL_ENIRQ_PSWITCH			(1 << 17)
76 #define	POWER_CTRL_POLARITY_DC_OK			(1 << 16)
77 #define	POWER_CTRL_DC_OK_IRQ				(1 << 15)
78 #define	POWER_CTRL_ENIRQ_DC_OK				(1 << 14)
79 #define	POWER_CTRL_BATT_BO_IRQ				(1 << 13)
80 #define	POWER_CTRL_ENIRQ_BATT_BO			(1 << 12)
81 #define	POWER_CTRL_VDDIO_BO_IRQ				(1 << 11)
82 #define	POWER_CTRL_ENIRQ_VDDIO_BO			(1 << 10)
83 #define	POWER_CTRL_VDDA_BO_IRQ				(1 << 9)
84 #define	POWER_CTRL_ENIRQ_VDDA_BO			(1 << 8)
85 #define	POWER_CTRL_VDDD_BO_IRQ				(1 << 7)
86 #define	POWER_CTRL_ENIRQ_VDDD_BO			(1 << 6)
87 #define	POWER_CTRL_POLARITY_VBUSVALID			(1 << 5)
88 #define	POWER_CTRL_VBUS_VALID_IRQ			(1 << 4)
89 #define	POWER_CTRL_ENIRQ_VBUS_VALID			(1 << 3)
90 #define	POWER_CTRL_POLARITY_VDD5V_GT_VDDIO		(1 << 2)
91 #define	POWER_CTRL_VDD5V_GT_VDDIO_IRQ			(1 << 1)
92 #define	POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO			(1 << 0)
93 
94 #define	POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 30)
95 #define	POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		30
96 #define	POWER_5VCTRL_VBUSDROOP_TRSH_4V3			(0x0 << 30)
97 #define	POWER_5VCTRL_VBUSDROOP_TRSH_4V4			(0x1 << 30)
98 #define	POWER_5VCTRL_VBUSDROOP_TRSH_4V5			(0x2 << 30)
99 #define	POWER_5VCTRL_VBUSDROOP_TRSH_4V7			(0x3 << 30)
100 #define	POWER_5VCTRL_HEADROOM_ADJ_MASK			(0x7 << 24)
101 #define	POWER_5VCTRL_HEADROOM_ADJ_OFFSET		24
102 #define	POWER_5VCTRL_PWD_CHARGE_4P2_MASK		(0x3 << 20)
103 #define	POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET		20
104 #define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK		(0x3f << 12)
105 #define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET		12
106 #define	POWER_5VCTRL_VBUSVALID_TRSH_MASK		(0x7 << 8)
107 #define	POWER_5VCTRL_VBUSVALID_TRSH_OFFSET		8
108 #define	POWER_5VCTRL_VBUSVALID_TRSH_2V9			(0x0 << 8)
109 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V0			(0x1 << 8)
110 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V1			(0x2 << 8)
111 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V2			(0x3 << 8)
112 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V3			(0x4 << 8)
113 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V4			(0x5 << 8)
114 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V5			(0x6 << 8)
115 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V6			(0x7 << 8)
116 #define	POWER_5VCTRL_PWDN_5VBRNOUT			(1 << 7)
117 #define	POWER_5VCTRL_ENABLE_LINREG_ILIMIT		(1 << 6)
118 #define	POWER_5VCTRL_DCDC_XFER				(1 << 5)
119 #define	POWER_5VCTRL_VBUSVALID_5VDETECT			(1 << 4)
120 #define	POWER_5VCTRL_VBUSVALID_TO_B			(1 << 3)
121 #define	POWER_5VCTRL_ILIMIT_EQ_ZERO			(1 << 2)
122 #define	POWER_5VCTRL_PWRUP_VBUS_CMPS			(1 << 1)
123 #define	POWER_5VCTRL_ENABLE_DCDC			(1 << 0)
124 
125 #define	POWER_MINPWR_LOWPWR_4P2				(1 << 14)
126 #define	POWER_MINPWR_PWD_BO				(1 << 12)
127 #define	POWER_MINPWR_USE_VDDXTAL_VBG			(1 << 11)
128 #define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
129 #define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
130 #define	POWER_MINPWR_SELECT_OSC				(1 << 8)
131 #define	POWER_MINPWR_VBG_OFF				(1 << 7)
132 #define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
133 #define	POWER_MINPWR_HALFFETS				(1 << 5)
134 #define	POWER_MINPWR_LESSANA_I				(1 << 4)
135 #define	POWER_MINPWR_PWD_XTAL24				(1 << 3)
136 #define	POWER_MINPWR_DC_STOPCLK				(1 << 2)
137 #define	POWER_MINPWR_EN_DC_PFM				(1 << 1)
138 #define	POWER_MINPWR_DC_HALFCLK				(1 << 0)
139 
140 #define	POWER_CHARGE_ADJ_VOLT_MASK			(0x7 << 24)
141 #define	POWER_CHARGE_ADJ_VOLT_OFFSET			24
142 #define	POWER_CHARGE_ADJ_VOLT_M025P			(0x1 << 24)
143 #define	POWER_CHARGE_ADJ_VOLT_P050P			(0x2 << 24)
144 #define	POWER_CHARGE_ADJ_VOLT_M075P			(0x3 << 24)
145 #define	POWER_CHARGE_ADJ_VOLT_P025P			(0x4 << 24)
146 #define	POWER_CHARGE_ADJ_VOLT_M050P			(0x5 << 24)
147 #define	POWER_CHARGE_ADJ_VOLT_P075P			(0x6 << 24)
148 #define	POWER_CHARGE_ADJ_VOLT_M100P			(0x7 << 24)
149 #define	POWER_CHARGE_ENABLE_LOAD			(1 << 22)
150 #define	POWER_CHARGE_ENABLE_FAULT_DETECT		(1 << 20)
151 #define	POWER_CHARGE_CHRG_STS_OFF			(1 << 19)
152 #define	POWER_CHARGE_LIION_4P1				(1 << 18)
153 #define	POWER_CHARGE_PWD_BATTCHRG			(1 << 16)
154 #define	POWER_CHARGE_ENABLE_CHARGER_USB1		(1 << 13)
155 #define	POWER_CHARGE_ENABLE_CHARGER_USB0		(1 << 12)
156 #define	POWER_CHARGE_STOP_ILIMIT_MASK			(0xf << 8)
157 #define	POWER_CHARGE_STOP_ILIMIT_OFFSET			8
158 #define	POWER_CHARGE_STOP_ILIMIT_10MA			(0x1 << 8)
159 #define	POWER_CHARGE_STOP_ILIMIT_20MA			(0x2 << 8)
160 #define	POWER_CHARGE_STOP_ILIMIT_50MA			(0x4 << 8)
161 #define	POWER_CHARGE_STOP_ILIMIT_100MA			(0x8 << 8)
162 #define	POWER_CHARGE_BATTCHRG_I_MASK			0x3f
163 #define	POWER_CHARGE_BATTCHRG_I_OFFSET			0
164 #define	POWER_CHARGE_BATTCHRG_I_10MA			0x01
165 #define	POWER_CHARGE_BATTCHRG_I_20MA			0x02
166 #define	POWER_CHARGE_BATTCHRG_I_50MA			0x04
167 #define	POWER_CHARGE_BATTCHRG_I_100MA			0x08
168 #define	POWER_CHARGE_BATTCHRG_I_200MA			0x10
169 #define	POWER_CHARGE_BATTCHRG_I_400MA			0x20
170 
171 #define	POWER_VDDDCTRL_ADJTN_MASK			(0xf << 28)
172 #define	POWER_VDDDCTRL_ADJTN_OFFSET			28
173 #define	POWER_VDDDCTRL_PWDN_BRNOUT			(1 << 23)
174 #define	POWER_VDDDCTRL_DISABLE_STEPPING			(1 << 22)
175 #define	POWER_VDDDCTRL_ENABLE_LINREG			(1 << 21)
176 #define	POWER_VDDDCTRL_DISABLE_FET			(1 << 20)
177 #define	POWER_VDDDCTRL_LINREG_OFFSET_MASK		(0x3 << 16)
178 #define	POWER_VDDDCTRL_LINREG_OFFSET_OFFSET		16
179 #define	POWER_VDDDCTRL_LINREG_OFFSET_0STEPS		(0x0 << 16)
180 #define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 16)
181 #define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 16)
182 #define	POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 16)
183 #define	POWER_VDDDCTRL_BO_OFFSET_MASK			(0x7 << 8)
184 #define	POWER_VDDDCTRL_BO_OFFSET_OFFSET			8
185 #define	POWER_VDDDCTRL_TRG_MASK				0x1f
186 #define	POWER_VDDDCTRL_TRG_OFFSET			0
187 
188 #define	POWER_VDDACTRL_PWDN_BRNOUT			(1 << 19)
189 #define	POWER_VDDACTRL_DISABLE_STEPPING			(1 << 18)
190 #define	POWER_VDDACTRL_ENABLE_LINREG			(1 << 17)
191 #define	POWER_VDDACTRL_DISABLE_FET			(1 << 16)
192 #define	POWER_VDDACTRL_LINREG_OFFSET_MASK		(0x3 << 12)
193 #define	POWER_VDDACTRL_LINREG_OFFSET_OFFSET		12
194 #define	POWER_VDDACTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
195 #define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
196 #define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
197 #define	POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
198 #define	POWER_VDDACTRL_BO_OFFSET_MASK			(0x7 << 8)
199 #define	POWER_VDDACTRL_BO_OFFSET_OFFSET			8
200 #define	POWER_VDDACTRL_TRG_MASK				0x1f
201 #define	POWER_VDDACTRL_TRG_OFFSET			0
202 
203 #define	POWER_VDDIOCTRL_ADJTN_MASK			(0xf << 20)
204 #define	POWER_VDDIOCTRL_ADJTN_OFFSET			20
205 #define	POWER_VDDIOCTRL_PWDN_BRNOUT			(1 << 18)
206 #define	POWER_VDDIOCTRL_DISABLE_STEPPING		(1 << 17)
207 #define	POWER_VDDIOCTRL_DISABLE_FET			(1 << 16)
208 #define	POWER_VDDIOCTRL_LINREG_OFFSET_MASK		(0x3 << 12)
209 #define	POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET		12
210 #define	POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
211 #define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
212 #define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
213 #define	POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
214 #define	POWER_VDDIOCTRL_BO_OFFSET_MASK			(0x7 << 8)
215 #define	POWER_VDDIOCTRL_BO_OFFSET_OFFSET		8
216 #define	POWER_VDDIOCTRL_TRG_MASK			0x1f
217 #define	POWER_VDDIOCTRL_TRG_OFFSET			0
218 
219 #define	POWER_VDDMEMCTRL_PULLDOWN_ACTIVE		(1 << 10)
220 #define	POWER_VDDMEMCTRL_ENABLE_ILIMIT			(1 << 9)
221 #define	POWER_VDDMEMCTRL_ENABLE_LINREG			(1 << 8)
222 #define	POWER_VDDMEMCTRL_BO_OFFSET_MASK			(0x7 << 5)
223 #define	POWER_VDDMEMCTRL_BO_OFFSET_OFFSET		5
224 #define	POWER_VDDMEMCTRL_TRG_MASK			0x1f
225 #define	POWER_VDDMEMCTRL_TRG_OFFSET			0
226 
227 #define	POWER_DCDC4P2_DROPOUT_CTRL_MASK			(0xf << 28)
228 #define	POWER_DCDC4P2_DROPOUT_CTRL_OFFSET		28
229 #define	POWER_DCDC4P2_DROPOUT_CTRL_200MV		(0x3 << 30)
230 #define	POWER_DCDC4P2_DROPOUT_CTRL_100MV		(0x2 << 30)
231 #define	POWER_DCDC4P2_DROPOUT_CTRL_50MV			(0x1 << 30)
232 #define	POWER_DCDC4P2_DROPOUT_CTRL_25MV			(0x0 << 30)
233 #define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2		(0x0 << 28)
234 #define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT	(0x1 << 28)
235 #define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL		(0x2 << 28)
236 #define	POWER_DCDC4P2_ISTEAL_THRESH_MASK		(0x3 << 24)
237 #define	POWER_DCDC4P2_ISTEAL_THRESH_OFFSET		24
238 #define	POWER_DCDC4P2_ENABLE_4P2			(1 << 23)
239 #define	POWER_DCDC4P2_ENABLE_DCDC			(1 << 22)
240 #define	POWER_DCDC4P2_HYST_DIR				(1 << 21)
241 #define	POWER_DCDC4P2_HYST_THRESH			(1 << 20)
242 #define	POWER_DCDC4P2_TRG_MASK				(0x7 << 16)
243 #define	POWER_DCDC4P2_TRG_OFFSET			16
244 #define	POWER_DCDC4P2_TRG_4V2				(0x0 << 16)
245 #define	POWER_DCDC4P2_TRG_4V1				(0x1 << 16)
246 #define	POWER_DCDC4P2_TRG_4V0				(0x2 << 16)
247 #define	POWER_DCDC4P2_TRG_3V9				(0x3 << 16)
248 #define	POWER_DCDC4P2_TRG_BATT				(0x4 << 16)
249 #define	POWER_DCDC4P2_BO_MASK				(0x1f << 8)
250 #define	POWER_DCDC4P2_BO_OFFSET				8
251 #define	POWER_DCDC4P2_CMPTRIP_MASK			0x1f
252 #define	POWER_DCDC4P2_CMPTRIP_OFFSET			0
253 
254 #define	POWER_MISC_FREQSEL_MASK				(0x7 << 4)
255 #define	POWER_MISC_FREQSEL_OFFSET			4
256 #define	POWER_MISC_FREQSEL_20MHZ			(0x1 << 4)
257 #define	POWER_MISC_FREQSEL_24MHZ			(0x2 << 4)
258 #define	POWER_MISC_FREQSEL_19MHZ			(0x3 << 4)
259 #define	POWER_MISC_FREQSEL_14MHZ			(0x4 << 4)
260 #define	POWER_MISC_FREQSEL_18MHZ			(0x5 << 4)
261 #define	POWER_MISC_FREQSEL_21MHZ			(0x6 << 4)
262 #define	POWER_MISC_FREQSEL_17MHZ			(0x7 << 4)
263 #define	POWER_MISC_DISABLE_FET_BO_LOGIC			(1 << 3)
264 #define	POWER_MISC_DELAY_TIMING				(1 << 2)
265 #define	POWER_MISC_TEST					(1 << 1)
266 #define	POWER_MISC_SEL_PLLCLK				(1 << 0)
267 
268 #define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
269 #define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
270 #define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
271 #define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
272 
273 #define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
274 #define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)
275 #define	POWER_LOOPCTRL_EN_CM_HYST			(1 << 18)
276 #define	POWER_LOOPCTRL_EN_DF_HYST			(1 << 17)
277 #define	POWER_LOOPCTRL_CM_HYST_THRESH			(1 << 16)
278 #define	POWER_LOOPCTRL_DF_HYST_THRESH			(1 << 15)
279 #define	POWER_LOOPCTRL_RCSCALE_THRESH			(1 << 14)
280 #define	POWER_LOOPCTRL_EN_RCSCALE_MASK			(0x3 << 12)
281 #define	POWER_LOOPCTRL_EN_RCSCALE_OFFSET		12
282 #define	POWER_LOOPCTRL_EN_RCSCALE_DIS			(0x0 << 12)
283 #define	POWER_LOOPCTRL_EN_RCSCALE_2X			(0x1 << 12)
284 #define	POWER_LOOPCTRL_EN_RCSCALE_4X			(0x2 << 12)
285 #define	POWER_LOOPCTRL_EN_RCSCALE_8X			(0x3 << 12)
286 #define	POWER_LOOPCTRL_DC_FF_MASK			(0x7 << 8)
287 #define	POWER_LOOPCTRL_DC_FF_OFFSET			8
288 #define	POWER_LOOPCTRL_DC_R_MASK			(0xf << 4)
289 #define	POWER_LOOPCTRL_DC_R_OFFSET			4
290 #define	POWER_LOOPCTRL_DC_C_MASK			0x3
291 #define	POWER_LOOPCTRL_DC_C_OFFSET			0
292 #define	POWER_LOOPCTRL_DC_C_MAX				0x0
293 #define	POWER_LOOPCTRL_DC_C_2X				0x1
294 #define	POWER_LOOPCTRL_DC_C_4X				0x2
295 #define	POWER_LOOPCTRL_DC_C_MIN				0x3
296 
297 #define	POWER_STS_PWRUP_SOURCE_MASK			(0x3f << 24)
298 #define	POWER_STS_PWRUP_SOURCE_OFFSET			24
299 #define	POWER_STS_PWRUP_SOURCE_5V			(0x20 << 24)
300 #define	POWER_STS_PWRUP_SOURCE_RTC			(0x10 << 24)
301 #define	POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH		(0x02 << 24)
302 #define	POWER_STS_PWRUP_SOURCE_PSWITCH_MID		(0x01 << 24)
303 #define	POWER_STS_PSWITCH_MASK				(0x3 << 20)
304 #define	POWER_STS_PSWITCH_OFFSET			20
305 #define	POWER_STS_THERMAL_WARNING			(1 << 19)
306 #define	POWER_STS_VDDMEM_BO				(1 << 18)
307 #define	POWER_STS_AVALID0_STATUS			(1 << 17)
308 #define	POWER_STS_BVALID0_STATUS			(1 << 16)
309 #define	POWER_STS_VBUSVALID0_STATUS			(1 << 15)
310 #define	POWER_STS_SESSEND0_STATUS			(1 << 14)
311 #define	POWER_STS_BATT_BO				(1 << 13)
312 #define	POWER_STS_VDD5V_FAULT				(1 << 12)
313 #define	POWER_STS_CHRGSTS				(1 << 11)
314 #define	POWER_STS_DCDC_4P2_BO				(1 << 10)
315 #define	POWER_STS_DC_OK					(1 << 9)
316 #define	POWER_STS_VDDIO_BO				(1 << 8)
317 #define	POWER_STS_VDDA_BO				(1 << 7)
318 #define	POWER_STS_VDDD_BO				(1 << 6)
319 #define	POWER_STS_VDD5V_GT_VDDIO			(1 << 5)
320 #define	POWER_STS_VDD5V_DROOP				(1 << 4)
321 #define	POWER_STS_AVALID0				(1 << 3)
322 #define	POWER_STS_BVALID0				(1 << 2)
323 #define	POWER_STS_VBUSVALID0				(1 << 1)
324 #define	POWER_STS_SESSEND0				(1 << 0)
325 
326 #define	POWER_SPEED_STATUS_MASK				(0xffff << 8)
327 #define	POWER_SPEED_STATUS_OFFSET			8
328 #define	POWER_SPEED_STATUS_SEL_MASK			(0x3 << 6)
329 #define	POWER_SPEED_STATUS_SEL_OFFSET			6
330 #define	POWER_SPEED_STATUS_SEL_DCDC_STAT		(0x0 << 6)
331 #define	POWER_SPEED_STATUS_SEL_CORE_STAT		(0x1 << 6)
332 #define	POWER_SPEED_STATUS_SEL_ARM_STAT			(0x2 << 6)
333 #define	POWER_SPEED_CTRL_MASK				0x3
334 #define	POWER_SPEED_CTRL_OFFSET				0
335 #define	POWER_SPEED_CTRL_SS_OFF				0x0
336 #define	POWER_SPEED_CTRL_SS_ON				0x1
337 #define	POWER_SPEED_CTRL_SS_ENABLE			0x3
338 
339 #define	POWER_BATTMONITOR_BATT_VAL_MASK			(0x3ff << 16)
340 #define	POWER_BATTMONITOR_BATT_VAL_OFFSET		16
341 #define	POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN	(1 << 11)
342 #define	POWER_BATTMONITOR_EN_BATADJ			(1 << 10)
343 #define	POWER_BATTMONITOR_PWDN_BATTBRNOUT		(1 << 9)
344 #define	POWER_BATTMONITOR_BRWNOUT_PWD			(1 << 8)
345 #define	POWER_BATTMONITOR_BRWNOUT_LVL_MASK		0x1f
346 #define	POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET		0
347 
348 #define	POWER_RESET_UNLOCK_MASK				(0xffff << 16)
349 #define	POWER_RESET_UNLOCK_OFFSET			16
350 #define	POWER_RESET_UNLOCK_KEY				(0x3e77 << 16)
351 #define	POWER_RESET_FASTFALL_PSWITCH_OFF		(1 << 2)
352 #define	POWER_RESET_PWD_OFF				(1 << 1)
353 #define	POWER_RESET_PWD					(1 << 0)
354 
355 #define	POWER_DEBUG_VBUSVALIDPIOLOCK			(1 << 3)
356 #define	POWER_DEBUG_AVALIDPIOLOCK			(1 << 2)
357 #define	POWER_DEBUG_BVALIDPIOLOCK			(1 << 1)
358 #define	POWER_DEBUG_SESSENDPIOLOCK			(1 << 0)
359 
360 #define	POWER_THERMAL_TEST				(1 << 8)
361 #define	POWER_THERMAL_PWD				(1 << 7)
362 #define	POWER_THERMAL_LOW_POWER				(1 << 6)
363 #define	POWER_THERMAL_OFFSET_ADJ_MASK			(0x3 << 4)
364 #define	POWER_THERMAL_OFFSET_ADJ_OFFSET			4
365 #define	POWER_THERMAL_OFFSET_ADJ_ENABLE			(1 << 3)
366 #define	POWER_THERMAL_TEMP_THRESHOLD_MASK		0x7
367 #define	POWER_THERMAL_TEMP_THRESHOLD_OFFSET		0
368 
369 #define	POWER_USB1CTRL_AVALID1				(1 << 3)
370 #define	POWER_USB1CTRL_BVALID1				(1 << 2)
371 #define	POWER_USB1CTRL_VBUSVALID1			(1 << 1)
372 #define	POWER_USB1CTRL_SESSEND1				(1 << 0)
373 
374 #define	POWER_SPECIAL_TEST_MASK				0xffffffff
375 #define	POWER_SPECIAL_TEST_OFFSET			0
376 
377 #define	POWER_VERSION_MAJOR_MASK			(0xff << 24)
378 #define	POWER_VERSION_MAJOR_OFFSET			24
379 #define	POWER_VERSION_MINOR_MASK			(0xff << 16)
380 #define	POWER_VERSION_MINOR_OFFSET			16
381 #define	POWER_VERSION_STEP_MASK				0xffff
382 #define	POWER_VERSION_STEP_OFFSET			0
383 
384 #define	POWER_ANACLKCTRL_CLKGATE_0			(1 << 31)
385 #define	POWER_ANACLKCTRL_OUTDIV_MASK			(0x7 << 28)
386 #define	POWER_ANACLKCTRL_OUTDIV_OFFSET			28
387 #define	POWER_ANACLKCTRL_INVERT_OUTCLK			(1 << 27)
388 #define	POWER_ANACLKCTRL_CLKGATE_I			(1 << 26)
389 #define	POWER_ANACLKCTRL_DITHER_OFF			(1 << 10)
390 #define	POWER_ANACLKCTRL_SLOW_DITHER			(1 << 9)
391 #define	POWER_ANACLKCTRL_INVERT_INCLK			(1 << 8)
392 #define	POWER_ANACLKCTRL_INCLK_SHIFT_MASK		(0x3 << 4)
393 #define	POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET		4
394 #define	POWER_ANACLKCTRL_INDIV_MASK			0x7
395 #define	POWER_ANACLKCTRL_INDIV_OFFSET			0
396 
397 #define	POWER_REFCTRL_FASTSETTLING			(1 << 26)
398 #define	POWER_REFCTRL_RAISE_REF				(1 << 25)
399 #define	POWER_REFCTRL_XTAL_BGR_BIAS			(1 << 24)
400 #define	POWER_REFCTRL_VBG_ADJ_MASK			(0x7 << 20)
401 #define	POWER_REFCTRL_VBG_ADJ_OFFSET			20
402 #define	POWER_REFCTRL_LOW_PWR				(1 << 19)
403 #define	POWER_REFCTRL_BIAS_CTRL_MASK			(0x3 << 16)
404 #define	POWER_REFCTRL_BIAS_CTRL_OFFSET			16
405 #define	POWER_REFCTRL_VDDXTAL_TO_VDDD			(1 << 14)
406 #define	POWER_REFCTRL_ADJ_ANA				(1 << 13)
407 #define	POWER_REFCTRL_ADJ_VAG				(1 << 12)
408 #define	POWER_REFCTRL_ANA_REFVAL_MASK			(0xf << 8)
409 #define	POWER_REFCTRL_ANA_REFVAL_OFFSET			8
410 #define	POWER_REFCTRL_VAG_VAL_MASK			(0xf << 4)
411 #define	POWER_REFCTRL_VAG_VAL_OFFSET			4
412 
413 #endif	/* __MX28_REGS_POWER_H__ */
414