1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2893aabbeSMarek Vasut /* 3893aabbeSMarek Vasut * Freescale i.MX28 Power Controller Register Definitions 4893aabbeSMarek Vasut * 5893aabbeSMarek Vasut * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 6893aabbeSMarek Vasut */ 7893aabbeSMarek Vasut 8893aabbeSMarek Vasut #ifndef __MX28_REGS_POWER_H__ 9893aabbeSMarek Vasut #define __MX28_REGS_POWER_H__ 10893aabbeSMarek Vasut 11552a848eSStefano Babic #include <asm/mach-imx/regs-common.h> 12893aabbeSMarek Vasut 13893aabbeSMarek Vasut #ifndef __ASSEMBLY__ 14893aabbeSMarek Vasut struct mxs_power_regs { 15893aabbeSMarek Vasut mxs_reg_32(hw_power_ctrl) 16893aabbeSMarek Vasut mxs_reg_32(hw_power_5vctrl) 17893aabbeSMarek Vasut mxs_reg_32(hw_power_minpwr) 18893aabbeSMarek Vasut mxs_reg_32(hw_power_charge) 19893aabbeSMarek Vasut uint32_t hw_power_vdddctrl; 20893aabbeSMarek Vasut uint32_t reserved_vddd[3]; 21893aabbeSMarek Vasut uint32_t hw_power_vddactrl; 22893aabbeSMarek Vasut uint32_t reserved_vdda[3]; 23893aabbeSMarek Vasut uint32_t hw_power_vddioctrl; 24893aabbeSMarek Vasut uint32_t reserved_vddio[3]; 25893aabbeSMarek Vasut uint32_t hw_power_vddmemctrl; 26893aabbeSMarek Vasut uint32_t reserved_vddmem[3]; 27893aabbeSMarek Vasut uint32_t hw_power_dcdc4p2; 28893aabbeSMarek Vasut uint32_t reserved_dcdc4p2[3]; 29893aabbeSMarek Vasut uint32_t hw_power_misc; 30893aabbeSMarek Vasut uint32_t reserved_misc[3]; 31893aabbeSMarek Vasut uint32_t hw_power_dclimits; 32893aabbeSMarek Vasut uint32_t reserved_dclimits[3]; 33893aabbeSMarek Vasut mxs_reg_32(hw_power_loopctrl) 34893aabbeSMarek Vasut uint32_t hw_power_sts; 35893aabbeSMarek Vasut uint32_t reserved_sts[3]; 36893aabbeSMarek Vasut mxs_reg_32(hw_power_speed) 37893aabbeSMarek Vasut uint32_t hw_power_battmonitor; 38893aabbeSMarek Vasut uint32_t reserved_battmonitor[3]; 39893aabbeSMarek Vasut 40893aabbeSMarek Vasut uint32_t reserved[4]; 41893aabbeSMarek Vasut 42893aabbeSMarek Vasut mxs_reg_32(hw_power_reset) 43893aabbeSMarek Vasut mxs_reg_32(hw_power_debug) 44893aabbeSMarek Vasut mxs_reg_32(hw_power_thermal) 45893aabbeSMarek Vasut mxs_reg_32(hw_power_usb1ctrl) 46893aabbeSMarek Vasut mxs_reg_32(hw_power_special) 47893aabbeSMarek Vasut mxs_reg_32(hw_power_version) 48893aabbeSMarek Vasut mxs_reg_32(hw_power_anaclkctrl) 49893aabbeSMarek Vasut mxs_reg_32(hw_power_refctrl) 50893aabbeSMarek Vasut }; 51893aabbeSMarek Vasut #endif 52893aabbeSMarek Vasut 53893aabbeSMarek Vasut #define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) 54893aabbeSMarek Vasut #define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) 55893aabbeSMarek Vasut #define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) 56893aabbeSMarek Vasut #define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) 57893aabbeSMarek Vasut #define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) 58893aabbeSMarek Vasut #define POWER_CTRL_PSWITCH_IRQ (1 << 20) 59893aabbeSMarek Vasut #define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) 60893aabbeSMarek Vasut #define POWER_CTRL_POLARITY_PSWITCH (1 << 18) 61893aabbeSMarek Vasut #define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) 62893aabbeSMarek Vasut #define POWER_CTRL_POLARITY_DC_OK (1 << 16) 63893aabbeSMarek Vasut #define POWER_CTRL_DC_OK_IRQ (1 << 15) 64893aabbeSMarek Vasut #define POWER_CTRL_ENIRQ_DC_OK (1 << 14) 65893aabbeSMarek Vasut #define POWER_CTRL_BATT_BO_IRQ (1 << 13) 66893aabbeSMarek Vasut #define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) 67893aabbeSMarek Vasut #define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) 68893aabbeSMarek Vasut #define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) 69893aabbeSMarek Vasut #define POWER_CTRL_VDDA_BO_IRQ (1 << 9) 70893aabbeSMarek Vasut #define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) 71893aabbeSMarek Vasut #define POWER_CTRL_VDDD_BO_IRQ (1 << 7) 72893aabbeSMarek Vasut #define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) 73893aabbeSMarek Vasut #define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) 74893aabbeSMarek Vasut #define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) 75893aabbeSMarek Vasut #define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) 76893aabbeSMarek Vasut #define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) 77893aabbeSMarek Vasut #define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) 78893aabbeSMarek Vasut #define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) 79893aabbeSMarek Vasut 80893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) 81893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 82893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30) 83893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30) 84893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30) 85893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30) 86893aabbeSMarek Vasut #define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) 87893aabbeSMarek Vasut #define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 88893aabbeSMarek Vasut #define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20) 89893aabbeSMarek Vasut #define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 90893aabbeSMarek Vasut #define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) 91893aabbeSMarek Vasut #define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 92893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) 93893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 94893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) 95893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) 96893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) 97893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) 98893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) 99893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) 100893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) 101893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) 102893aabbeSMarek Vasut #define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) 103893aabbeSMarek Vasut #define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) 104893aabbeSMarek Vasut #define POWER_5VCTRL_DCDC_XFER (1 << 5) 105893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) 106893aabbeSMarek Vasut #define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) 107893aabbeSMarek Vasut #define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) 108893aabbeSMarek Vasut #define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) 109893aabbeSMarek Vasut #define POWER_5VCTRL_ENABLE_DCDC (1 << 0) 110893aabbeSMarek Vasut 111893aabbeSMarek Vasut #define POWER_MINPWR_LOWPWR_4P2 (1 << 14) 112893aabbeSMarek Vasut #define POWER_MINPWR_PWD_BO (1 << 12) 113893aabbeSMarek Vasut #define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) 114893aabbeSMarek Vasut #define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) 115893aabbeSMarek Vasut #define POWER_MINPWR_ENABLE_OSC (1 << 9) 116893aabbeSMarek Vasut #define POWER_MINPWR_SELECT_OSC (1 << 8) 117893aabbeSMarek Vasut #define POWER_MINPWR_VBG_OFF (1 << 7) 118893aabbeSMarek Vasut #define POWER_MINPWR_DOUBLE_FETS (1 << 6) 119893aabbeSMarek Vasut #define POWER_MINPWR_HALFFETS (1 << 5) 120893aabbeSMarek Vasut #define POWER_MINPWR_LESSANA_I (1 << 4) 121893aabbeSMarek Vasut #define POWER_MINPWR_PWD_XTAL24 (1 << 3) 122893aabbeSMarek Vasut #define POWER_MINPWR_DC_STOPCLK (1 << 2) 123893aabbeSMarek Vasut #define POWER_MINPWR_EN_DC_PFM (1 << 1) 124893aabbeSMarek Vasut #define POWER_MINPWR_DC_HALFCLK (1 << 0) 125893aabbeSMarek Vasut 126893aabbeSMarek Vasut #define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) 127893aabbeSMarek Vasut #define POWER_CHARGE_ADJ_VOLT_OFFSET 24 128893aabbeSMarek Vasut #define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) 129893aabbeSMarek Vasut #define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) 130893aabbeSMarek Vasut #define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) 131893aabbeSMarek Vasut #define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) 132893aabbeSMarek Vasut #define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) 133893aabbeSMarek Vasut #define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) 134893aabbeSMarek Vasut #define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) 135893aabbeSMarek Vasut #define POWER_CHARGE_ENABLE_LOAD (1 << 22) 136893aabbeSMarek Vasut #define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) 137893aabbeSMarek Vasut #define POWER_CHARGE_CHRG_STS_OFF (1 << 19) 138893aabbeSMarek Vasut #define POWER_CHARGE_LIION_4P1 (1 << 18) 139893aabbeSMarek Vasut #define POWER_CHARGE_PWD_BATTCHRG (1 << 16) 140893aabbeSMarek Vasut #define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) 141893aabbeSMarek Vasut #define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) 142893aabbeSMarek Vasut #define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) 143893aabbeSMarek Vasut #define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 144893aabbeSMarek Vasut #define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) 145893aabbeSMarek Vasut #define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) 146893aabbeSMarek Vasut #define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) 147893aabbeSMarek Vasut #define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) 148893aabbeSMarek Vasut #define POWER_CHARGE_BATTCHRG_I_MASK 0x3f 149893aabbeSMarek Vasut #define POWER_CHARGE_BATTCHRG_I_OFFSET 0 150893aabbeSMarek Vasut #define POWER_CHARGE_BATTCHRG_I_10MA 0x01 151893aabbeSMarek Vasut #define POWER_CHARGE_BATTCHRG_I_20MA 0x02 152893aabbeSMarek Vasut #define POWER_CHARGE_BATTCHRG_I_50MA 0x04 153893aabbeSMarek Vasut #define POWER_CHARGE_BATTCHRG_I_100MA 0x08 154893aabbeSMarek Vasut #define POWER_CHARGE_BATTCHRG_I_200MA 0x10 155893aabbeSMarek Vasut #define POWER_CHARGE_BATTCHRG_I_400MA 0x20 156893aabbeSMarek Vasut 157893aabbeSMarek Vasut #define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) 158893aabbeSMarek Vasut #define POWER_VDDDCTRL_ADJTN_OFFSET 28 159893aabbeSMarek Vasut #define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) 160893aabbeSMarek Vasut #define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) 161893aabbeSMarek Vasut #define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) 162893aabbeSMarek Vasut #define POWER_VDDDCTRL_DISABLE_FET (1 << 20) 163893aabbeSMarek Vasut #define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) 164893aabbeSMarek Vasut #define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 165893aabbeSMarek Vasut #define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) 166893aabbeSMarek Vasut #define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) 167893aabbeSMarek Vasut #define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) 168893aabbeSMarek Vasut #define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) 169893aabbeSMarek Vasut #define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) 170893aabbeSMarek Vasut #define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 171893aabbeSMarek Vasut #define POWER_VDDDCTRL_TRG_MASK 0x1f 172893aabbeSMarek Vasut #define POWER_VDDDCTRL_TRG_OFFSET 0 173893aabbeSMarek Vasut 174893aabbeSMarek Vasut #define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) 175893aabbeSMarek Vasut #define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) 176893aabbeSMarek Vasut #define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) 177893aabbeSMarek Vasut #define POWER_VDDACTRL_DISABLE_FET (1 << 16) 178893aabbeSMarek Vasut #define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) 179893aabbeSMarek Vasut #define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 180893aabbeSMarek Vasut #define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) 181893aabbeSMarek Vasut #define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) 182893aabbeSMarek Vasut #define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) 183893aabbeSMarek Vasut #define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) 184893aabbeSMarek Vasut #define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) 185893aabbeSMarek Vasut #define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 186893aabbeSMarek Vasut #define POWER_VDDACTRL_TRG_MASK 0x1f 187893aabbeSMarek Vasut #define POWER_VDDACTRL_TRG_OFFSET 0 188893aabbeSMarek Vasut 189893aabbeSMarek Vasut #define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) 190893aabbeSMarek Vasut #define POWER_VDDIOCTRL_ADJTN_OFFSET 20 191893aabbeSMarek Vasut #define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) 192893aabbeSMarek Vasut #define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) 193893aabbeSMarek Vasut #define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) 194893aabbeSMarek Vasut #define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) 195893aabbeSMarek Vasut #define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 196893aabbeSMarek Vasut #define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) 197893aabbeSMarek Vasut #define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) 198893aabbeSMarek Vasut #define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) 199893aabbeSMarek Vasut #define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) 200893aabbeSMarek Vasut #define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) 201893aabbeSMarek Vasut #define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 202893aabbeSMarek Vasut #define POWER_VDDIOCTRL_TRG_MASK 0x1f 203893aabbeSMarek Vasut #define POWER_VDDIOCTRL_TRG_OFFSET 0 204893aabbeSMarek Vasut 205893aabbeSMarek Vasut #define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) 206893aabbeSMarek Vasut #define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) 207893aabbeSMarek Vasut #define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) 208893aabbeSMarek Vasut #define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) 209893aabbeSMarek Vasut #define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 210893aabbeSMarek Vasut #define POWER_VDDMEMCTRL_TRG_MASK 0x1f 211893aabbeSMarek Vasut #define POWER_VDDMEMCTRL_TRG_OFFSET 0 212893aabbeSMarek Vasut 213893aabbeSMarek Vasut #define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) 214893aabbeSMarek Vasut #define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 215893aabbeSMarek Vasut #define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) 216893aabbeSMarek Vasut #define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) 217893aabbeSMarek Vasut #define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) 218893aabbeSMarek Vasut #define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) 219893aabbeSMarek Vasut #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) 220893aabbeSMarek Vasut #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) 221893aabbeSMarek Vasut #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) 222893aabbeSMarek Vasut #define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) 223893aabbeSMarek Vasut #define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 224893aabbeSMarek Vasut #define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) 225893aabbeSMarek Vasut #define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) 226893aabbeSMarek Vasut #define POWER_DCDC4P2_HYST_DIR (1 << 21) 227893aabbeSMarek Vasut #define POWER_DCDC4P2_HYST_THRESH (1 << 20) 228893aabbeSMarek Vasut #define POWER_DCDC4P2_TRG_MASK (0x7 << 16) 229893aabbeSMarek Vasut #define POWER_DCDC4P2_TRG_OFFSET 16 230893aabbeSMarek Vasut #define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) 231893aabbeSMarek Vasut #define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) 232893aabbeSMarek Vasut #define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) 233893aabbeSMarek Vasut #define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) 234893aabbeSMarek Vasut #define POWER_DCDC4P2_TRG_BATT (0x4 << 16) 235893aabbeSMarek Vasut #define POWER_DCDC4P2_BO_MASK (0x1f << 8) 236893aabbeSMarek Vasut #define POWER_DCDC4P2_BO_OFFSET 8 237893aabbeSMarek Vasut #define POWER_DCDC4P2_CMPTRIP_MASK 0x1f 238893aabbeSMarek Vasut #define POWER_DCDC4P2_CMPTRIP_OFFSET 0 239893aabbeSMarek Vasut 240893aabbeSMarek Vasut #define POWER_MISC_FREQSEL_MASK (0x7 << 4) 241893aabbeSMarek Vasut #define POWER_MISC_FREQSEL_OFFSET 4 242893aabbeSMarek Vasut #define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) 243893aabbeSMarek Vasut #define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) 244893aabbeSMarek Vasut #define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) 245893aabbeSMarek Vasut #define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) 246893aabbeSMarek Vasut #define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) 247893aabbeSMarek Vasut #define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) 248893aabbeSMarek Vasut #define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) 249893aabbeSMarek Vasut #define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) 250893aabbeSMarek Vasut #define POWER_MISC_DELAY_TIMING (1 << 2) 251893aabbeSMarek Vasut #define POWER_MISC_TEST (1 << 1) 252893aabbeSMarek Vasut #define POWER_MISC_SEL_PLLCLK (1 << 0) 253893aabbeSMarek Vasut 254893aabbeSMarek Vasut #define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) 255893aabbeSMarek Vasut #define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 256893aabbeSMarek Vasut #define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f 257893aabbeSMarek Vasut #define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 258893aabbeSMarek Vasut 259893aabbeSMarek Vasut #define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) 260893aabbeSMarek Vasut #define POWER_LOOPCTRL_HYST_SIGN (1 << 19) 261893aabbeSMarek Vasut #define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) 262893aabbeSMarek Vasut #define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) 263893aabbeSMarek Vasut #define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) 264893aabbeSMarek Vasut #define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) 265893aabbeSMarek Vasut #define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) 266893aabbeSMarek Vasut #define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) 267893aabbeSMarek Vasut #define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 268893aabbeSMarek Vasut #define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) 269893aabbeSMarek Vasut #define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) 270893aabbeSMarek Vasut #define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) 271893aabbeSMarek Vasut #define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) 272893aabbeSMarek Vasut #define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) 273893aabbeSMarek Vasut #define POWER_LOOPCTRL_DC_FF_OFFSET 8 274893aabbeSMarek Vasut #define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) 275893aabbeSMarek Vasut #define POWER_LOOPCTRL_DC_R_OFFSET 4 276893aabbeSMarek Vasut #define POWER_LOOPCTRL_DC_C_MASK 0x3 277893aabbeSMarek Vasut #define POWER_LOOPCTRL_DC_C_OFFSET 0 278893aabbeSMarek Vasut #define POWER_LOOPCTRL_DC_C_MAX 0x0 279893aabbeSMarek Vasut #define POWER_LOOPCTRL_DC_C_2X 0x1 280893aabbeSMarek Vasut #define POWER_LOOPCTRL_DC_C_4X 0x2 281893aabbeSMarek Vasut #define POWER_LOOPCTRL_DC_C_MIN 0x3 282893aabbeSMarek Vasut 283893aabbeSMarek Vasut #define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) 284893aabbeSMarek Vasut #define POWER_STS_PWRUP_SOURCE_OFFSET 24 285893aabbeSMarek Vasut #define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) 286893aabbeSMarek Vasut #define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) 287893aabbeSMarek Vasut #define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) 288893aabbeSMarek Vasut #define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) 289893aabbeSMarek Vasut #define POWER_STS_PSWITCH_MASK (0x3 << 20) 290893aabbeSMarek Vasut #define POWER_STS_PSWITCH_OFFSET 20 291893aabbeSMarek Vasut #define POWER_STS_THERMAL_WARNING (1 << 19) 292893aabbeSMarek Vasut #define POWER_STS_VDDMEM_BO (1 << 18) 293893aabbeSMarek Vasut #define POWER_STS_AVALID0_STATUS (1 << 17) 294893aabbeSMarek Vasut #define POWER_STS_BVALID0_STATUS (1 << 16) 295893aabbeSMarek Vasut #define POWER_STS_VBUSVALID0_STATUS (1 << 15) 296893aabbeSMarek Vasut #define POWER_STS_SESSEND0_STATUS (1 << 14) 297893aabbeSMarek Vasut #define POWER_STS_BATT_BO (1 << 13) 298893aabbeSMarek Vasut #define POWER_STS_VDD5V_FAULT (1 << 12) 299893aabbeSMarek Vasut #define POWER_STS_CHRGSTS (1 << 11) 300893aabbeSMarek Vasut #define POWER_STS_DCDC_4P2_BO (1 << 10) 301893aabbeSMarek Vasut #define POWER_STS_DC_OK (1 << 9) 302893aabbeSMarek Vasut #define POWER_STS_VDDIO_BO (1 << 8) 303893aabbeSMarek Vasut #define POWER_STS_VDDA_BO (1 << 7) 304893aabbeSMarek Vasut #define POWER_STS_VDDD_BO (1 << 6) 305893aabbeSMarek Vasut #define POWER_STS_VDD5V_GT_VDDIO (1 << 5) 306893aabbeSMarek Vasut #define POWER_STS_VDD5V_DROOP (1 << 4) 307893aabbeSMarek Vasut #define POWER_STS_AVALID0 (1 << 3) 308893aabbeSMarek Vasut #define POWER_STS_BVALID0 (1 << 2) 309893aabbeSMarek Vasut #define POWER_STS_VBUSVALID0 (1 << 1) 310893aabbeSMarek Vasut #define POWER_STS_SESSEND0 (1 << 0) 311893aabbeSMarek Vasut 312893aabbeSMarek Vasut #define POWER_SPEED_STATUS_MASK (0xffff << 8) 313893aabbeSMarek Vasut #define POWER_SPEED_STATUS_OFFSET 8 314893aabbeSMarek Vasut #define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6) 315893aabbeSMarek Vasut #define POWER_SPEED_STATUS_SEL_OFFSET 6 316893aabbeSMarek Vasut #define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6) 317893aabbeSMarek Vasut #define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6) 318893aabbeSMarek Vasut #define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6) 319893aabbeSMarek Vasut #define POWER_SPEED_CTRL_MASK 0x3 320893aabbeSMarek Vasut #define POWER_SPEED_CTRL_OFFSET 0 321893aabbeSMarek Vasut #define POWER_SPEED_CTRL_SS_OFF 0x0 322893aabbeSMarek Vasut #define POWER_SPEED_CTRL_SS_ON 0x1 323893aabbeSMarek Vasut #define POWER_SPEED_CTRL_SS_ENABLE 0x3 324893aabbeSMarek Vasut 325893aabbeSMarek Vasut #define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) 326893aabbeSMarek Vasut #define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 327893aabbeSMarek Vasut #define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) 328893aabbeSMarek Vasut #define POWER_BATTMONITOR_EN_BATADJ (1 << 10) 329893aabbeSMarek Vasut #define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) 330893aabbeSMarek Vasut #define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) 331893aabbeSMarek Vasut #define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f 332893aabbeSMarek Vasut #define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 333893aabbeSMarek Vasut 334893aabbeSMarek Vasut #define POWER_RESET_UNLOCK_MASK (0xffff << 16) 335893aabbeSMarek Vasut #define POWER_RESET_UNLOCK_OFFSET 16 336893aabbeSMarek Vasut #define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) 337893aabbeSMarek Vasut #define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) 338893aabbeSMarek Vasut #define POWER_RESET_PWD_OFF (1 << 1) 339893aabbeSMarek Vasut #define POWER_RESET_PWD (1 << 0) 340893aabbeSMarek Vasut 341893aabbeSMarek Vasut #define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) 342893aabbeSMarek Vasut #define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) 343893aabbeSMarek Vasut #define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) 344893aabbeSMarek Vasut #define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) 345893aabbeSMarek Vasut 346893aabbeSMarek Vasut #define POWER_THERMAL_TEST (1 << 8) 347893aabbeSMarek Vasut #define POWER_THERMAL_PWD (1 << 7) 348893aabbeSMarek Vasut #define POWER_THERMAL_LOW_POWER (1 << 6) 349893aabbeSMarek Vasut #define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) 350893aabbeSMarek Vasut #define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 351893aabbeSMarek Vasut #define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) 352893aabbeSMarek Vasut #define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 353893aabbeSMarek Vasut #define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 354893aabbeSMarek Vasut 355893aabbeSMarek Vasut #define POWER_USB1CTRL_AVALID1 (1 << 3) 356893aabbeSMarek Vasut #define POWER_USB1CTRL_BVALID1 (1 << 2) 357893aabbeSMarek Vasut #define POWER_USB1CTRL_VBUSVALID1 (1 << 1) 358893aabbeSMarek Vasut #define POWER_USB1CTRL_SESSEND1 (1 << 0) 359893aabbeSMarek Vasut 360893aabbeSMarek Vasut #define POWER_SPECIAL_TEST_MASK 0xffffffff 361893aabbeSMarek Vasut #define POWER_SPECIAL_TEST_OFFSET 0 362893aabbeSMarek Vasut 363893aabbeSMarek Vasut #define POWER_VERSION_MAJOR_MASK (0xff << 24) 364893aabbeSMarek Vasut #define POWER_VERSION_MAJOR_OFFSET 24 365893aabbeSMarek Vasut #define POWER_VERSION_MINOR_MASK (0xff << 16) 366893aabbeSMarek Vasut #define POWER_VERSION_MINOR_OFFSET 16 367893aabbeSMarek Vasut #define POWER_VERSION_STEP_MASK 0xffff 368893aabbeSMarek Vasut #define POWER_VERSION_STEP_OFFSET 0 369893aabbeSMarek Vasut 370893aabbeSMarek Vasut #define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) 371893aabbeSMarek Vasut #define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) 372893aabbeSMarek Vasut #define POWER_ANACLKCTRL_OUTDIV_OFFSET 28 373893aabbeSMarek Vasut #define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) 374893aabbeSMarek Vasut #define POWER_ANACLKCTRL_CLKGATE_I (1 << 26) 375893aabbeSMarek Vasut #define POWER_ANACLKCTRL_DITHER_OFF (1 << 10) 376893aabbeSMarek Vasut #define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) 377893aabbeSMarek Vasut #define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) 378893aabbeSMarek Vasut #define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) 379893aabbeSMarek Vasut #define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 380893aabbeSMarek Vasut #define POWER_ANACLKCTRL_INDIV_MASK 0x7 381893aabbeSMarek Vasut #define POWER_ANACLKCTRL_INDIV_OFFSET 0 382893aabbeSMarek Vasut 383893aabbeSMarek Vasut #define POWER_REFCTRL_FASTSETTLING (1 << 26) 384893aabbeSMarek Vasut #define POWER_REFCTRL_RAISE_REF (1 << 25) 385893aabbeSMarek Vasut #define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) 386893aabbeSMarek Vasut #define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) 387893aabbeSMarek Vasut #define POWER_REFCTRL_VBG_ADJ_OFFSET 20 388893aabbeSMarek Vasut #define POWER_REFCTRL_LOW_PWR (1 << 19) 389893aabbeSMarek Vasut #define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) 390893aabbeSMarek Vasut #define POWER_REFCTRL_BIAS_CTRL_OFFSET 16 391893aabbeSMarek Vasut #define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) 392893aabbeSMarek Vasut #define POWER_REFCTRL_ADJ_ANA (1 << 13) 393893aabbeSMarek Vasut #define POWER_REFCTRL_ADJ_VAG (1 << 12) 394893aabbeSMarek Vasut #define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) 395893aabbeSMarek Vasut #define POWER_REFCTRL_ANA_REFVAL_OFFSET 8 396893aabbeSMarek Vasut #define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) 397893aabbeSMarek Vasut #define POWER_REFCTRL_VAG_VAL_OFFSET 4 398893aabbeSMarek Vasut 399893aabbeSMarek Vasut #endif /* __MX28_REGS_POWER_H__ */ 400