1 /* 2 * Freescale i.MX23 Power Controller Register Definitions 3 * 4 * Copyright (C) 2012 Marek Vasut <marex@denx.de> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 #ifndef __MX23_REGS_POWER_H__ 23 #define __MX23_REGS_POWER_H__ 24 25 #include <asm/arch/regs-common.h> 26 27 #ifndef __ASSEMBLY__ 28 struct mxs_power_regs { 29 mxs_reg_32(hw_power_ctrl) 30 mxs_reg_32(hw_power_5vctrl) 31 mxs_reg_32(hw_power_minpwr) 32 mxs_reg_32(hw_power_charge) 33 uint32_t hw_power_vdddctrl; 34 uint32_t reserved_vddd[3]; 35 uint32_t hw_power_vddactrl; 36 uint32_t reserved_vdda[3]; 37 uint32_t hw_power_vddioctrl; 38 uint32_t reserved_vddio[3]; 39 uint32_t hw_power_vddmemctrl; 40 uint32_t reserved_vddmem[3]; 41 uint32_t hw_power_dcdc4p2; 42 uint32_t reserved_dcdc4p2[3]; 43 uint32_t hw_power_misc; 44 uint32_t reserved_misc[3]; 45 uint32_t hw_power_dclimits; 46 uint32_t reserved_dclimits[3]; 47 mxs_reg_32(hw_power_loopctrl) 48 uint32_t hw_power_sts; 49 uint32_t reserved_sts[3]; 50 mxs_reg_32(hw_power_speed) 51 uint32_t hw_power_battmonitor; 52 uint32_t reserved_battmonitor[3]; 53 54 uint32_t reserved1[4]; 55 56 mxs_reg_32(hw_power_reset) 57 58 uint32_t reserved2[4]; 59 60 mxs_reg_32(hw_power_special) 61 mxs_reg_32(hw_power_version) 62 }; 63 #endif 64 65 #define POWER_CTRL_CLKGATE (1 << 30) 66 #define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) 67 #define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) 68 #define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) 69 #define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) 70 #define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) 71 #define POWER_CTRL_PSWITCH_IRQ (1 << 20) 72 #define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) 73 #define POWER_CTRL_POLARITY_PSWITCH (1 << 18) 74 #define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) 75 #define POWER_CTRL_POLARITY_DC_OK (1 << 16) 76 #define POWER_CTRL_DC_OK_IRQ (1 << 15) 77 #define POWER_CTRL_ENIRQ_DC_OK (1 << 14) 78 #define POWER_CTRL_BATT_BO_IRQ (1 << 13) 79 #define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) 80 #define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) 81 #define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) 82 #define POWER_CTRL_VDDA_BO_IRQ (1 << 9) 83 #define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) 84 #define POWER_CTRL_VDDD_BO_IRQ (1 << 7) 85 #define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) 86 #define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) 87 #define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) 88 #define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) 89 #define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) 90 #define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) 91 #define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) 92 93 #define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28) 94 #define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28 95 #define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28) 96 #define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28) 97 #define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28) 98 #define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28) 99 #define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) 100 #define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 101 #define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20) 102 #define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 103 #define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) 104 #define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 105 #define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) 106 #define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 107 #define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) 108 #define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) 109 #define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) 110 #define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) 111 #define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) 112 #define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) 113 #define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) 114 #define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) 115 #define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) 116 #define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) 117 #define POWER_5VCTRL_DCDC_XFER (1 << 5) 118 #define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) 119 #define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) 120 #define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) 121 #define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) 122 #define POWER_5VCTRL_ENABLE_DCDC (1 << 0) 123 124 #define POWER_MINPWR_LOWPWR_4P2 (1 << 14) 125 #define POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13) 126 #define POWER_MINPWR_PWD_BO (1 << 12) 127 #define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) 128 #define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) 129 #define POWER_MINPWR_ENABLE_OSC (1 << 9) 130 #define POWER_MINPWR_SELECT_OSC (1 << 8) 131 #define POWER_MINPWR_VBG_OFF (1 << 7) 132 #define POWER_MINPWR_DOUBLE_FETS (1 << 6) 133 #define POWER_MINPWR_HALFFETS (1 << 5) 134 #define POWER_MINPWR_LESSANA_I (1 << 4) 135 #define POWER_MINPWR_PWD_XTAL24 (1 << 3) 136 #define POWER_MINPWR_DC_STOPCLK (1 << 2) 137 #define POWER_MINPWR_EN_DC_PFM (1 << 1) 138 #define POWER_MINPWR_DC_HALFCLK (1 << 0) 139 140 #define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) 141 #define POWER_CHARGE_ADJ_VOLT_OFFSET 24 142 #define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) 143 #define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) 144 #define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) 145 #define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) 146 #define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) 147 #define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) 148 #define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) 149 #define POWER_CHARGE_ENABLE_LOAD (1 << 22) 150 #define POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21) 151 #define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) 152 #define POWER_CHARGE_CHRG_STS_OFF (1 << 19) 153 #define POWER_CHARGE_USE_EXTERN_R (1 << 17) 154 #define POWER_CHARGE_PWD_BATTCHRG (1 << 16) 155 #define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) 156 #define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 157 #define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) 158 #define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) 159 #define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) 160 #define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) 161 #define POWER_CHARGE_BATTCHRG_I_MASK 0x3f 162 #define POWER_CHARGE_BATTCHRG_I_OFFSET 0 163 #define POWER_CHARGE_BATTCHRG_I_10MA 0x01 164 #define POWER_CHARGE_BATTCHRG_I_20MA 0x02 165 #define POWER_CHARGE_BATTCHRG_I_50MA 0x04 166 #define POWER_CHARGE_BATTCHRG_I_100MA 0x08 167 #define POWER_CHARGE_BATTCHRG_I_200MA 0x10 168 #define POWER_CHARGE_BATTCHRG_I_400MA 0x20 169 170 #define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) 171 #define POWER_VDDDCTRL_ADJTN_OFFSET 28 172 #define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) 173 #define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) 174 #define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) 175 #define POWER_VDDDCTRL_DISABLE_FET (1 << 20) 176 #define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) 177 #define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 178 #define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) 179 #define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) 180 #define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) 181 #define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) 182 #define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) 183 #define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 184 #define POWER_VDDDCTRL_TRG_MASK 0x1f 185 #define POWER_VDDDCTRL_TRG_OFFSET 0 186 187 #define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) 188 #define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) 189 #define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) 190 #define POWER_VDDACTRL_DISABLE_FET (1 << 16) 191 #define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) 192 #define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 193 #define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) 194 #define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) 195 #define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) 196 #define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) 197 #define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) 198 #define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 199 #define POWER_VDDACTRL_TRG_MASK 0x1f 200 #define POWER_VDDACTRL_TRG_OFFSET 0 201 202 #define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) 203 #define POWER_VDDIOCTRL_ADJTN_OFFSET 20 204 #define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) 205 #define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) 206 #define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) 207 #define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) 208 #define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 209 #define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) 210 #define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) 211 #define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) 212 #define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) 213 #define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) 214 #define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 215 #define POWER_VDDIOCTRL_TRG_MASK 0x1f 216 #define POWER_VDDIOCTRL_TRG_OFFSET 0 217 218 #define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) 219 #define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) 220 #define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) 221 #define POWER_VDDMEMCTRL_TRG_MASK 0x1f 222 #define POWER_VDDMEMCTRL_TRG_OFFSET 0 223 224 #define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) 225 #define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 226 #define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) 227 #define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) 228 #define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) 229 #define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) 230 #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) 231 #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) 232 #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) 233 #define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) 234 #define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 235 #define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) 236 #define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) 237 #define POWER_DCDC4P2_HYST_DIR (1 << 21) 238 #define POWER_DCDC4P2_HYST_THRESH (1 << 20) 239 #define POWER_DCDC4P2_TRG_MASK (0x7 << 16) 240 #define POWER_DCDC4P2_TRG_OFFSET 16 241 #define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) 242 #define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) 243 #define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) 244 #define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) 245 #define POWER_DCDC4P2_TRG_BATT (0x4 << 16) 246 #define POWER_DCDC4P2_BO_MASK (0x1f << 8) 247 #define POWER_DCDC4P2_BO_OFFSET 8 248 #define POWER_DCDC4P2_CMPTRIP_MASK 0x1f 249 #define POWER_DCDC4P2_CMPTRIP_OFFSET 0 250 251 #define POWER_MISC_FREQSEL_MASK (0x7 << 4) 252 #define POWER_MISC_FREQSEL_OFFSET 4 253 #define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) 254 #define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) 255 #define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) 256 #define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) 257 #define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) 258 #define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) 259 #define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) 260 #define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) 261 #define POWER_MISC_DELAY_TIMING (1 << 2) 262 #define POWER_MISC_TEST (1 << 1) 263 #define POWER_MISC_SEL_PLLCLK (1 << 0) 264 265 #define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) 266 #define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 267 #define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f 268 #define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 269 270 #define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) 271 #define POWER_LOOPCTRL_HYST_SIGN (1 << 19) 272 #define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) 273 #define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) 274 #define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) 275 #define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) 276 #define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) 277 #define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) 278 #define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 279 #define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) 280 #define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) 281 #define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) 282 #define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) 283 #define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) 284 #define POWER_LOOPCTRL_DC_FF_OFFSET 8 285 #define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) 286 #define POWER_LOOPCTRL_DC_R_OFFSET 4 287 #define POWER_LOOPCTRL_DC_C_MASK 0x3 288 #define POWER_LOOPCTRL_DC_C_OFFSET 0 289 #define POWER_LOOPCTRL_DC_C_MAX 0x0 290 #define POWER_LOOPCTRL_DC_C_2X 0x1 291 #define POWER_LOOPCTRL_DC_C_4X 0x2 292 #define POWER_LOOPCTRL_DC_C_MIN 0x3 293 294 #define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) 295 #define POWER_STS_PWRUP_SOURCE_OFFSET 24 296 #define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) 297 #define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) 298 #define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) 299 #define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) 300 #define POWER_STS_PSWITCH_MASK (0x3 << 20) 301 #define POWER_STS_PSWITCH_OFFSET 20 302 #define POWER_STS_AVALID0_STATUS (1 << 17) 303 #define POWER_STS_BVALID0_STATUS (1 << 16) 304 #define POWER_STS_VBUSVALID0_STATUS (1 << 15) 305 #define POWER_STS_SESSEND0_STATUS (1 << 14) 306 #define POWER_STS_BATT_BO (1 << 13) 307 #define POWER_STS_VDD5V_FAULT (1 << 12) 308 #define POWER_STS_CHRGSTS (1 << 11) 309 #define POWER_STS_DCDC_4P2_BO (1 << 10) 310 #define POWER_STS_DC_OK (1 << 9) 311 #define POWER_STS_VDDIO_BO (1 << 8) 312 #define POWER_STS_VDDA_BO (1 << 7) 313 #define POWER_STS_VDDD_BO (1 << 6) 314 #define POWER_STS_VDD5V_GT_VDDIO (1 << 5) 315 #define POWER_STS_VDD5V_DROOP (1 << 4) 316 #define POWER_STS_AVALID0 (1 << 3) 317 #define POWER_STS_BVALID0 (1 << 2) 318 #define POWER_STS_VBUSVALID0 (1 << 1) 319 #define POWER_STS_SESSEND0 (1 << 0) 320 321 #define POWER_SPEED_STATUS_MASK (0xff << 16) 322 #define POWER_SPEED_STATUS_OFFSET 16 323 #define POWER_SPEED_CTRL_MASK 0x3 324 #define POWER_SPEED_CTRL_OFFSET 0 325 #define POWER_SPEED_CTRL_SS_OFF 0x0 326 #define POWER_SPEED_CTRL_SS_ON 0x1 327 #define POWER_SPEED_CTRL_SS_ENABLE 0x3 328 329 #define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) 330 #define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 331 #define POWER_BATTMONITOR_EN_BATADJ (1 << 10) 332 #define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) 333 #define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) 334 #define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f 335 #define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 336 337 #define POWER_RESET_UNLOCK_MASK (0xffff << 16) 338 #define POWER_RESET_UNLOCK_OFFSET 16 339 #define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) 340 #define POWER_RESET_PWD_OFF (1 << 1) 341 #define POWER_RESET_PWD (1 << 0) 342 343 #define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) 344 #define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) 345 #define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) 346 #define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) 347 348 #define POWER_SPECIAL_TEST_MASK 0xffffffff 349 #define POWER_SPECIAL_TEST_OFFSET 0 350 351 #define POWER_VERSION_MAJOR_MASK (0xff << 24) 352 #define POWER_VERSION_MAJOR_OFFSET 24 353 #define POWER_VERSION_MINOR_MASK (0xff << 16) 354 #define POWER_VERSION_MINOR_OFFSET 16 355 #define POWER_VERSION_STEP_MASK 0xffff 356 #define POWER_VERSION_STEP_OFFSET 0 357 358 #endif /* __MX23_REGS_POWER_H__ */ 359