1 /* 2 * Freescale i.MX28 PINCTRL Register Definitions 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __MX28_REGS_PINCTRL_H__ 14 #define __MX28_REGS_PINCTRL_H__ 15 16 #include <asm/mach-imx/regs-common.h> 17 18 #ifndef __ASSEMBLY__ 19 struct mxs_pinctrl_regs { 20 mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */ 21 22 uint32_t reserved1[60]; 23 24 mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ 25 mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ 26 mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ 27 mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ 28 mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ 29 mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ 30 mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ 31 mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ 32 mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ 33 mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ 34 mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ 35 mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ 36 mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ 37 mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ 38 39 uint32_t reserved2[72]; 40 41 mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */ 42 mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */ 43 mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */ 44 mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */ 45 mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */ 46 mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */ 47 mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */ 48 mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */ 49 mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */ 50 mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */ 51 mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ 52 mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ 53 mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ 54 mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ 55 mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ 56 mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ 57 mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */ 58 mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */ 59 mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */ 60 mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */ 61 62 uint32_t reserved3[112]; 63 64 mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */ 65 mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */ 66 mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */ 67 mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */ 68 mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */ 69 mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */ 70 mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */ 71 72 uint32_t reserved4[36]; 73 74 mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */ 75 mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */ 76 mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */ 77 mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */ 78 mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */ 79 80 uint32_t reserved5[108]; 81 82 mxs_reg_32(hw_pinctrl_din0) /* 0x900 */ 83 mxs_reg_32(hw_pinctrl_din1) /* 0x910 */ 84 mxs_reg_32(hw_pinctrl_din2) /* 0x920 */ 85 mxs_reg_32(hw_pinctrl_din3) /* 0x930 */ 86 mxs_reg_32(hw_pinctrl_din4) /* 0x940 */ 87 88 uint32_t reserved6[108]; 89 90 mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */ 91 mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */ 92 mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */ 93 mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */ 94 mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */ 95 96 uint32_t reserved7[300]; 97 98 mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ 99 mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ 100 mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ 101 mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ 102 mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ 103 104 uint32_t reserved8[44]; 105 106 mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ 107 mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ 108 mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ 109 mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ 110 mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ 111 112 uint32_t reserved9[44]; 113 114 mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ 115 mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ 116 mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ 117 mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ 118 mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ 119 120 uint32_t reserved10[44]; 121 122 mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ 123 mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ 124 mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ 125 mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ 126 mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ 127 128 uint32_t reserved11[44]; 129 130 mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ 131 mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ 132 mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ 133 mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ 134 mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ 135 136 uint32_t reserved12[380]; 137 138 mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ 139 140 uint32_t reserved13[76]; 141 142 mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ 143 }; 144 #endif 145 146 #define PINCTRL_CTRL_SFTRST (1 << 31) 147 #define PINCTRL_CTRL_CLKGATE (1 << 30) 148 #define PINCTRL_CTRL_PRESENT4 (1 << 24) 149 #define PINCTRL_CTRL_PRESENT3 (1 << 23) 150 #define PINCTRL_CTRL_PRESENT2 (1 << 22) 151 #define PINCTRL_CTRL_PRESENT1 (1 << 21) 152 #define PINCTRL_CTRL_PRESENT0 (1 << 20) 153 #define PINCTRL_CTRL_IRQOUT4 (1 << 4) 154 #define PINCTRL_CTRL_IRQOUT3 (1 << 3) 155 #define PINCTRL_CTRL_IRQOUT2 (1 << 2) 156 #define PINCTRL_CTRL_IRQOUT1 (1 << 1) 157 #define PINCTRL_CTRL_IRQOUT0 (1 << 0) 158 159 #define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) 160 #define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 161 #define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12) 162 #define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12 163 #define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10) 164 #define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10 165 #define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8) 166 #define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8 167 #define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6) 168 #define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6 169 #define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4) 170 #define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4 171 #define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2) 172 #define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2 173 #define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0) 174 #define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0 175 176 #define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24) 177 #define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24 178 #define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22) 179 #define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22 180 #define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20) 181 #define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20 182 #define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18) 183 #define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18 184 #define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16) 185 #define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16 186 #define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14) 187 #define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14 188 #define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12) 189 #define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12 190 #define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10) 191 #define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10 192 #define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8) 193 #define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8 194 #define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6) 195 #define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6 196 #define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4) 197 #define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4 198 #define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2) 199 #define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2 200 #define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0) 201 #define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0 202 203 #define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30) 204 #define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30 205 #define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28) 206 #define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28 207 #define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26) 208 #define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26 209 #define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24) 210 #define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24 211 #define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22) 212 #define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22 213 #define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20) 214 #define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20 215 #define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18) 216 #define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18 217 #define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16) 218 #define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16 219 #define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14) 220 #define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14 221 #define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12) 222 #define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12 223 #define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10) 224 #define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10 225 #define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8) 226 #define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8 227 #define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6) 228 #define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6 229 #define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4) 230 #define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4 231 #define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2) 232 #define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2 233 #define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0) 234 #define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0 235 236 #define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30) 237 #define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30 238 #define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28) 239 #define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28 240 #define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26) 241 #define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26 242 #define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24) 243 #define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24 244 #define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22) 245 #define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22 246 #define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20) 247 #define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20 248 #define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18) 249 #define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18 250 #define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16) 251 #define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16 252 #define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14) 253 #define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14 254 #define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12) 255 #define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12 256 #define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10) 257 #define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10 258 #define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8) 259 #define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8 260 #define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6) 261 #define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6 262 #define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4) 263 #define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4 264 #define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2) 265 #define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2 266 #define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0) 267 #define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0 268 269 #define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30) 270 #define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30 271 #define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28) 272 #define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28 273 #define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26) 274 #define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26 275 #define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24) 276 #define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24 277 #define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20) 278 #define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20 279 #define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18) 280 #define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18 281 #define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16) 282 #define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16 283 #define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14) 284 #define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14 285 #define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12) 286 #define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12 287 #define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10) 288 #define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10 289 #define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8) 290 #define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8 291 #define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6) 292 #define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6 293 #define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4) 294 #define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4 295 #define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2) 296 #define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2 297 #define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0) 298 #define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0 299 300 #define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22) 301 #define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22 302 #define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20) 303 #define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20 304 #define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18) 305 #define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18 306 #define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16) 307 #define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16 308 #define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10) 309 #define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10 310 #define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8) 311 #define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8 312 #define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6) 313 #define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6 314 #define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4) 315 #define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4 316 #define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2) 317 #define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2 318 #define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0) 319 #define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0 320 321 #define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30) 322 #define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30 323 #define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28) 324 #define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28 325 #define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26) 326 #define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26 327 #define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24) 328 #define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24 329 #define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22) 330 #define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22 331 #define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20) 332 #define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20 333 #define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18) 334 #define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18 335 #define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16) 336 #define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16 337 #define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14) 338 #define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14 339 #define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12) 340 #define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12 341 #define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10) 342 #define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10 343 #define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8) 344 #define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8 345 #define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6) 346 #define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6 347 #define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4) 348 #define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4 349 #define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2) 350 #define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2 351 #define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0) 352 #define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0 353 354 #define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28) 355 #define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28 356 #define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26) 357 #define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26 358 #define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24) 359 #define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24 360 #define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22) 361 #define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22 362 #define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20) 363 #define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20 364 #define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18) 365 #define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18 366 #define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16) 367 #define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16 368 #define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14) 369 #define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14 370 #define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12) 371 #define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12 372 #define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10) 373 #define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10 374 #define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8) 375 #define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8 376 #define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4) 377 #define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4 378 #define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2) 379 #define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2 380 #define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0) 381 #define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0 382 383 #define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30) 384 #define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30 385 #define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28) 386 #define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28 387 #define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26) 388 #define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26 389 #define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24) 390 #define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24 391 #define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22) 392 #define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22 393 #define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20) 394 #define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20 395 #define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18) 396 #define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18 397 #define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16) 398 #define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16 399 #define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14) 400 #define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14 401 #define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12) 402 #define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12 403 #define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10) 404 #define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10 405 #define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8) 406 #define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8 407 #define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6) 408 #define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6 409 #define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4) 410 #define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4 411 #define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2) 412 #define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2 413 #define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0) 414 #define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0 415 416 #define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8) 417 #define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8 418 #define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0) 419 #define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0 420 421 #define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30) 422 #define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30 423 #define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28) 424 #define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28 425 #define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26) 426 #define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26 427 #define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24) 428 #define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24 429 #define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22) 430 #define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22 431 #define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20) 432 #define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20 433 #define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18) 434 #define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18 435 #define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16) 436 #define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16 437 #define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14) 438 #define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14 439 #define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12) 440 #define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12 441 #define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10) 442 #define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10 443 #define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8) 444 #define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8 445 #define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6) 446 #define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6 447 #define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4) 448 #define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4 449 #define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2) 450 #define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2 451 #define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0) 452 #define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0 453 454 #define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20) 455 #define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20 456 #define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14) 457 #define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14 458 #define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12) 459 #define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12 460 #define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10) 461 #define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10 462 #define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8) 463 #define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8 464 #define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6) 465 #define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6 466 #define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4) 467 #define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4 468 #define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2) 469 #define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2 470 #define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0) 471 #define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0 472 473 #define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28) 474 #define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28 475 #define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26) 476 #define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26 477 #define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24) 478 #define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24 479 #define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22) 480 #define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22 481 #define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20) 482 #define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20 483 #define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18) 484 #define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18 485 #define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16) 486 #define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16 487 #define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14) 488 #define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14 489 #define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12) 490 #define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12 491 #define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10) 492 #define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10 493 #define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8) 494 #define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8 495 #define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6) 496 #define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6 497 #define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4) 498 #define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4 499 #define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2) 500 #define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2 501 #define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0) 502 #define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0 503 504 #define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16) 505 #define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16 506 #define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14) 507 #define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14 508 #define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12) 509 #define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12 510 #define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10) 511 #define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10 512 #define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8) 513 #define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8 514 #define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6) 515 #define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6 516 #define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4) 517 #define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4 518 #define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2) 519 #define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2 520 #define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) 521 #define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 522 523 #define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) 524 #define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) 525 #define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 526 #define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) 527 #define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) 528 #define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 529 #define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) 530 #define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) 531 #define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 532 #define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) 533 #define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) 534 #define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 535 #define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) 536 #define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) 537 #define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 538 #define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) 539 #define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) 540 #define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 541 #define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) 542 #define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) 543 #define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 544 #define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) 545 #define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) 546 #define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 547 548 #define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) 549 #define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) 550 #define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 551 #define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) 552 #define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) 553 #define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 554 #define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) 555 #define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) 556 #define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 557 #define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) 558 #define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) 559 #define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 560 #define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) 561 #define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) 562 #define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 563 #define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) 564 #define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) 565 #define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 566 #define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) 567 #define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) 568 #define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 569 #define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) 570 #define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) 571 #define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 572 573 #define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) 574 #define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) 575 #define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 576 #define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) 577 #define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) 578 #define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 579 #define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) 580 #define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) 581 #define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 582 #define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) 583 #define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) 584 #define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 585 #define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) 586 #define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) 587 #define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 588 589 #define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) 590 #define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) 591 #define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 592 #define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) 593 #define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) 594 #define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 595 #define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) 596 #define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) 597 #define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 598 #define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) 599 #define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) 600 #define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 601 #define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) 602 #define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) 603 #define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 604 #define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) 605 #define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) 606 #define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 607 #define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) 608 #define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) 609 #define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 610 #define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) 611 #define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) 612 #define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 613 614 #define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) 615 #define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) 616 #define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 617 #define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) 618 #define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) 619 #define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 620 #define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) 621 #define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) 622 #define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 623 #define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) 624 #define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) 625 #define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 626 #define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) 627 #define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) 628 #define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 629 #define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) 630 #define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) 631 #define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 632 #define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) 633 #define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) 634 #define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 635 #define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) 636 #define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) 637 #define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 638 639 #define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) 640 #define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) 641 #define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 642 #define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) 643 #define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) 644 #define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 645 #define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) 646 #define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) 647 #define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 648 #define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) 649 #define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) 650 #define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 651 #define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) 652 #define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) 653 #define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 654 #define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) 655 #define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) 656 #define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 657 #define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) 658 #define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) 659 #define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 660 #define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) 661 #define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) 662 #define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 663 664 #define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) 665 #define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) 666 #define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 667 #define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) 668 #define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) 669 #define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 670 #define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) 671 #define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) 672 #define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 673 #define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) 674 #define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) 675 #define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 676 #define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) 677 #define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) 678 #define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 679 #define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) 680 #define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) 681 #define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 682 #define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) 683 #define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) 684 #define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 685 #define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) 686 #define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) 687 #define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 688 689 #define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) 690 #define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) 691 #define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 692 #define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) 693 #define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) 694 #define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 695 #define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) 696 #define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) 697 #define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 698 #define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) 699 #define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) 700 #define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 701 #define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) 702 #define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) 703 #define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 704 #define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) 705 #define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) 706 #define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 707 #define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) 708 #define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) 709 #define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 710 #define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) 711 #define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) 712 #define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 713 714 #define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) 715 #define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) 716 #define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 717 #define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) 718 #define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) 719 #define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 720 #define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) 721 #define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) 722 #define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 723 #define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) 724 #define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) 725 #define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 726 #define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) 727 #define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) 728 #define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 729 #define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) 730 #define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) 731 #define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 732 #define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) 733 #define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) 734 #define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 735 736 #define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) 737 #define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) 738 #define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 739 #define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) 740 #define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) 741 #define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 742 #define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) 743 #define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) 744 #define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 745 #define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) 746 #define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) 747 #define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 748 #define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) 749 #define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) 750 #define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 751 #define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) 752 #define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) 753 #define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 754 755 #define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) 756 #define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) 757 #define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 758 #define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) 759 #define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) 760 #define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 761 #define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) 762 #define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) 763 #define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 764 #define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) 765 #define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) 766 #define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 767 768 #define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) 769 #define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) 770 #define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 771 #define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) 772 #define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) 773 #define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 774 #define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) 775 #define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) 776 #define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 777 #define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) 778 #define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) 779 #define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 780 #define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) 781 #define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) 782 #define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 783 #define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) 784 #define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) 785 #define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 786 #define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) 787 #define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) 788 #define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 789 #define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) 790 #define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) 791 #define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 792 793 #define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) 794 #define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) 795 #define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 796 #define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) 797 #define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) 798 #define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 799 #define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) 800 #define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) 801 #define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 802 #define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) 803 #define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) 804 #define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 805 #define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) 806 #define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) 807 #define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 808 #define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) 809 #define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) 810 #define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 811 #define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) 812 #define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) 813 #define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 814 #define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) 815 #define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) 816 #define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 817 818 #define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) 819 #define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) 820 #define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 821 #define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) 822 #define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) 823 #define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 824 #define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) 825 #define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) 826 #define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 827 #define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) 828 #define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) 829 #define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 830 #define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) 831 #define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) 832 #define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 833 #define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) 834 #define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) 835 #define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 836 #define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) 837 #define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) 838 #define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 839 840 #define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) 841 #define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) 842 #define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 843 #define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) 844 #define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) 845 #define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 846 #define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) 847 #define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) 848 #define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 849 #define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) 850 #define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) 851 #define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 852 #define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) 853 #define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) 854 #define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 855 #define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) 856 #define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) 857 #define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 858 #define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) 859 #define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) 860 #define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 861 862 #define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) 863 #define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) 864 #define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 865 #define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) 866 #define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) 867 #define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 868 #define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) 869 #define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) 870 #define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 871 #define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) 872 #define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) 873 #define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 874 #define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) 875 #define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) 876 #define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 877 #define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) 878 #define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) 879 #define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 880 #define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) 881 #define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) 882 #define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 883 #define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) 884 #define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) 885 #define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 886 887 #define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) 888 #define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) 889 #define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 890 #define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) 891 #define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) 892 #define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 893 #define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) 894 #define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) 895 #define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 896 #define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) 897 #define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) 898 #define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 899 #define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) 900 #define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) 901 #define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 902 #define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) 903 #define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) 904 #define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 905 #define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) 906 #define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) 907 #define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 908 #define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) 909 #define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) 910 #define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 911 912 #define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) 913 #define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) 914 #define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 915 #define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) 916 #define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) 917 #define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 918 919 #define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) 920 #define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) 921 #define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) 922 #define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) 923 #define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) 924 #define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) 925 #define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) 926 #define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) 927 #define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) 928 #define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) 929 #define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) 930 #define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) 931 #define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) 932 #define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) 933 #define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) 934 #define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) 935 #define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) 936 #define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) 937 #define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) 938 #define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) 939 #define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) 940 941 #define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) 942 #define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) 943 #define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) 944 #define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) 945 #define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) 946 #define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) 947 #define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) 948 #define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) 949 #define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) 950 #define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) 951 #define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) 952 #define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) 953 #define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) 954 #define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) 955 #define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) 956 #define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) 957 #define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) 958 #define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) 959 #define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) 960 #define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) 961 #define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) 962 #define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) 963 #define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) 964 #define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) 965 #define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) 966 #define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) 967 #define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) 968 #define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) 969 #define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) 970 #define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) 971 #define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) 972 #define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) 973 974 #define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) 975 #define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) 976 #define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) 977 #define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) 978 #define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) 979 #define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) 980 #define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) 981 #define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) 982 #define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) 983 #define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) 984 #define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) 985 #define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) 986 #define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) 987 #define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) 988 #define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) 989 #define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) 990 #define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) 991 #define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) 992 #define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) 993 #define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) 994 #define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) 995 #define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) 996 #define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) 997 #define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) 998 #define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) 999 1000 #define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) 1001 #define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) 1002 #define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) 1003 #define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) 1004 #define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) 1005 #define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) 1006 #define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) 1007 #define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) 1008 #define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) 1009 #define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) 1010 #define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) 1011 #define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) 1012 #define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) 1013 #define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) 1014 #define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) 1015 #define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) 1016 #define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) 1017 #define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) 1018 #define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) 1019 #define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) 1020 #define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) 1021 #define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) 1022 #define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) 1023 #define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) 1024 #define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) 1025 #define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) 1026 #define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) 1027 #define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) 1028 #define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) 1029 #define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) 1030 1031 #define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) 1032 #define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) 1033 #define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) 1034 #define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) 1035 #define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) 1036 #define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) 1037 #define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) 1038 #define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) 1039 #define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) 1040 #define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) 1041 #define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) 1042 #define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) 1043 #define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) 1044 #define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) 1045 #define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) 1046 #define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) 1047 #define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) 1048 #define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) 1049 1050 #define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) 1051 #define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) 1052 #define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) 1053 #define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) 1054 #define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) 1055 #define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) 1056 #define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) 1057 #define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) 1058 #define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) 1059 #define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) 1060 #define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) 1061 #define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) 1062 #define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) 1063 #define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) 1064 #define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) 1065 #define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) 1066 #define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) 1067 #define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) 1068 #define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) 1069 #define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) 1070 #define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) 1071 #define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) 1072 #define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) 1073 #define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) 1074 #define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) 1075 1076 #define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) 1077 #define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) 1078 #define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) 1079 #define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) 1080 #define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) 1081 #define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) 1082 #define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) 1083 #define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) 1084 #define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) 1085 #define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) 1086 #define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) 1087 #define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) 1088 #define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) 1089 #define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) 1090 #define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) 1091 #define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) 1092 #define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) 1093 #define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) 1094 #define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) 1095 #define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) 1096 #define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) 1097 #define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) 1098 #define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) 1099 #define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) 1100 1101 #define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff 1102 #define PINCTRL_DOUT0_DOUT_OFFSET 0 1103 1104 #define PINCTRL_DOUT1_DOUT_MASK 0xffffffff 1105 #define PINCTRL_DOUT1_DOUT_OFFSET 0 1106 1107 #define PINCTRL_DOUT2_DOUT_MASK 0xfffffff 1108 #define PINCTRL_DOUT2_DOUT_OFFSET 0 1109 1110 #define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff 1111 #define PINCTRL_DOUT3_DOUT_OFFSET 0 1112 1113 #define PINCTRL_DOUT4_DOUT_MASK 0x1fffff 1114 #define PINCTRL_DOUT4_DOUT_OFFSET 0 1115 1116 #define PINCTRL_DIN0_DIN_MASK 0x1fffffff 1117 #define PINCTRL_DIN0_DIN_OFFSET 0 1118 1119 #define PINCTRL_DIN1_DIN_MASK 0xffffffff 1120 #define PINCTRL_DIN1_DIN_OFFSET 0 1121 1122 #define PINCTRL_DIN2_DIN_MASK 0xfffffff 1123 #define PINCTRL_DIN2_DIN_OFFSET 0 1124 1125 #define PINCTRL_DIN3_DIN_MASK 0x7fffffff 1126 #define PINCTRL_DIN3_DIN_OFFSET 0 1127 1128 #define PINCTRL_DIN4_DIN_MASK 0x1fffff 1129 #define PINCTRL_DIN4_DIN_OFFSET 0 1130 1131 #define PINCTRL_DOE0_DOE_MASK 0x1fffffff 1132 #define PINCTRL_DOE0_DOE_OFFSET 0 1133 1134 #define PINCTRL_DOE1_DOE_MASK 0xffffffff 1135 #define PINCTRL_DOE1_DOE_OFFSET 0 1136 1137 #define PINCTRL_DOE2_DOE_MASK 0xfffffff 1138 #define PINCTRL_DOE2_DOE_OFFSET 0 1139 1140 #define PINCTRL_DOE3_DOE_MASK 0x7fffffff 1141 #define PINCTRL_DOE3_DOE_OFFSET 0 1142 1143 #define PINCTRL_DOE4_DOE_MASK 0x1fffff 1144 #define PINCTRL_DOE4_DOE_OFFSET 0 1145 1146 #define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff 1147 #define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0 1148 1149 #define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff 1150 #define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0 1151 1152 #define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff 1153 #define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0 1154 1155 #define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff 1156 #define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0 1157 1158 #define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff 1159 #define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0 1160 1161 #define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff 1162 #define PINCTRL_IRQEN0_IRQEN_OFFSET 0 1163 1164 #define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff 1165 #define PINCTRL_IRQEN1_IRQEN_OFFSET 0 1166 1167 #define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff 1168 #define PINCTRL_IRQEN2_IRQEN_OFFSET 0 1169 1170 #define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff 1171 #define PINCTRL_IRQEN3_IRQEN_OFFSET 0 1172 1173 #define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff 1174 #define PINCTRL_IRQEN4_IRQEN_OFFSET 0 1175 1176 #define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff 1177 #define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0 1178 1179 #define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff 1180 #define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0 1181 1182 #define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff 1183 #define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0 1184 1185 #define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff 1186 #define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0 1187 1188 #define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff 1189 #define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0 1190 1191 #define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff 1192 #define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0 1193 1194 #define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff 1195 #define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0 1196 1197 #define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff 1198 #define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0 1199 1200 #define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff 1201 #define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0 1202 1203 #define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff 1204 #define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0 1205 1206 #define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff 1207 #define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0 1208 1209 #define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff 1210 #define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0 1211 1212 #define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff 1213 #define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0 1214 1215 #define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff 1216 #define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0 1217 1218 #define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff 1219 #define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0 1220 1221 #define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26) 1222 #define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26 1223 #define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24) 1224 #define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24 1225 #define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22) 1226 #define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22 1227 #define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20) 1228 #define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20 1229 #define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18) 1230 #define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18 1231 #define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16) 1232 #define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16 1233 #define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14) 1234 #define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14 1235 #define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12) 1236 #define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12 1237 #define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10) 1238 #define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10 1239 #define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8) 1240 #define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8 1241 #define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6) 1242 #define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6 1243 #define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4) 1244 #define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4 1245 #define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2) 1246 #define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2 1247 #define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0) 1248 #define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0 1249 1250 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16) 1251 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16 1252 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16) 1253 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16) 1254 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16) 1255 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) 1256 #define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12) 1257 #define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12 1258 #define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10) 1259 #define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10 1260 #define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8) 1261 #define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8 1262 #define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6) 1263 #define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6 1264 #define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4) 1265 #define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4 1266 #define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2) 1267 #define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2 1268 #define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0) 1269 #define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0 1270 1271 #endif /* __MX28_REGS_PINCTRL_H__ */ 1272