1 /*
2  * Freescale i.MX28 PINCTRL Register Definitions
3  *
4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * Based on code from LTIB:
8  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  */
25 
26 #ifndef __MX28_REGS_PINCTRL_H__
27 #define __MX28_REGS_PINCTRL_H__
28 
29 #include <asm/imx-common/regs-common.h>
30 
31 #ifndef	__ASSEMBLY__
32 struct mxs_pinctrl_regs {
33 	mxs_reg_32(hw_pinctrl_ctrl)		/* 0x0 */
34 
35 	uint32_t	reserved1[60];
36 
37 	mxs_reg_32(hw_pinctrl_muxsel0)		/* 0x100 */
38 	mxs_reg_32(hw_pinctrl_muxsel1)		/* 0x110 */
39 	mxs_reg_32(hw_pinctrl_muxsel2)		/* 0x120 */
40 	mxs_reg_32(hw_pinctrl_muxsel3)		/* 0x130 */
41 	mxs_reg_32(hw_pinctrl_muxsel4)		/* 0x140 */
42 	mxs_reg_32(hw_pinctrl_muxsel5)		/* 0x150 */
43 	mxs_reg_32(hw_pinctrl_muxsel6)		/* 0x160 */
44 	mxs_reg_32(hw_pinctrl_muxsel7)		/* 0x170 */
45 	mxs_reg_32(hw_pinctrl_muxsel8)		/* 0x180 */
46 	mxs_reg_32(hw_pinctrl_muxsel9)		/* 0x190 */
47 	mxs_reg_32(hw_pinctrl_muxsel10)	/* 0x1a0 */
48 	mxs_reg_32(hw_pinctrl_muxsel11)	/* 0x1b0 */
49 	mxs_reg_32(hw_pinctrl_muxsel12)	/* 0x1c0 */
50 	mxs_reg_32(hw_pinctrl_muxsel13)	/* 0x1d0 */
51 
52 	uint32_t	reserved2[72];
53 
54 	mxs_reg_32(hw_pinctrl_drive0)		/* 0x300 */
55 	mxs_reg_32(hw_pinctrl_drive1)		/* 0x310 */
56 	mxs_reg_32(hw_pinctrl_drive2)		/* 0x320 */
57 	mxs_reg_32(hw_pinctrl_drive3)		/* 0x330 */
58 	mxs_reg_32(hw_pinctrl_drive4)		/* 0x340 */
59 	mxs_reg_32(hw_pinctrl_drive5)		/* 0x350 */
60 	mxs_reg_32(hw_pinctrl_drive6)		/* 0x360 */
61 	mxs_reg_32(hw_pinctrl_drive7)		/* 0x370 */
62 	mxs_reg_32(hw_pinctrl_drive8)		/* 0x380 */
63 	mxs_reg_32(hw_pinctrl_drive9)		/* 0x390 */
64 	mxs_reg_32(hw_pinctrl_drive10)		/* 0x3a0 */
65 	mxs_reg_32(hw_pinctrl_drive11)		/* 0x3b0 */
66 	mxs_reg_32(hw_pinctrl_drive12)		/* 0x3c0 */
67 	mxs_reg_32(hw_pinctrl_drive13)		/* 0x3d0 */
68 	mxs_reg_32(hw_pinctrl_drive14)		/* 0x3e0 */
69 	mxs_reg_32(hw_pinctrl_drive15)		/* 0x3f0 */
70 	mxs_reg_32(hw_pinctrl_drive16)		/* 0x400 */
71 	mxs_reg_32(hw_pinctrl_drive17)		/* 0x410 */
72 	mxs_reg_32(hw_pinctrl_drive18)		/* 0x420 */
73 	mxs_reg_32(hw_pinctrl_drive19)		/* 0x430 */
74 
75 	uint32_t	reserved3[112];
76 
77 	mxs_reg_32(hw_pinctrl_pull0)		/* 0x600 */
78 	mxs_reg_32(hw_pinctrl_pull1)		/* 0x610 */
79 	mxs_reg_32(hw_pinctrl_pull2)		/* 0x620 */
80 	mxs_reg_32(hw_pinctrl_pull3)		/* 0x630 */
81 	mxs_reg_32(hw_pinctrl_pull4)		/* 0x640 */
82 	mxs_reg_32(hw_pinctrl_pull5)		/* 0x650 */
83 	mxs_reg_32(hw_pinctrl_pull6)		/* 0x660 */
84 
85 	uint32_t	reserved4[36];
86 
87 	mxs_reg_32(hw_pinctrl_dout0)		/* 0x700 */
88 	mxs_reg_32(hw_pinctrl_dout1)		/* 0x710 */
89 	mxs_reg_32(hw_pinctrl_dout2)		/* 0x720 */
90 	mxs_reg_32(hw_pinctrl_dout3)		/* 0x730 */
91 	mxs_reg_32(hw_pinctrl_dout4)		/* 0x740 */
92 
93 	uint32_t	reserved5[108];
94 
95 	mxs_reg_32(hw_pinctrl_din0)		/* 0x900 */
96 	mxs_reg_32(hw_pinctrl_din1)		/* 0x910 */
97 	mxs_reg_32(hw_pinctrl_din2)		/* 0x920 */
98 	mxs_reg_32(hw_pinctrl_din3)		/* 0x930 */
99 	mxs_reg_32(hw_pinctrl_din4)		/* 0x940 */
100 
101 	uint32_t	reserved6[108];
102 
103 	mxs_reg_32(hw_pinctrl_doe0)		/* 0xb00 */
104 	mxs_reg_32(hw_pinctrl_doe1)		/* 0xb10 */
105 	mxs_reg_32(hw_pinctrl_doe2)		/* 0xb20 */
106 	mxs_reg_32(hw_pinctrl_doe3)		/* 0xb30 */
107 	mxs_reg_32(hw_pinctrl_doe4)		/* 0xb40 */
108 
109 	uint32_t	reserved7[300];
110 
111 	mxs_reg_32(hw_pinctrl_pin2irq0)	/* 0x1000 */
112 	mxs_reg_32(hw_pinctrl_pin2irq1)	/* 0x1010 */
113 	mxs_reg_32(hw_pinctrl_pin2irq2)	/* 0x1020 */
114 	mxs_reg_32(hw_pinctrl_pin2irq3)	/* 0x1030 */
115 	mxs_reg_32(hw_pinctrl_pin2irq4)	/* 0x1040 */
116 
117 	uint32_t	reserved8[44];
118 
119 	mxs_reg_32(hw_pinctrl_irqen0)		/* 0x1100 */
120 	mxs_reg_32(hw_pinctrl_irqen1)		/* 0x1110 */
121 	mxs_reg_32(hw_pinctrl_irqen2)		/* 0x1120 */
122 	mxs_reg_32(hw_pinctrl_irqen3)		/* 0x1130 */
123 	mxs_reg_32(hw_pinctrl_irqen4)		/* 0x1140 */
124 
125 	uint32_t	reserved9[44];
126 
127 	mxs_reg_32(hw_pinctrl_irqlevel0)	/* 0x1200 */
128 	mxs_reg_32(hw_pinctrl_irqlevel1)	/* 0x1210 */
129 	mxs_reg_32(hw_pinctrl_irqlevel2)	/* 0x1220 */
130 	mxs_reg_32(hw_pinctrl_irqlevel3)	/* 0x1230 */
131 	mxs_reg_32(hw_pinctrl_irqlevel4)	/* 0x1240 */
132 
133 	uint32_t	reserved10[44];
134 
135 	mxs_reg_32(hw_pinctrl_irqpol0)		/* 0x1300 */
136 	mxs_reg_32(hw_pinctrl_irqpol1)		/* 0x1310 */
137 	mxs_reg_32(hw_pinctrl_irqpol2)		/* 0x1320 */
138 	mxs_reg_32(hw_pinctrl_irqpol3)		/* 0x1330 */
139 	mxs_reg_32(hw_pinctrl_irqpol4)		/* 0x1340 */
140 
141 	uint32_t	reserved11[44];
142 
143 	mxs_reg_32(hw_pinctrl_irqstat0)	/* 0x1400 */
144 	mxs_reg_32(hw_pinctrl_irqstat1)	/* 0x1410 */
145 	mxs_reg_32(hw_pinctrl_irqstat2)	/* 0x1420 */
146 	mxs_reg_32(hw_pinctrl_irqstat3)	/* 0x1430 */
147 	mxs_reg_32(hw_pinctrl_irqstat4)	/* 0x1440 */
148 
149 	uint32_t	reserved12[380];
150 
151 	mxs_reg_32(hw_pinctrl_emi_odt_ctrl)	/* 0x1a40 */
152 
153 	uint32_t	reserved13[76];
154 
155 	mxs_reg_32(hw_pinctrl_emi_ds_ctrl)	/* 0x1b80 */
156 };
157 #endif
158 
159 #define	PINCTRL_CTRL_SFTRST				(1 << 31)
160 #define	PINCTRL_CTRL_CLKGATE				(1 << 30)
161 #define	PINCTRL_CTRL_PRESENT4				(1 << 24)
162 #define	PINCTRL_CTRL_PRESENT3				(1 << 23)
163 #define	PINCTRL_CTRL_PRESENT2				(1 << 22)
164 #define	PINCTRL_CTRL_PRESENT1				(1 << 21)
165 #define	PINCTRL_CTRL_PRESENT0				(1 << 20)
166 #define	PINCTRL_CTRL_IRQOUT4				(1 << 4)
167 #define	PINCTRL_CTRL_IRQOUT3				(1 << 3)
168 #define	PINCTRL_CTRL_IRQOUT2				(1 << 2)
169 #define	PINCTRL_CTRL_IRQOUT1				(1 << 1)
170 #define	PINCTRL_CTRL_IRQOUT0				(1 << 0)
171 
172 #define	PINCTRL_MUXSEL0_BANK0_PIN07_MASK		(0x3 << 14)
173 #define	PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET		14
174 #define	PINCTRL_MUXSEL0_BANK0_PIN06_MASK		(0x3 << 12)
175 #define	PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET		12
176 #define	PINCTRL_MUXSEL0_BANK0_PIN05_MASK		(0x3 << 10)
177 #define	PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET		10
178 #define	PINCTRL_MUXSEL0_BANK0_PIN04_MASK		(0x3 << 8)
179 #define	PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET		8
180 #define	PINCTRL_MUXSEL0_BANK0_PIN03_MASK		(0x3 << 6)
181 #define	PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET		6
182 #define	PINCTRL_MUXSEL0_BANK0_PIN02_MASK		(0x3 << 4)
183 #define	PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET		4
184 #define	PINCTRL_MUXSEL0_BANK0_PIN01_MASK		(0x3 << 2)
185 #define	PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET		2
186 #define	PINCTRL_MUXSEL0_BANK0_PIN00_MASK		(0x3 << 0)
187 #define	PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET		0
188 
189 #define	PINCTRL_MUXSEL1_BANK0_PIN28_MASK		(0x3 << 24)
190 #define	PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET		24
191 #define	PINCTRL_MUXSEL1_BANK0_PIN27_MASK		(0x3 << 22)
192 #define	PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET		22
193 #define	PINCTRL_MUXSEL1_BANK0_PIN26_MASK		(0x3 << 20)
194 #define	PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET		20
195 #define	PINCTRL_MUXSEL1_BANK0_PIN25_MASK		(0x3 << 18)
196 #define	PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET		18
197 #define	PINCTRL_MUXSEL1_BANK0_PIN24_MASK		(0x3 << 16)
198 #define	PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET		16
199 #define	PINCTRL_MUXSEL1_BANK0_PIN23_MASK		(0x3 << 14)
200 #define	PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET		14
201 #define	PINCTRL_MUXSEL1_BANK0_PIN22_MASK		(0x3 << 12)
202 #define	PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET		12
203 #define	PINCTRL_MUXSEL1_BANK0_PIN21_MASK		(0x3 << 10)
204 #define	PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET		10
205 #define	PINCTRL_MUXSEL1_BANK0_PIN20_MASK		(0x3 << 8)
206 #define	PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET		8
207 #define	PINCTRL_MUXSEL1_BANK0_PIN19_MASK		(0x3 << 6)
208 #define	PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET		6
209 #define	PINCTRL_MUXSEL1_BANK0_PIN18_MASK		(0x3 << 4)
210 #define	PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET		4
211 #define	PINCTRL_MUXSEL1_BANK0_PIN17_MASK		(0x3 << 2)
212 #define	PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET		2
213 #define	PINCTRL_MUXSEL1_BANK0_PIN16_MASK		(0x3 << 0)
214 #define	PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET		0
215 
216 #define	PINCTRL_MUXSEL2_BANK1_PIN15_MASK		(0x3 << 30)
217 #define	PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET		30
218 #define	PINCTRL_MUXSEL2_BANK1_PIN14_MASK		(0x3 << 28)
219 #define	PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET		28
220 #define	PINCTRL_MUXSEL2_BANK1_PIN13_MASK		(0x3 << 26)
221 #define	PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET		26
222 #define	PINCTRL_MUXSEL2_BANK1_PIN12_MASK		(0x3 << 24)
223 #define	PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET		24
224 #define	PINCTRL_MUXSEL2_BANK1_PIN11_MASK		(0x3 << 22)
225 #define	PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET		22
226 #define	PINCTRL_MUXSEL2_BANK1_PIN10_MASK		(0x3 << 20)
227 #define	PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET		20
228 #define	PINCTRL_MUXSEL2_BANK1_PIN09_MASK		(0x3 << 18)
229 #define	PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET		18
230 #define	PINCTRL_MUXSEL2_BANK1_PIN08_MASK		(0x3 << 16)
231 #define	PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET		16
232 #define	PINCTRL_MUXSEL2_BANK1_PIN07_MASK		(0x3 << 14)
233 #define	PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET		14
234 #define	PINCTRL_MUXSEL2_BANK1_PIN06_MASK		(0x3 << 12)
235 #define	PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET		12
236 #define	PINCTRL_MUXSEL2_BANK1_PIN05_MASK		(0x3 << 10)
237 #define	PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET		10
238 #define	PINCTRL_MUXSEL2_BANK1_PIN04_MASK		(0x3 << 8)
239 #define	PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET		8
240 #define	PINCTRL_MUXSEL2_BANK1_PIN03_MASK		(0x3 << 6)
241 #define	PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET		6
242 #define	PINCTRL_MUXSEL2_BANK1_PIN02_MASK		(0x3 << 4)
243 #define	PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET		4
244 #define	PINCTRL_MUXSEL2_BANK1_PIN01_MASK		(0x3 << 2)
245 #define	PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET		2
246 #define	PINCTRL_MUXSEL2_BANK1_PIN00_MASK		(0x3 << 0)
247 #define	PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET		0
248 
249 #define	PINCTRL_MUXSEL3_BANK1_PIN31_MASK		(0x3 << 30)
250 #define	PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET		30
251 #define	PINCTRL_MUXSEL3_BANK1_PIN30_MASK		(0x3 << 28)
252 #define	PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET		28
253 #define	PINCTRL_MUXSEL3_BANK1_PIN29_MASK		(0x3 << 26)
254 #define	PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET		26
255 #define	PINCTRL_MUXSEL3_BANK1_PIN28_MASK		(0x3 << 24)
256 #define	PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET		24
257 #define	PINCTRL_MUXSEL3_BANK1_PIN27_MASK		(0x3 << 22)
258 #define	PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET		22
259 #define	PINCTRL_MUXSEL3_BANK1_PIN26_MASK		(0x3 << 20)
260 #define	PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET		20
261 #define	PINCTRL_MUXSEL3_BANK1_PIN25_MASK		(0x3 << 18)
262 #define	PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET		18
263 #define	PINCTRL_MUXSEL3_BANK1_PIN24_MASK		(0x3 << 16)
264 #define	PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET		16
265 #define	PINCTRL_MUXSEL3_BANK1_PIN23_MASK		(0x3 << 14)
266 #define	PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET		14
267 #define	PINCTRL_MUXSEL3_BANK1_PIN22_MASK		(0x3 << 12)
268 #define	PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET		12
269 #define	PINCTRL_MUXSEL3_BANK1_PIN21_MASK		(0x3 << 10)
270 #define	PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET		10
271 #define	PINCTRL_MUXSEL3_BANK1_PIN20_MASK		(0x3 << 8)
272 #define	PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET		8
273 #define	PINCTRL_MUXSEL3_BANK1_PIN19_MASK		(0x3 << 6)
274 #define	PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET		6
275 #define	PINCTRL_MUXSEL3_BANK1_PIN18_MASK		(0x3 << 4)
276 #define	PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET		4
277 #define	PINCTRL_MUXSEL3_BANK1_PIN17_MASK		(0x3 << 2)
278 #define	PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET		2
279 #define	PINCTRL_MUXSEL3_BANK1_PIN16_MASK		(0x3 << 0)
280 #define	PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET		0
281 
282 #define	PINCTRL_MUXSEL4_BANK2_PIN15_MASK		(0x3 << 30)
283 #define	PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET		30
284 #define	PINCTRL_MUXSEL4_BANK2_PIN14_MASK		(0x3 << 28)
285 #define	PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET		28
286 #define	PINCTRL_MUXSEL4_BANK2_PIN13_MASK		(0x3 << 26)
287 #define	PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET		26
288 #define	PINCTRL_MUXSEL4_BANK2_PIN12_MASK		(0x3 << 24)
289 #define	PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET		24
290 #define	PINCTRL_MUXSEL4_BANK2_PIN10_MASK		(0x3 << 20)
291 #define	PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET		20
292 #define	PINCTRL_MUXSEL4_BANK2_PIN09_MASK		(0x3 << 18)
293 #define	PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET		18
294 #define	PINCTRL_MUXSEL4_BANK2_PIN08_MASK		(0x3 << 16)
295 #define	PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET		16
296 #define	PINCTRL_MUXSEL4_BANK2_PIN07_MASK		(0x3 << 14)
297 #define	PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET		14
298 #define	PINCTRL_MUXSEL4_BANK2_PIN06_MASK		(0x3 << 12)
299 #define	PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET		12
300 #define	PINCTRL_MUXSEL4_BANK2_PIN05_MASK		(0x3 << 10)
301 #define	PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET		10
302 #define	PINCTRL_MUXSEL4_BANK2_PIN04_MASK		(0x3 << 8)
303 #define	PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET		8
304 #define	PINCTRL_MUXSEL4_BANK2_PIN03_MASK		(0x3 << 6)
305 #define	PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET		6
306 #define	PINCTRL_MUXSEL4_BANK2_PIN02_MASK		(0x3 << 4)
307 #define	PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET		4
308 #define	PINCTRL_MUXSEL4_BANK2_PIN01_MASK		(0x3 << 2)
309 #define	PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET		2
310 #define	PINCTRL_MUXSEL4_BANK2_PIN00_MASK		(0x3 << 0)
311 #define	PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET		0
312 
313 #define	PINCTRL_MUXSEL5_BANK2_PIN27_MASK		(0x3 << 22)
314 #define	PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET		22
315 #define	PINCTRL_MUXSEL5_BANK2_PIN26_MASK		(0x3 << 20)
316 #define	PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET		20
317 #define	PINCTRL_MUXSEL5_BANK2_PIN25_MASK		(0x3 << 18)
318 #define	PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET		18
319 #define	PINCTRL_MUXSEL5_BANK2_PIN24_MASK		(0x3 << 16)
320 #define	PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET		16
321 #define	PINCTRL_MUXSEL5_BANK2_PIN21_MASK		(0x3 << 10)
322 #define	PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET		10
323 #define	PINCTRL_MUXSEL5_BANK2_PIN20_MASK		(0x3 << 8)
324 #define	PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET		8
325 #define	PINCTRL_MUXSEL5_BANK2_PIN19_MASK		(0x3 << 6)
326 #define	PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET		6
327 #define	PINCTRL_MUXSEL5_BANK2_PIN18_MASK		(0x3 << 4)
328 #define	PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET		4
329 #define	PINCTRL_MUXSEL5_BANK2_PIN17_MASK		(0x3 << 2)
330 #define	PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET		2
331 #define	PINCTRL_MUXSEL5_BANK2_PIN16_MASK		(0x3 << 0)
332 #define	PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET		0
333 
334 #define	PINCTRL_MUXSEL6_BANK3_PIN15_MASK		(0x3 << 30)
335 #define	PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET		30
336 #define	PINCTRL_MUXSEL6_BANK3_PIN14_MASK		(0x3 << 28)
337 #define	PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET		28
338 #define	PINCTRL_MUXSEL6_BANK3_PIN13_MASK		(0x3 << 26)
339 #define	PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET		26
340 #define	PINCTRL_MUXSEL6_BANK3_PIN12_MASK		(0x3 << 24)
341 #define	PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET		24
342 #define	PINCTRL_MUXSEL6_BANK3_PIN11_MASK		(0x3 << 22)
343 #define	PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET		22
344 #define	PINCTRL_MUXSEL6_BANK3_PIN10_MASK		(0x3 << 20)
345 #define	PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET		20
346 #define	PINCTRL_MUXSEL6_BANK3_PIN09_MASK		(0x3 << 18)
347 #define	PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET		18
348 #define	PINCTRL_MUXSEL6_BANK3_PIN08_MASK		(0x3 << 16)
349 #define	PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET		16
350 #define	PINCTRL_MUXSEL6_BANK3_PIN07_MASK		(0x3 << 14)
351 #define	PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET		14
352 #define	PINCTRL_MUXSEL6_BANK3_PIN06_MASK		(0x3 << 12)
353 #define	PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET		12
354 #define	PINCTRL_MUXSEL6_BANK3_PIN05_MASK		(0x3 << 10)
355 #define	PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET		10
356 #define	PINCTRL_MUXSEL6_BANK3_PIN04_MASK		(0x3 << 8)
357 #define	PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET		8
358 #define	PINCTRL_MUXSEL6_BANK3_PIN03_MASK		(0x3 << 6)
359 #define	PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET		6
360 #define	PINCTRL_MUXSEL6_BANK3_PIN02_MASK		(0x3 << 4)
361 #define	PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET		4
362 #define	PINCTRL_MUXSEL6_BANK3_PIN01_MASK		(0x3 << 2)
363 #define	PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET		2
364 #define	PINCTRL_MUXSEL6_BANK3_PIN00_MASK		(0x3 << 0)
365 #define	PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET		0
366 
367 #define	PINCTRL_MUXSEL7_BANK3_PIN30_MASK		(0x3 << 28)
368 #define	PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET		28
369 #define	PINCTRL_MUXSEL7_BANK3_PIN29_MASK		(0x3 << 26)
370 #define	PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET		26
371 #define	PINCTRL_MUXSEL7_BANK3_PIN28_MASK		(0x3 << 24)
372 #define	PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET		24
373 #define	PINCTRL_MUXSEL7_BANK3_PIN27_MASK		(0x3 << 22)
374 #define	PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET		22
375 #define	PINCTRL_MUXSEL7_BANK3_PIN26_MASK		(0x3 << 20)
376 #define	PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET		20
377 #define	PINCTRL_MUXSEL7_BANK3_PIN25_MASK		(0x3 << 18)
378 #define	PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET		18
379 #define	PINCTRL_MUXSEL7_BANK3_PIN24_MASK		(0x3 << 16)
380 #define	PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET		16
381 #define	PINCTRL_MUXSEL7_BANK3_PIN23_MASK		(0x3 << 14)
382 #define	PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET		14
383 #define	PINCTRL_MUXSEL7_BANK3_PIN22_MASK		(0x3 << 12)
384 #define	PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET		12
385 #define	PINCTRL_MUXSEL7_BANK3_PIN21_MASK		(0x3 << 10)
386 #define	PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET		10
387 #define	PINCTRL_MUXSEL7_BANK3_PIN20_MASK		(0x3 << 8)
388 #define	PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET		8
389 #define	PINCTRL_MUXSEL7_BANK3_PIN18_MASK		(0x3 << 4)
390 #define	PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET		4
391 #define	PINCTRL_MUXSEL7_BANK3_PIN17_MASK		(0x3 << 2)
392 #define	PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET		2
393 #define	PINCTRL_MUXSEL7_BANK3_PIN16_MASK		(0x3 << 0)
394 #define	PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET		0
395 
396 #define	PINCTRL_MUXSEL8_BANK4_PIN15_MASK		(0x3 << 30)
397 #define	PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET		30
398 #define	PINCTRL_MUXSEL8_BANK4_PIN14_MASK		(0x3 << 28)
399 #define	PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET		28
400 #define	PINCTRL_MUXSEL8_BANK4_PIN13_MASK		(0x3 << 26)
401 #define	PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET		26
402 #define	PINCTRL_MUXSEL8_BANK4_PIN12_MASK		(0x3 << 24)
403 #define	PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET		24
404 #define	PINCTRL_MUXSEL8_BANK4_PIN11_MASK		(0x3 << 22)
405 #define	PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET		22
406 #define	PINCTRL_MUXSEL8_BANK4_PIN10_MASK		(0x3 << 20)
407 #define	PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET		20
408 #define	PINCTRL_MUXSEL8_BANK4_PIN09_MASK		(0x3 << 18)
409 #define	PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET		18
410 #define	PINCTRL_MUXSEL8_BANK4_PIN08_MASK		(0x3 << 16)
411 #define	PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET		16
412 #define	PINCTRL_MUXSEL8_BANK4_PIN07_MASK		(0x3 << 14)
413 #define	PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET		14
414 #define	PINCTRL_MUXSEL8_BANK4_PIN06_MASK		(0x3 << 12)
415 #define	PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET		12
416 #define	PINCTRL_MUXSEL8_BANK4_PIN05_MASK		(0x3 << 10)
417 #define	PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET		10
418 #define	PINCTRL_MUXSEL8_BANK4_PIN04_MASK		(0x3 << 8)
419 #define	PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET		8
420 #define	PINCTRL_MUXSEL8_BANK4_PIN03_MASK		(0x3 << 6)
421 #define	PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET		6
422 #define	PINCTRL_MUXSEL8_BANK4_PIN02_MASK		(0x3 << 4)
423 #define	PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET		4
424 #define	PINCTRL_MUXSEL8_BANK4_PIN01_MASK		(0x3 << 2)
425 #define	PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET		2
426 #define	PINCTRL_MUXSEL8_BANK4_PIN00_MASK		(0x3 << 0)
427 #define	PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET		0
428 
429 #define	PINCTRL_MUXSEL9_BANK4_PIN20_MASK		(0x3 << 8)
430 #define	PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET		8
431 #define	PINCTRL_MUXSEL9_BANK4_PIN16_MASK		(0x3 << 0)
432 #define	PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET		0
433 
434 #define	PINCTRL_MUXSEL10_BANK5_PIN15_MASK		(0x3 << 30)
435 #define	PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET		30
436 #define	PINCTRL_MUXSEL10_BANK5_PIN14_MASK		(0x3 << 28)
437 #define	PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET		28
438 #define	PINCTRL_MUXSEL10_BANK5_PIN13_MASK		(0x3 << 26)
439 #define	PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET		26
440 #define	PINCTRL_MUXSEL10_BANK5_PIN12_MASK		(0x3 << 24)
441 #define	PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET		24
442 #define	PINCTRL_MUXSEL10_BANK5_PIN11_MASK		(0x3 << 22)
443 #define	PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET		22
444 #define	PINCTRL_MUXSEL10_BANK5_PIN10_MASK		(0x3 << 20)
445 #define	PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET		20
446 #define	PINCTRL_MUXSEL10_BANK5_PIN09_MASK		(0x3 << 18)
447 #define	PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET		18
448 #define	PINCTRL_MUXSEL10_BANK5_PIN08_MASK		(0x3 << 16)
449 #define	PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET		16
450 #define	PINCTRL_MUXSEL10_BANK5_PIN07_MASK		(0x3 << 14)
451 #define	PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET		14
452 #define	PINCTRL_MUXSEL10_BANK5_PIN06_MASK		(0x3 << 12)
453 #define	PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET		12
454 #define	PINCTRL_MUXSEL10_BANK5_PIN05_MASK		(0x3 << 10)
455 #define	PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET		10
456 #define	PINCTRL_MUXSEL10_BANK5_PIN04_MASK		(0x3 << 8)
457 #define	PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET		8
458 #define	PINCTRL_MUXSEL10_BANK5_PIN03_MASK		(0x3 << 6)
459 #define	PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET		6
460 #define	PINCTRL_MUXSEL10_BANK5_PIN02_MASK		(0x3 << 4)
461 #define	PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET		4
462 #define	PINCTRL_MUXSEL10_BANK5_PIN01_MASK		(0x3 << 2)
463 #define	PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET		2
464 #define	PINCTRL_MUXSEL10_BANK5_PIN00_MASK		(0x3 << 0)
465 #define	PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET		0
466 
467 #define	PINCTRL_MUXSEL11_BANK5_PIN26_MASK		(0x3 << 20)
468 #define	PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET		20
469 #define	PINCTRL_MUXSEL11_BANK5_PIN23_MASK		(0x3 << 14)
470 #define	PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET		14
471 #define	PINCTRL_MUXSEL11_BANK5_PIN22_MASK		(0x3 << 12)
472 #define	PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET		12
473 #define	PINCTRL_MUXSEL11_BANK5_PIN21_MASK		(0x3 << 10)
474 #define	PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET		10
475 #define	PINCTRL_MUXSEL11_BANK5_PIN20_MASK		(0x3 << 8)
476 #define	PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET		8
477 #define	PINCTRL_MUXSEL11_BANK5_PIN19_MASK		(0x3 << 6)
478 #define	PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET		6
479 #define	PINCTRL_MUXSEL11_BANK5_PIN18_MASK		(0x3 << 4)
480 #define	PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET		4
481 #define	PINCTRL_MUXSEL11_BANK5_PIN17_MASK		(0x3 << 2)
482 #define	PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET		2
483 #define	PINCTRL_MUXSEL11_BANK5_PIN16_MASK		(0x3 << 0)
484 #define	PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET		0
485 
486 #define	PINCTRL_MUXSEL12_BANK6_PIN14_MASK		(0x3 << 28)
487 #define	PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET		28
488 #define	PINCTRL_MUXSEL12_BANK6_PIN13_MASK		(0x3 << 26)
489 #define	PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET		26
490 #define	PINCTRL_MUXSEL12_BANK6_PIN12_MASK		(0x3 << 24)
491 #define	PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET		24
492 #define	PINCTRL_MUXSEL12_BANK6_PIN11_MASK		(0x3 << 22)
493 #define	PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET		22
494 #define	PINCTRL_MUXSEL12_BANK6_PIN10_MASK		(0x3 << 20)
495 #define	PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET		20
496 #define	PINCTRL_MUXSEL12_BANK6_PIN09_MASK		(0x3 << 18)
497 #define	PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET		18
498 #define	PINCTRL_MUXSEL12_BANK6_PIN08_MASK		(0x3 << 16)
499 #define	PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET		16
500 #define	PINCTRL_MUXSEL12_BANK6_PIN07_MASK		(0x3 << 14)
501 #define	PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET		14
502 #define	PINCTRL_MUXSEL12_BANK6_PIN06_MASK		(0x3 << 12)
503 #define	PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET		12
504 #define	PINCTRL_MUXSEL12_BANK6_PIN05_MASK		(0x3 << 10)
505 #define	PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET		10
506 #define	PINCTRL_MUXSEL12_BANK6_PIN04_MASK		(0x3 << 8)
507 #define	PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET		8
508 #define	PINCTRL_MUXSEL12_BANK6_PIN03_MASK		(0x3 << 6)
509 #define	PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET		6
510 #define	PINCTRL_MUXSEL12_BANK6_PIN02_MASK		(0x3 << 4)
511 #define	PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET		4
512 #define	PINCTRL_MUXSEL12_BANK6_PIN01_MASK		(0x3 << 2)
513 #define	PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET		2
514 #define	PINCTRL_MUXSEL12_BANK6_PIN00_MASK		(0x3 << 0)
515 #define	PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET		0
516 
517 #define	PINCTRL_MUXSEL13_BANK6_PIN24_MASK		(0x3 << 16)
518 #define	PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET		16
519 #define	PINCTRL_MUXSEL13_BANK6_PIN23_MASK		(0x3 << 14)
520 #define	PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET		14
521 #define	PINCTRL_MUXSEL13_BANK6_PIN22_MASK		(0x3 << 12)
522 #define	PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET		12
523 #define	PINCTRL_MUXSEL13_BANK6_PIN21_MASK		(0x3 << 10)
524 #define	PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET		10
525 #define	PINCTRL_MUXSEL13_BANK6_PIN20_MASK		(0x3 << 8)
526 #define	PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET		8
527 #define	PINCTRL_MUXSEL13_BANK6_PIN19_MASK		(0x3 << 6)
528 #define	PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET		6
529 #define	PINCTRL_MUXSEL13_BANK6_PIN18_MASK		(0x3 << 4)
530 #define	PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET		4
531 #define	PINCTRL_MUXSEL13_BANK6_PIN17_MASK		(0x3 << 2)
532 #define	PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET		2
533 #define	PINCTRL_MUXSEL13_BANK6_PIN16_MASK		(0x3 << 0)
534 #define	PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET		0
535 
536 #define	PINCTRL_DRIVE0_BANK0_PIN07_V			(1 << 30)
537 #define	PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK		(0x3 << 28)
538 #define	PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET		28
539 #define	PINCTRL_DRIVE0_BANK0_PIN06_V			(1 << 26)
540 #define	PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK		(0x3 << 24)
541 #define	PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET		24
542 #define	PINCTRL_DRIVE0_BANK0_PIN05_V			(1 << 22)
543 #define	PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK		(0x3 << 20)
544 #define	PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET		20
545 #define	PINCTRL_DRIVE0_BANK0_PIN04_V			(1 << 18)
546 #define	PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK		(0x3 << 16)
547 #define	PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET		16
548 #define	PINCTRL_DRIVE0_BANK0_PIN03_V			(1 << 14)
549 #define	PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK		(0x3 << 12)
550 #define	PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET		12
551 #define	PINCTRL_DRIVE0_BANK0_PIN02_V			(1 << 10)
552 #define	PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK		(0x3 << 8)
553 #define	PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET		8
554 #define	PINCTRL_DRIVE0_BANK0_PIN01_V			(1 << 6)
555 #define	PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK		(0x3 << 4)
556 #define	PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET		4
557 #define	PINCTRL_DRIVE0_BANK0_PIN00_V			(1 << 2)
558 #define	PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK		(0x3 << 0)
559 #define	PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET		0
560 
561 #define	PINCTRL_DRIVE2_BANK0_PIN23_V			(1 << 30)
562 #define	PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK		(0x3 << 28)
563 #define	PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET		28
564 #define	PINCTRL_DRIVE2_BANK0_PIN22_V			(1 << 26)
565 #define	PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK		(0x3 << 24)
566 #define	PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET		24
567 #define	PINCTRL_DRIVE2_BANK0_PIN21_V			(1 << 22)
568 #define	PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK		(0x3 << 20)
569 #define	PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET		20
570 #define	PINCTRL_DRIVE2_BANK0_PIN20_V			(1 << 18)
571 #define	PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK		(0x3 << 16)
572 #define	PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET		16
573 #define	PINCTRL_DRIVE2_BANK0_PIN19_V			(1 << 14)
574 #define	PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK		(0x3 << 12)
575 #define	PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET		12
576 #define	PINCTRL_DRIVE2_BANK0_PIN18_V			(1 << 10)
577 #define	PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK		(0x3 << 8)
578 #define	PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET		8
579 #define	PINCTRL_DRIVE2_BANK0_PIN17_V			(1 << 6)
580 #define	PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK		(0x3 << 4)
581 #define	PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET		4
582 #define	PINCTRL_DRIVE2_BANK0_PIN16_V			(1 << 2)
583 #define	PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK		(0x3 << 0)
584 #define	PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET		0
585 
586 #define	PINCTRL_DRIVE3_BANK0_PIN28_V			(1 << 18)
587 #define	PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK		(0x3 << 16)
588 #define	PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET		16
589 #define	PINCTRL_DRIVE3_BANK0_PIN27_V			(1 << 14)
590 #define	PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK		(0x3 << 12)
591 #define	PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET		12
592 #define	PINCTRL_DRIVE3_BANK0_PIN26_V			(1 << 10)
593 #define	PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK		(0x3 << 8)
594 #define	PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET		8
595 #define	PINCTRL_DRIVE3_BANK0_PIN25_V			(1 << 6)
596 #define	PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK		(0x3 << 4)
597 #define	PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET		4
598 #define	PINCTRL_DRIVE3_BANK0_PIN24_V			(1 << 2)
599 #define	PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK		(0x3 << 0)
600 #define	PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET		0
601 
602 #define	PINCTRL_DRIVE4_BANK1_PIN07_V			(1 << 30)
603 #define	PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK		(0x3 << 28)
604 #define	PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET		28
605 #define	PINCTRL_DRIVE4_BANK1_PIN06_V			(1 << 26)
606 #define	PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK		(0x3 << 24)
607 #define	PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET		24
608 #define	PINCTRL_DRIVE4_BANK1_PIN05_V			(1 << 22)
609 #define	PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK		(0x3 << 20)
610 #define	PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET		20
611 #define	PINCTRL_DRIVE4_BANK1_PIN04_V			(1 << 18)
612 #define	PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK		(0x3 << 16)
613 #define	PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET		16
614 #define	PINCTRL_DRIVE4_BANK1_PIN03_V			(1 << 14)
615 #define	PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK		(0x3 << 12)
616 #define	PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET		12
617 #define	PINCTRL_DRIVE4_BANK1_PIN02_V			(1 << 10)
618 #define	PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK		(0x3 << 8)
619 #define	PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET		8
620 #define	PINCTRL_DRIVE4_BANK1_PIN01_V			(1 << 6)
621 #define	PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK		(0x3 << 4)
622 #define	PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET		4
623 #define	PINCTRL_DRIVE4_BANK1_PIN00_V			(1 << 2)
624 #define	PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK		(0x3 << 0)
625 #define	PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET		0
626 
627 #define	PINCTRL_DRIVE5_BANK1_PIN15_V			(1 << 30)
628 #define	PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK		(0x3 << 28)
629 #define	PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET		28
630 #define	PINCTRL_DRIVE5_BANK1_PIN14_V			(1 << 26)
631 #define	PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK		(0x3 << 24)
632 #define	PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET		24
633 #define	PINCTRL_DRIVE5_BANK1_PIN13_V			(1 << 22)
634 #define	PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK		(0x3 << 20)
635 #define	PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET		20
636 #define	PINCTRL_DRIVE5_BANK1_PIN12_V			(1 << 18)
637 #define	PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK		(0x3 << 16)
638 #define	PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET		16
639 #define	PINCTRL_DRIVE5_BANK1_PIN11_V			(1 << 14)
640 #define	PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK		(0x3 << 12)
641 #define	PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET		12
642 #define	PINCTRL_DRIVE5_BANK1_PIN10_V			(1 << 10)
643 #define	PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK		(0x3 << 8)
644 #define	PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET		8
645 #define	PINCTRL_DRIVE5_BANK1_PIN09_V			(1 << 6)
646 #define	PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK		(0x3 << 4)
647 #define	PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET		4
648 #define	PINCTRL_DRIVE5_BANK1_PIN08_V			(1 << 2)
649 #define	PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK		(0x3 << 0)
650 #define	PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET		0
651 
652 #define	PINCTRL_DRIVE6_BANK1_PIN23_V			(1 << 30)
653 #define	PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK		(0x3 << 28)
654 #define	PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET		28
655 #define	PINCTRL_DRIVE6_BANK1_PIN22_V			(1 << 26)
656 #define	PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK		(0x3 << 24)
657 #define	PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET		24
658 #define	PINCTRL_DRIVE6_BANK1_PIN21_V			(1 << 22)
659 #define	PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK		(0x3 << 20)
660 #define	PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET		20
661 #define	PINCTRL_DRIVE6_BANK1_PIN20_V			(1 << 18)
662 #define	PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK		(0x3 << 16)
663 #define	PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET		16
664 #define	PINCTRL_DRIVE6_BANK1_PIN19_V			(1 << 14)
665 #define	PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK		(0x3 << 12)
666 #define	PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET		12
667 #define	PINCTRL_DRIVE6_BANK1_PIN18_V			(1 << 10)
668 #define	PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK		(0x3 << 8)
669 #define	PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET		8
670 #define	PINCTRL_DRIVE6_BANK1_PIN17_V			(1 << 6)
671 #define	PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK		(0x3 << 4)
672 #define	PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET		4
673 #define	PINCTRL_DRIVE6_BANK1_PIN16_V			(1 << 2)
674 #define	PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK		(0x3 << 0)
675 #define	PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET		0
676 
677 #define	PINCTRL_DRIVE7_BANK1_PIN31_V			(1 << 30)
678 #define	PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK		(0x3 << 28)
679 #define	PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET		28
680 #define	PINCTRL_DRIVE7_BANK1_PIN30_V			(1 << 26)
681 #define	PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK		(0x3 << 24)
682 #define	PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET		24
683 #define	PINCTRL_DRIVE7_BANK1_PIN29_V			(1 << 22)
684 #define	PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK		(0x3 << 20)
685 #define	PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET		20
686 #define	PINCTRL_DRIVE7_BANK1_PIN28_V			(1 << 18)
687 #define	PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK		(0x3 << 16)
688 #define	PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET		16
689 #define	PINCTRL_DRIVE7_BANK1_PIN27_V			(1 << 14)
690 #define	PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK		(0x3 << 12)
691 #define	PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET		12
692 #define	PINCTRL_DRIVE7_BANK1_PIN26_V			(1 << 10)
693 #define	PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK		(0x3 << 8)
694 #define	PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET		8
695 #define	PINCTRL_DRIVE7_BANK1_PIN25_V			(1 << 6)
696 #define	PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK		(0x3 << 4)
697 #define	PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET		4
698 #define	PINCTRL_DRIVE7_BANK1_PIN24_V			(1 << 2)
699 #define	PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK		(0x3 << 0)
700 #define	PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET		0
701 
702 #define	PINCTRL_DRIVE8_BANK2_PIN07_V			(1 << 30)
703 #define	PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK		(0x3 << 28)
704 #define	PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET		28
705 #define	PINCTRL_DRIVE8_BANK2_PIN06_V			(1 << 26)
706 #define	PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK		(0x3 << 24)
707 #define	PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET		24
708 #define	PINCTRL_DRIVE8_BANK2_PIN05_V			(1 << 22)
709 #define	PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK		(0x3 << 20)
710 #define	PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET		20
711 #define	PINCTRL_DRIVE8_BANK2_PIN04_V			(1 << 18)
712 #define	PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK		(0x3 << 16)
713 #define	PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET		16
714 #define	PINCTRL_DRIVE8_BANK2_PIN03_V			(1 << 14)
715 #define	PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK		(0x3 << 12)
716 #define	PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET		12
717 #define	PINCTRL_DRIVE8_BANK2_PIN02_V			(1 << 10)
718 #define	PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK		(0x3 << 8)
719 #define	PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET		8
720 #define	PINCTRL_DRIVE8_BANK2_PIN01_V			(1 << 6)
721 #define	PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK		(0x3 << 4)
722 #define	PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET		4
723 #define	PINCTRL_DRIVE8_BANK2_PIN00_V			(1 << 2)
724 #define	PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK		(0x3 << 0)
725 #define	PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET		0
726 
727 #define	PINCTRL_DRIVE9_BANK2_PIN15_V			(1 << 30)
728 #define	PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK		(0x3 << 28)
729 #define	PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET		28
730 #define	PINCTRL_DRIVE9_BANK2_PIN14_V			(1 << 26)
731 #define	PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK		(0x3 << 24)
732 #define	PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET		24
733 #define	PINCTRL_DRIVE9_BANK2_PIN13_V			(1 << 22)
734 #define	PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK		(0x3 << 20)
735 #define	PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET		20
736 #define	PINCTRL_DRIVE9_BANK2_PIN12_V			(1 << 18)
737 #define	PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK		(0x3 << 16)
738 #define	PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET		16
739 #define	PINCTRL_DRIVE9_BANK2_PIN10_V			(1 << 10)
740 #define	PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK		(0x3 << 8)
741 #define	PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET		8
742 #define	PINCTRL_DRIVE9_BANK2_PIN09_V			(1 << 6)
743 #define	PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK		(0x3 << 4)
744 #define	PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET		4
745 #define	PINCTRL_DRIVE9_BANK2_PIN08_V			(1 << 2)
746 #define	PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK		(0x3 << 0)
747 #define	PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET		0
748 
749 #define	PINCTRL_DRIVE10_BANK2_PIN21_V			(1 << 22)
750 #define	PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK		(0x3 << 20)
751 #define	PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET		20
752 #define	PINCTRL_DRIVE10_BANK2_PIN20_V			(1 << 18)
753 #define	PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK		(0x3 << 16)
754 #define	PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET		16
755 #define	PINCTRL_DRIVE10_BANK2_PIN19_V			(1 << 14)
756 #define	PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK		(0x3 << 12)
757 #define	PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET		12
758 #define	PINCTRL_DRIVE10_BANK2_PIN18_V			(1 << 10)
759 #define	PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK		(0x3 << 8)
760 #define	PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET		8
761 #define	PINCTRL_DRIVE10_BANK2_PIN17_V			(1 << 6)
762 #define	PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK		(0x3 << 4)
763 #define	PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET		4
764 #define	PINCTRL_DRIVE10_BANK2_PIN16_V			(1 << 2)
765 #define	PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK		(0x3 << 0)
766 #define	PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET		0
767 
768 #define	PINCTRL_DRIVE11_BANK2_PIN27_V			(1 << 14)
769 #define	PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK		(0x3 << 12)
770 #define	PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET		12
771 #define	PINCTRL_DRIVE11_BANK2_PIN26_V			(1 << 10)
772 #define	PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK		(0x3 << 8)
773 #define	PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET		8
774 #define	PINCTRL_DRIVE11_BANK2_PIN25_V			(1 << 6)
775 #define	PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK		(0x3 << 4)
776 #define	PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET		4
777 #define	PINCTRL_DRIVE11_BANK2_PIN24_V			(1 << 2)
778 #define	PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK		(0x3 << 0)
779 #define	PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET		0
780 
781 #define	PINCTRL_DRIVE12_BANK3_PIN07_V			(1 << 30)
782 #define	PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK		(0x3 << 28)
783 #define	PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET		28
784 #define	PINCTRL_DRIVE12_BANK3_PIN06_V			(1 << 26)
785 #define	PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK		(0x3 << 24)
786 #define	PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET		24
787 #define	PINCTRL_DRIVE12_BANK3_PIN05_V			(1 << 22)
788 #define	PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK		(0x3 << 20)
789 #define	PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET		20
790 #define	PINCTRL_DRIVE12_BANK3_PIN04_V			(1 << 18)
791 #define	PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK		(0x3 << 16)
792 #define	PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET		16
793 #define	PINCTRL_DRIVE12_BANK3_PIN03_V			(1 << 14)
794 #define	PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK		(0x3 << 12)
795 #define	PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET		12
796 #define	PINCTRL_DRIVE12_BANK3_PIN02_V			(1 << 10)
797 #define	PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK		(0x3 << 8)
798 #define	PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET		8
799 #define	PINCTRL_DRIVE12_BANK3_PIN01_V			(1 << 6)
800 #define	PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK		(0x3 << 4)
801 #define	PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET		4
802 #define	PINCTRL_DRIVE12_BANK3_PIN00_V			(1 << 2)
803 #define	PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK		(0x3 << 0)
804 #define	PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET		0
805 
806 #define	PINCTRL_DRIVE13_BANK3_PIN15_V			(1 << 30)
807 #define	PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK		(0x3 << 28)
808 #define	PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET		28
809 #define	PINCTRL_DRIVE13_BANK3_PIN14_V			(1 << 26)
810 #define	PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK		(0x3 << 24)
811 #define	PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET		24
812 #define	PINCTRL_DRIVE13_BANK3_PIN13_V			(1 << 22)
813 #define	PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK		(0x3 << 20)
814 #define	PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET		20
815 #define	PINCTRL_DRIVE13_BANK3_PIN12_V			(1 << 18)
816 #define	PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK		(0x3 << 16)
817 #define	PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET		16
818 #define	PINCTRL_DRIVE13_BANK3_PIN11_V			(1 << 14)
819 #define	PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK		(0x3 << 12)
820 #define	PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET		12
821 #define	PINCTRL_DRIVE13_BANK3_PIN10_V			(1 << 10)
822 #define	PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK		(0x3 << 8)
823 #define	PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET		8
824 #define	PINCTRL_DRIVE13_BANK3_PIN09_V			(1 << 6)
825 #define	PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK		(0x3 << 4)
826 #define	PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET		4
827 #define	PINCTRL_DRIVE13_BANK3_PIN08_V			(1 << 2)
828 #define	PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK		(0x3 << 0)
829 #define	PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET		0
830 
831 #define	PINCTRL_DRIVE14_BANK3_PIN23_V			(1 << 30)
832 #define	PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK		(0x3 << 28)
833 #define	PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET		28
834 #define	PINCTRL_DRIVE14_BANK3_PIN22_V			(1 << 26)
835 #define	PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK		(0x3 << 24)
836 #define	PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET		24
837 #define	PINCTRL_DRIVE14_BANK3_PIN21_V			(1 << 22)
838 #define	PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK		(0x3 << 20)
839 #define	PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET		20
840 #define	PINCTRL_DRIVE14_BANK3_PIN20_V			(1 << 18)
841 #define	PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK		(0x3 << 16)
842 #define	PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET		16
843 #define	PINCTRL_DRIVE14_BANK3_PIN18_V			(1 << 10)
844 #define	PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK		(0x3 << 8)
845 #define	PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET		8
846 #define	PINCTRL_DRIVE14_BANK3_PIN17_V			(1 << 6)
847 #define	PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK		(0x3 << 4)
848 #define	PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET		4
849 #define	PINCTRL_DRIVE14_BANK3_PIN16_V			(1 << 2)
850 #define	PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK		(0x3 << 0)
851 #define	PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET		0
852 
853 #define	PINCTRL_DRIVE15_BANK3_PIN30_V			(1 << 26)
854 #define	PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK		(0x3 << 24)
855 #define	PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET		24
856 #define	PINCTRL_DRIVE15_BANK3_PIN29_V			(1 << 22)
857 #define	PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK		(0x3 << 20)
858 #define	PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET		20
859 #define	PINCTRL_DRIVE15_BANK3_PIN28_V			(1 << 18)
860 #define	PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK		(0x3 << 16)
861 #define	PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET		16
862 #define	PINCTRL_DRIVE15_BANK3_PIN27_V			(1 << 14)
863 #define	PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK		(0x3 << 12)
864 #define	PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET		12
865 #define	PINCTRL_DRIVE15_BANK3_PIN26_V			(1 << 10)
866 #define	PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK		(0x3 << 8)
867 #define	PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET		8
868 #define	PINCTRL_DRIVE15_BANK3_PIN25_V			(1 << 6)
869 #define	PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK		(0x3 << 4)
870 #define	PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET		4
871 #define	PINCTRL_DRIVE15_BANK3_PIN24_V			(1 << 2)
872 #define	PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK		(0x3 << 0)
873 #define	PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET		0
874 
875 #define	PINCTRL_DRIVE16_BANK4_PIN07_V			(1 << 30)
876 #define	PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK		(0x3 << 28)
877 #define	PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET		28
878 #define	PINCTRL_DRIVE16_BANK4_PIN06_V			(1 << 26)
879 #define	PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK		(0x3 << 24)
880 #define	PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET		24
881 #define	PINCTRL_DRIVE16_BANK4_PIN05_V			(1 << 22)
882 #define	PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK		(0x3 << 20)
883 #define	PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET		20
884 #define	PINCTRL_DRIVE16_BANK4_PIN04_V			(1 << 18)
885 #define	PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK		(0x3 << 16)
886 #define	PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET		16
887 #define	PINCTRL_DRIVE16_BANK4_PIN03_V			(1 << 14)
888 #define	PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK		(0x3 << 12)
889 #define	PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET		12
890 #define	PINCTRL_DRIVE16_BANK4_PIN02_V			(1 << 10)
891 #define	PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK		(0x3 << 8)
892 #define	PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET		8
893 #define	PINCTRL_DRIVE16_BANK4_PIN01_V			(1 << 6)
894 #define	PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK		(0x3 << 4)
895 #define	PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET		4
896 #define	PINCTRL_DRIVE16_BANK4_PIN00_V			(1 << 2)
897 #define	PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK		(0x3 << 0)
898 #define	PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET		0
899 
900 #define	PINCTRL_DRIVE17_BANK4_PIN15_V			(1 << 30)
901 #define	PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK		(0x3 << 28)
902 #define	PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET		28
903 #define	PINCTRL_DRIVE17_BANK4_PIN14_V			(1 << 26)
904 #define	PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK		(0x3 << 24)
905 #define	PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET		24
906 #define	PINCTRL_DRIVE17_BANK4_PIN13_V			(1 << 22)
907 #define	PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK		(0x3 << 20)
908 #define	PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET		20
909 #define	PINCTRL_DRIVE17_BANK4_PIN12_V			(1 << 18)
910 #define	PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK		(0x3 << 16)
911 #define	PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET		16
912 #define	PINCTRL_DRIVE17_BANK4_PIN11_V			(1 << 14)
913 #define	PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK		(0x3 << 12)
914 #define	PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET		12
915 #define	PINCTRL_DRIVE17_BANK4_PIN10_V			(1 << 10)
916 #define	PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK		(0x3 << 8)
917 #define	PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET		8
918 #define	PINCTRL_DRIVE17_BANK4_PIN09_V			(1 << 6)
919 #define	PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK		(0x3 << 4)
920 #define	PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET		4
921 #define	PINCTRL_DRIVE17_BANK4_PIN08_V			(1 << 2)
922 #define	PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK		(0x3 << 0)
923 #define	PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET		0
924 
925 #define	PINCTRL_DRIVE18_BANK4_PIN20_V			(1 << 18)
926 #define	PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK		(0x3 << 16)
927 #define	PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET		16
928 #define	PINCTRL_DRIVE18_BANK4_PIN16_V			(1 << 2)
929 #define	PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK		(0x3 << 0)
930 #define	PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET		0
931 
932 #define	PINCTRL_PULL0_BANK0_PIN28			(1 << 28)
933 #define	PINCTRL_PULL0_BANK0_PIN27			(1 << 27)
934 #define	PINCTRL_PULL0_BANK0_PIN26			(1 << 26)
935 #define	PINCTRL_PULL0_BANK0_PIN25			(1 << 25)
936 #define	PINCTRL_PULL0_BANK0_PIN24			(1 << 24)
937 #define	PINCTRL_PULL0_BANK0_PIN23			(1 << 23)
938 #define	PINCTRL_PULL0_BANK0_PIN22			(1 << 22)
939 #define	PINCTRL_PULL0_BANK0_PIN21			(1 << 21)
940 #define	PINCTRL_PULL0_BANK0_PIN20			(1 << 20)
941 #define	PINCTRL_PULL0_BANK0_PIN19			(1 << 19)
942 #define	PINCTRL_PULL0_BANK0_PIN18			(1 << 18)
943 #define	PINCTRL_PULL0_BANK0_PIN17			(1 << 17)
944 #define	PINCTRL_PULL0_BANK0_PIN16			(1 << 16)
945 #define	PINCTRL_PULL0_BANK0_PIN07			(1 << 7)
946 #define	PINCTRL_PULL0_BANK0_PIN06			(1 << 6)
947 #define	PINCTRL_PULL0_BANK0_PIN05			(1 << 5)
948 #define	PINCTRL_PULL0_BANK0_PIN04			(1 << 4)
949 #define	PINCTRL_PULL0_BANK0_PIN03			(1 << 3)
950 #define	PINCTRL_PULL0_BANK0_PIN02			(1 << 2)
951 #define	PINCTRL_PULL0_BANK0_PIN01			(1 << 1)
952 #define	PINCTRL_PULL0_BANK0_PIN00			(1 << 0)
953 
954 #define	PINCTRL_PULL1_BANK1_PIN31			(1 << 31)
955 #define	PINCTRL_PULL1_BANK1_PIN30			(1 << 30)
956 #define	PINCTRL_PULL1_BANK1_PIN29			(1 << 29)
957 #define	PINCTRL_PULL1_BANK1_PIN28			(1 << 28)
958 #define	PINCTRL_PULL1_BANK1_PIN27			(1 << 27)
959 #define	PINCTRL_PULL1_BANK1_PIN26			(1 << 26)
960 #define	PINCTRL_PULL1_BANK1_PIN25			(1 << 25)
961 #define	PINCTRL_PULL1_BANK1_PIN24			(1 << 24)
962 #define	PINCTRL_PULL1_BANK1_PIN23			(1 << 23)
963 #define	PINCTRL_PULL1_BANK1_PIN22			(1 << 22)
964 #define	PINCTRL_PULL1_BANK1_PIN21			(1 << 21)
965 #define	PINCTRL_PULL1_BANK1_PIN20			(1 << 20)
966 #define	PINCTRL_PULL1_BANK1_PIN19			(1 << 19)
967 #define	PINCTRL_PULL1_BANK1_PIN18			(1 << 18)
968 #define	PINCTRL_PULL1_BANK1_PIN17			(1 << 17)
969 #define	PINCTRL_PULL1_BANK1_PIN16			(1 << 16)
970 #define	PINCTRL_PULL1_BANK1_PIN15			(1 << 15)
971 #define	PINCTRL_PULL1_BANK1_PIN14			(1 << 14)
972 #define	PINCTRL_PULL1_BANK1_PIN13			(1 << 13)
973 #define	PINCTRL_PULL1_BANK1_PIN12			(1 << 12)
974 #define	PINCTRL_PULL1_BANK1_PIN11			(1 << 11)
975 #define	PINCTRL_PULL1_BANK1_PIN10			(1 << 10)
976 #define	PINCTRL_PULL1_BANK1_PIN09			(1 << 9)
977 #define	PINCTRL_PULL1_BANK1_PIN08			(1 << 8)
978 #define	PINCTRL_PULL1_BANK1_PIN07			(1 << 7)
979 #define	PINCTRL_PULL1_BANK1_PIN06			(1 << 6)
980 #define	PINCTRL_PULL1_BANK1_PIN05			(1 << 5)
981 #define	PINCTRL_PULL1_BANK1_PIN04			(1 << 4)
982 #define	PINCTRL_PULL1_BANK1_PIN03			(1 << 3)
983 #define	PINCTRL_PULL1_BANK1_PIN02			(1 << 2)
984 #define	PINCTRL_PULL1_BANK1_PIN01			(1 << 1)
985 #define	PINCTRL_PULL1_BANK1_PIN00			(1 << 0)
986 
987 #define	PINCTRL_PULL2_BANK2_PIN27			(1 << 27)
988 #define	PINCTRL_PULL2_BANK2_PIN26			(1 << 26)
989 #define	PINCTRL_PULL2_BANK2_PIN25			(1 << 25)
990 #define	PINCTRL_PULL2_BANK2_PIN24			(1 << 24)
991 #define	PINCTRL_PULL2_BANK2_PIN21			(1 << 21)
992 #define	PINCTRL_PULL2_BANK2_PIN20			(1 << 20)
993 #define	PINCTRL_PULL2_BANK2_PIN19			(1 << 19)
994 #define	PINCTRL_PULL2_BANK2_PIN18			(1 << 18)
995 #define	PINCTRL_PULL2_BANK2_PIN17			(1 << 17)
996 #define	PINCTRL_PULL2_BANK2_PIN16			(1 << 16)
997 #define	PINCTRL_PULL2_BANK2_PIN15			(1 << 15)
998 #define	PINCTRL_PULL2_BANK2_PIN14			(1 << 14)
999 #define	PINCTRL_PULL2_BANK2_PIN13			(1 << 13)
1000 #define	PINCTRL_PULL2_BANK2_PIN12			(1 << 12)
1001 #define	PINCTRL_PULL2_BANK2_PIN10			(1 << 10)
1002 #define	PINCTRL_PULL2_BANK2_PIN09			(1 << 9)
1003 #define	PINCTRL_PULL2_BANK2_PIN08			(1 << 8)
1004 #define	PINCTRL_PULL2_BANK2_PIN07			(1 << 7)
1005 #define	PINCTRL_PULL2_BANK2_PIN06			(1 << 6)
1006 #define	PINCTRL_PULL2_BANK2_PIN05			(1 << 5)
1007 #define	PINCTRL_PULL2_BANK2_PIN04			(1 << 4)
1008 #define	PINCTRL_PULL2_BANK2_PIN03			(1 << 3)
1009 #define	PINCTRL_PULL2_BANK2_PIN02			(1 << 2)
1010 #define	PINCTRL_PULL2_BANK2_PIN01			(1 << 1)
1011 #define	PINCTRL_PULL2_BANK2_PIN00			(1 << 0)
1012 
1013 #define	PINCTRL_PULL3_BANK3_PIN30			(1 << 30)
1014 #define	PINCTRL_PULL3_BANK3_PIN29			(1 << 29)
1015 #define	PINCTRL_PULL3_BANK3_PIN28			(1 << 28)
1016 #define	PINCTRL_PULL3_BANK3_PIN27			(1 << 27)
1017 #define	PINCTRL_PULL3_BANK3_PIN26			(1 << 26)
1018 #define	PINCTRL_PULL3_BANK3_PIN25			(1 << 25)
1019 #define	PINCTRL_PULL3_BANK3_PIN24			(1 << 24)
1020 #define	PINCTRL_PULL3_BANK3_PIN23			(1 << 23)
1021 #define	PINCTRL_PULL3_BANK3_PIN22			(1 << 22)
1022 #define	PINCTRL_PULL3_BANK3_PIN21			(1 << 21)
1023 #define	PINCTRL_PULL3_BANK3_PIN20			(1 << 20)
1024 #define	PINCTRL_PULL3_BANK3_PIN18			(1 << 18)
1025 #define	PINCTRL_PULL3_BANK3_PIN17			(1 << 17)
1026 #define	PINCTRL_PULL3_BANK3_PIN16			(1 << 16)
1027 #define	PINCTRL_PULL3_BANK3_PIN15			(1 << 15)
1028 #define	PINCTRL_PULL3_BANK3_PIN14			(1 << 14)
1029 #define	PINCTRL_PULL3_BANK3_PIN13			(1 << 13)
1030 #define	PINCTRL_PULL3_BANK3_PIN12			(1 << 12)
1031 #define	PINCTRL_PULL3_BANK3_PIN11			(1 << 11)
1032 #define	PINCTRL_PULL3_BANK3_PIN10			(1 << 10)
1033 #define	PINCTRL_PULL3_BANK3_PIN09			(1 << 9)
1034 #define	PINCTRL_PULL3_BANK3_PIN08			(1 << 8)
1035 #define	PINCTRL_PULL3_BANK3_PIN07			(1 << 7)
1036 #define	PINCTRL_PULL3_BANK3_PIN06			(1 << 6)
1037 #define	PINCTRL_PULL3_BANK3_PIN05			(1 << 5)
1038 #define	PINCTRL_PULL3_BANK3_PIN04			(1 << 4)
1039 #define	PINCTRL_PULL3_BANK3_PIN03			(1 << 3)
1040 #define	PINCTRL_PULL3_BANK3_PIN02			(1 << 2)
1041 #define	PINCTRL_PULL3_BANK3_PIN01			(1 << 1)
1042 #define	PINCTRL_PULL3_BANK3_PIN00			(1 << 0)
1043 
1044 #define	PINCTRL_PULL4_BANK4_PIN20			(1 << 20)
1045 #define	PINCTRL_PULL4_BANK4_PIN16			(1 << 16)
1046 #define	PINCTRL_PULL4_BANK4_PIN15			(1 << 15)
1047 #define	PINCTRL_PULL4_BANK4_PIN14			(1 << 14)
1048 #define	PINCTRL_PULL4_BANK4_PIN13			(1 << 13)
1049 #define	PINCTRL_PULL4_BANK4_PIN12			(1 << 12)
1050 #define	PINCTRL_PULL4_BANK4_PIN11			(1 << 11)
1051 #define	PINCTRL_PULL4_BANK4_PIN10			(1 << 10)
1052 #define	PINCTRL_PULL4_BANK4_PIN09			(1 << 9)
1053 #define	PINCTRL_PULL4_BANK4_PIN08			(1 << 8)
1054 #define	PINCTRL_PULL4_BANK4_PIN07			(1 << 7)
1055 #define	PINCTRL_PULL4_BANK4_PIN06			(1 << 6)
1056 #define	PINCTRL_PULL4_BANK4_PIN05			(1 << 5)
1057 #define	PINCTRL_PULL4_BANK4_PIN04			(1 << 4)
1058 #define	PINCTRL_PULL4_BANK4_PIN03			(1 << 3)
1059 #define	PINCTRL_PULL4_BANK4_PIN02			(1 << 2)
1060 #define	PINCTRL_PULL4_BANK4_PIN01			(1 << 1)
1061 #define	PINCTRL_PULL4_BANK4_PIN00			(1 << 0)
1062 
1063 #define	PINCTRL_PULL5_BANK5_PIN26			(1 << 26)
1064 #define	PINCTRL_PULL5_BANK5_PIN23			(1 << 23)
1065 #define	PINCTRL_PULL5_BANK5_PIN22			(1 << 22)
1066 #define	PINCTRL_PULL5_BANK5_PIN21			(1 << 21)
1067 #define	PINCTRL_PULL5_BANK5_PIN20			(1 << 20)
1068 #define	PINCTRL_PULL5_BANK5_PIN19			(1 << 19)
1069 #define	PINCTRL_PULL5_BANK5_PIN18			(1 << 18)
1070 #define	PINCTRL_PULL5_BANK5_PIN17			(1 << 17)
1071 #define	PINCTRL_PULL5_BANK5_PIN16			(1 << 16)
1072 #define	PINCTRL_PULL5_BANK5_PIN15			(1 << 15)
1073 #define	PINCTRL_PULL5_BANK5_PIN14			(1 << 14)
1074 #define	PINCTRL_PULL5_BANK5_PIN13			(1 << 13)
1075 #define	PINCTRL_PULL5_BANK5_PIN12			(1 << 12)
1076 #define	PINCTRL_PULL5_BANK5_PIN11			(1 << 11)
1077 #define	PINCTRL_PULL5_BANK5_PIN10			(1 << 10)
1078 #define	PINCTRL_PULL5_BANK5_PIN09			(1 << 9)
1079 #define	PINCTRL_PULL5_BANK5_PIN08			(1 << 8)
1080 #define	PINCTRL_PULL5_BANK5_PIN07			(1 << 7)
1081 #define	PINCTRL_PULL5_BANK5_PIN06			(1 << 6)
1082 #define	PINCTRL_PULL5_BANK5_PIN05			(1 << 5)
1083 #define	PINCTRL_PULL5_BANK5_PIN04			(1 << 4)
1084 #define	PINCTRL_PULL5_BANK5_PIN03			(1 << 3)
1085 #define	PINCTRL_PULL5_BANK5_PIN02			(1 << 2)
1086 #define	PINCTRL_PULL5_BANK5_PIN01			(1 << 1)
1087 #define	PINCTRL_PULL5_BANK5_PIN00			(1 << 0)
1088 
1089 #define	PINCTRL_PULL6_BANK6_PIN24			(1 << 24)
1090 #define	PINCTRL_PULL6_BANK6_PIN23			(1 << 23)
1091 #define	PINCTRL_PULL6_BANK6_PIN22			(1 << 22)
1092 #define	PINCTRL_PULL6_BANK6_PIN21			(1 << 21)
1093 #define	PINCTRL_PULL6_BANK6_PIN20			(1 << 20)
1094 #define	PINCTRL_PULL6_BANK6_PIN19			(1 << 19)
1095 #define	PINCTRL_PULL6_BANK6_PIN18			(1 << 18)
1096 #define	PINCTRL_PULL6_BANK6_PIN17			(1 << 17)
1097 #define	PINCTRL_PULL6_BANK6_PIN16			(1 << 16)
1098 #define	PINCTRL_PULL6_BANK6_PIN14			(1 << 14)
1099 #define	PINCTRL_PULL6_BANK6_PIN13			(1 << 13)
1100 #define	PINCTRL_PULL6_BANK6_PIN12			(1 << 12)
1101 #define	PINCTRL_PULL6_BANK6_PIN11			(1 << 11)
1102 #define	PINCTRL_PULL6_BANK6_PIN10			(1 << 10)
1103 #define	PINCTRL_PULL6_BANK6_PIN09			(1 << 9)
1104 #define	PINCTRL_PULL6_BANK6_PIN08			(1 << 8)
1105 #define	PINCTRL_PULL6_BANK6_PIN07			(1 << 7)
1106 #define	PINCTRL_PULL6_BANK6_PIN06			(1 << 6)
1107 #define	PINCTRL_PULL6_BANK6_PIN05			(1 << 5)
1108 #define	PINCTRL_PULL6_BANK6_PIN04			(1 << 4)
1109 #define	PINCTRL_PULL6_BANK6_PIN03			(1 << 3)
1110 #define	PINCTRL_PULL6_BANK6_PIN02			(1 << 2)
1111 #define	PINCTRL_PULL6_BANK6_PIN01			(1 << 1)
1112 #define	PINCTRL_PULL6_BANK6_PIN00			(1 << 0)
1113 
1114 #define	PINCTRL_DOUT0_DOUT_MASK				0x1fffffff
1115 #define	PINCTRL_DOUT0_DOUT_OFFSET			0
1116 
1117 #define	PINCTRL_DOUT1_DOUT_MASK				0xffffffff
1118 #define	PINCTRL_DOUT1_DOUT_OFFSET			0
1119 
1120 #define	PINCTRL_DOUT2_DOUT_MASK				0xfffffff
1121 #define	PINCTRL_DOUT2_DOUT_OFFSET			0
1122 
1123 #define	PINCTRL_DOUT3_DOUT_MASK				0x7fffffff
1124 #define	PINCTRL_DOUT3_DOUT_OFFSET			0
1125 
1126 #define	PINCTRL_DOUT4_DOUT_MASK				0x1fffff
1127 #define	PINCTRL_DOUT4_DOUT_OFFSET			0
1128 
1129 #define	PINCTRL_DIN0_DIN_MASK				0x1fffffff
1130 #define	PINCTRL_DIN0_DIN_OFFSET				0
1131 
1132 #define	PINCTRL_DIN1_DIN_MASK				0xffffffff
1133 #define	PINCTRL_DIN1_DIN_OFFSET				0
1134 
1135 #define	PINCTRL_DIN2_DIN_MASK				0xfffffff
1136 #define	PINCTRL_DIN2_DIN_OFFSET				0
1137 
1138 #define	PINCTRL_DIN3_DIN_MASK				0x7fffffff
1139 #define	PINCTRL_DIN3_DIN_OFFSET				0
1140 
1141 #define	PINCTRL_DIN4_DIN_MASK				0x1fffff
1142 #define	PINCTRL_DIN4_DIN_OFFSET				0
1143 
1144 #define	PINCTRL_DOE0_DOE_MASK				0x1fffffff
1145 #define	PINCTRL_DOE0_DOE_OFFSET				0
1146 
1147 #define	PINCTRL_DOE1_DOE_MASK				0xffffffff
1148 #define	PINCTRL_DOE1_DOE_OFFSET				0
1149 
1150 #define	PINCTRL_DOE2_DOE_MASK				0xfffffff
1151 #define	PINCTRL_DOE2_DOE_OFFSET				0
1152 
1153 #define	PINCTRL_DOE3_DOE_MASK				0x7fffffff
1154 #define	PINCTRL_DOE3_DOE_OFFSET				0
1155 
1156 #define	PINCTRL_DOE4_DOE_MASK				0x1fffff
1157 #define	PINCTRL_DOE4_DOE_OFFSET				0
1158 
1159 #define	PINCTRL_PIN2IRQ0_PIN2IRQ_MASK			0x1fffffff
1160 #define	PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET			0
1161 
1162 #define	PINCTRL_PIN2IRQ1_PIN2IRQ_MASK			0xffffffff
1163 #define	PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET			0
1164 
1165 #define	PINCTRL_PIN2IRQ2_PIN2IRQ_MASK			0xfffffff
1166 #define	PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET			0
1167 
1168 #define	PINCTRL_PIN2IRQ3_PIN2IRQ_MASK			0x7fffffff
1169 #define	PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET			0
1170 
1171 #define	PINCTRL_PIN2IRQ4_PIN2IRQ_MASK			0x1fffff
1172 #define	PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET			0
1173 
1174 #define	PINCTRL_IRQEN0_IRQEN_MASK			0x1fffffff
1175 #define	PINCTRL_IRQEN0_IRQEN_OFFSET			0
1176 
1177 #define	PINCTRL_IRQEN1_IRQEN_MASK			0xffffffff
1178 #define	PINCTRL_IRQEN1_IRQEN_OFFSET			0
1179 
1180 #define	PINCTRL_IRQEN2_IRQEN_MASK			0xfffffff
1181 #define	PINCTRL_IRQEN2_IRQEN_OFFSET			0
1182 
1183 #define	PINCTRL_IRQEN3_IRQEN_MASK			0x7fffffff
1184 #define	PINCTRL_IRQEN3_IRQEN_OFFSET			0
1185 
1186 #define	PINCTRL_IRQEN4_IRQEN_MASK			0x1fffff
1187 #define	PINCTRL_IRQEN4_IRQEN_OFFSET			0
1188 
1189 #define	PINCTRL_IRQLEVEL0_IRQLEVEL_MASK			0x1fffffff
1190 #define	PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET		0
1191 
1192 #define	PINCTRL_IRQLEVEL1_IRQLEVEL_MASK			0xffffffff
1193 #define	PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET		0
1194 
1195 #define	PINCTRL_IRQLEVEL2_IRQLEVEL_MASK			0xfffffff
1196 #define	PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET		0
1197 
1198 #define	PINCTRL_IRQLEVEL3_IRQLEVEL_MASK			0x7fffffff
1199 #define	PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET		0
1200 
1201 #define	PINCTRL_IRQLEVEL4_IRQLEVEL_MASK			0x1fffff
1202 #define	PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET		0
1203 
1204 #define	PINCTRL_IRQPOL0_IRQPOL_MASK			0x1fffffff
1205 #define	PINCTRL_IRQPOL0_IRQPOL_OFFSET			0
1206 
1207 #define	PINCTRL_IRQPOL1_IRQPOL_MASK			0xffffffff
1208 #define	PINCTRL_IRQPOL1_IRQPOL_OFFSET			0
1209 
1210 #define	PINCTRL_IRQPOL2_IRQPOL_MASK			0xfffffff
1211 #define	PINCTRL_IRQPOL2_IRQPOL_OFFSET			0
1212 
1213 #define	PINCTRL_IRQPOL3_IRQPOL_MASK			0x7fffffff
1214 #define	PINCTRL_IRQPOL3_IRQPOL_OFFSET			0
1215 
1216 #define	PINCTRL_IRQPOL4_IRQPOL_MASK			0x1fffff
1217 #define	PINCTRL_IRQPOL4_IRQPOL_OFFSET			0
1218 
1219 #define	PINCTRL_IRQSTAT0_IRQSTAT_MASK			0x1fffffff
1220 #define	PINCTRL_IRQSTAT0_IRQSTAT_OFFSET			0
1221 
1222 #define	PINCTRL_IRQSTAT1_IRQSTAT_MASK			0xffffffff
1223 #define	PINCTRL_IRQSTAT1_IRQSTAT_OFFSET			0
1224 
1225 #define	PINCTRL_IRQSTAT2_IRQSTAT_MASK			0xfffffff
1226 #define	PINCTRL_IRQSTAT2_IRQSTAT_OFFSET			0
1227 
1228 #define	PINCTRL_IRQSTAT3_IRQSTAT_MASK			0x7fffffff
1229 #define	PINCTRL_IRQSTAT3_IRQSTAT_OFFSET			0
1230 
1231 #define	PINCTRL_IRQSTAT4_IRQSTAT_MASK			0x1fffff
1232 #define	PINCTRL_IRQSTAT4_IRQSTAT_OFFSET			0
1233 
1234 #define	PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK		(0x3 << 26)
1235 #define	PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET	26
1236 #define	PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK		(0x3 << 24)
1237 #define	PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET	24
1238 #define	PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK		(0x3 << 22)
1239 #define	PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET	22
1240 #define	PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK		(0x3 << 20)
1241 #define	PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET	20
1242 #define	PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK		(0x3 << 18)
1243 #define	PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET	18
1244 #define	PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK		(0x3 << 16)
1245 #define	PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET	16
1246 #define	PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK		(0x3 << 14)
1247 #define	PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET	14
1248 #define	PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK		(0x3 << 12)
1249 #define	PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET	12
1250 #define	PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK		(0x3 << 10)
1251 #define	PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET	10
1252 #define	PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK		(0x3 << 8)
1253 #define	PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET	8
1254 #define	PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK		(0x3 << 6)
1255 #define	PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET	6
1256 #define	PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK		(0x3 << 4)
1257 #define	PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET	4
1258 #define	PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK		(0x3 << 2)
1259 #define	PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET	2
1260 #define	PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK		(0x3 << 0)
1261 #define	PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET	0
1262 
1263 #define	PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK		(0x3 << 16)
1264 #define	PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET		16
1265 #define	PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR		(0x0 << 16)
1266 #define	PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO		(0x1 << 16)
1267 #define	PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2		(0x2 << 16)
1268 #define	PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2		(0x3 << 16)
1269 #define	PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK		(0x3 << 12)
1270 #define	PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET		12
1271 #define	PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK		(0x3 << 10)
1272 #define	PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET		10
1273 #define	PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK		(0x3 << 8)
1274 #define	PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET		8
1275 #define	PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK		(0x3 << 6)
1276 #define	PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET		6
1277 #define	PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK		(0x3 << 4)
1278 #define	PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET		4
1279 #define	PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK		(0x3 << 2)
1280 #define	PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET		2
1281 #define	PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK		(0x3 << 0)
1282 #define	PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET		0
1283 
1284 #endif /* __MX28_REGS_PINCTRL_H__ */
1285