1 /* 2 * Freescale i.MX28 LRADC Register Definitions 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #ifndef __MX28_REGS_LRADC_H__ 27 #define __MX28_REGS_LRADC_H__ 28 29 #include <asm/arch/regs-common.h> 30 31 #ifndef __ASSEMBLY__ 32 struct mxs_lradc_regs { 33 mxs_reg_32(hw_lradc_ctrl0); 34 mxs_reg_32(hw_lradc_ctrl1); 35 mxs_reg_32(hw_lradc_ctrl2); 36 mxs_reg_32(hw_lradc_ctrl3); 37 mxs_reg_32(hw_lradc_status); 38 mxs_reg_32(hw_lradc_ch0); 39 mxs_reg_32(hw_lradc_ch1); 40 mxs_reg_32(hw_lradc_ch2); 41 mxs_reg_32(hw_lradc_ch3); 42 mxs_reg_32(hw_lradc_ch4); 43 mxs_reg_32(hw_lradc_ch5); 44 mxs_reg_32(hw_lradc_ch6); 45 mxs_reg_32(hw_lradc_ch7); 46 mxs_reg_32(hw_lradc_delay0); 47 mxs_reg_32(hw_lradc_delay1); 48 mxs_reg_32(hw_lradc_delay2); 49 mxs_reg_32(hw_lradc_delay3); 50 mxs_reg_32(hw_lradc_debug0); 51 mxs_reg_32(hw_lradc_debug1); 52 mxs_reg_32(hw_lradc_conversion); 53 mxs_reg_32(hw_lradc_ctrl4); 54 mxs_reg_32(hw_lradc_treshold0); 55 mxs_reg_32(hw_lradc_treshold1); 56 mxs_reg_32(hw_lradc_version); 57 }; 58 #endif 59 60 #define LRADC_CTRL0_SFTRST (1 << 31) 61 #define LRADC_CTRL0_CLKGATE (1 << 30) 62 #define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26) 63 #define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25) 64 #define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24) 65 #define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) 66 #define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) 67 #define LRADC_CTRL0_YNLRSW (1 << 21) 68 #define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19) 69 #define LRADC_CTRL0_YPLLSW_OFFSET 19 70 #define LRADC_CTRL0_XNURSW_MASK (0x3 << 17) 71 #define LRADC_CTRL0_XNURSW_OFFSET 17 72 #define LRADC_CTRL0_XPULSW (1 << 16) 73 #define LRADC_CTRL0_SCHEDULE_MASK 0xff 74 #define LRADC_CTRL0_SCHEDULE_OFFSET 0 75 76 #define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28) 77 #define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27) 78 #define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26) 79 #define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25) 80 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) 81 #define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23) 82 #define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22) 83 #define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21) 84 #define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20) 85 #define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19) 86 #define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18) 87 #define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17) 88 #define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16) 89 #define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12) 90 #define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11) 91 #define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10) 92 #define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9) 93 #define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) 94 #define LRADC_CTRL1_LRADC7_IRQ (1 << 7) 95 #define LRADC_CTRL1_LRADC6_IRQ (1 << 6) 96 #define LRADC_CTRL1_LRADC5_IRQ (1 << 5) 97 #define LRADC_CTRL1_LRADC4_IRQ (1 << 4) 98 #define LRADC_CTRL1_LRADC3_IRQ (1 << 3) 99 #define LRADC_CTRL1_LRADC2_IRQ (1 << 2) 100 #define LRADC_CTRL1_LRADC1_IRQ (1 << 1) 101 #define LRADC_CTRL1_LRADC0_IRQ (1 << 0) 102 103 #define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24) 104 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 105 #define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) 106 #define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13) 107 #define LRADC_CTRL2_VTHSENSE_OFFSET 13 108 #define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12) 109 #define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9) 110 #define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8) 111 #define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4) 112 #define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4 113 #define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4) 114 #define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4) 115 #define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4) 116 #define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4) 117 #define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4) 118 #define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4) 119 #define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4) 120 #define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4) 121 #define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4) 122 #define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4) 123 #define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4) 124 #define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4) 125 #define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4) 126 #define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4) 127 #define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4) 128 #define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4) 129 #define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0) 130 #define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0 131 #define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0) 132 #define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0) 133 #define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0) 134 #define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0) 135 #define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0) 136 #define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0) 137 #define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0) 138 #define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0) 139 #define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0) 140 #define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0) 141 #define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0) 142 #define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0) 143 #define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0) 144 #define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0) 145 #define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0) 146 #define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0) 147 148 #define LRADC_CTRL3_DISCARD_MASK (0x3 << 24) 149 #define LRADC_CTRL3_DISCARD_OFFSET 24 150 #define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24) 151 #define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24) 152 #define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24) 153 #define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23) 154 #define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22) 155 #define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8) 156 #define LRADC_CTRL3_CYCLE_TIME_OFFSET 8 157 #define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8) 158 #define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8) 159 #define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8) 160 #define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8) 161 #define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4) 162 #define LRADC_CTRL3_HIGH_TIME_OFFSET 4 163 #define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4) 164 #define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4) 165 #define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4) 166 #define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4) 167 #define LRADC_CTRL3_DELAY_CLOCK (1 << 1) 168 #define LRADC_CTRL3_INVERT_CLOCK (1 << 0) 169 170 #define LRADC_STATUS_BUTTON1_PRESENT (1 << 28) 171 #define LRADC_STATUS_BUTTON0_PRESENT (1 << 27) 172 #define LRADC_STATUS_TEMP1_PRESENT (1 << 26) 173 #define LRADC_STATUS_TEMP0_PRESENT (1 << 25) 174 #define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24) 175 #define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23) 176 #define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22) 177 #define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21) 178 #define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20) 179 #define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19) 180 #define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18) 181 #define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17) 182 #define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16) 183 #define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2) 184 #define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1) 185 #define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) 186 187 #define LRADC_CH_TOGGLE (1 << 31) 188 #define LRADC_CH7_TESTMODE_TOGGLE (1 << 30) 189 #define LRADC_CH_ACCUMULATE (1 << 29) 190 #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) 191 #define LRADC_CH_NUM_SAMPLES_OFFSET 24 192 #define LRADC_CH_VALUE_MASK 0x3ffff 193 #define LRADC_CH_VALUE_OFFSET 0 194 195 #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) 196 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 197 #define LRADC_DELAY_KICK (1 << 20) 198 #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) 199 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 200 #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) 201 #define LRADC_DELAY_LOOP_COUNT_OFFSET 11 202 #define LRADC_DELAY_DELAY_MASK 0x7ff 203 #define LRADC_DELAY_DELAY_OFFSET 0 204 205 #define LRADC_DEBUG0_READONLY_MASK (0xffff << 16) 206 #define LRADC_DEBUG0_READONLY_OFFSET 16 207 #define LRADC_DEBUG0_STATE_MASK (0xfff << 0) 208 #define LRADC_DEBUG0_STATE_OFFSET 0 209 210 #define LRADC_DEBUG1_REQUEST_MASK (0xff << 16) 211 #define LRADC_DEBUG1_REQUEST_OFFSET 16 212 #define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8) 213 #define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8 214 #define LRADC_DEBUG1_TESTMODE6 (1 << 2) 215 #define LRADC_DEBUG1_TESTMODE5 (1 << 1) 216 #define LRADC_DEBUG1_TESTMODE (1 << 0) 217 218 #define LRADC_CONVERSION_AUTOMATIC (1 << 20) 219 #define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16) 220 #define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16 221 #define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16) 222 #define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16) 223 #define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16) 224 #define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16) 225 #define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff 226 #define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0 227 228 #define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28) 229 #define LRADC_CTRL4_LRADC7SELECT_OFFSET 28 230 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28) 231 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28) 232 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28) 233 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28) 234 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28) 235 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28) 236 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28) 237 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28) 238 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28) 239 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28) 240 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28) 241 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28) 242 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28) 243 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28) 244 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28) 245 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28) 246 #define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24) 247 #define LRADC_CTRL4_LRADC6SELECT_OFFSET 24 248 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24) 249 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24) 250 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24) 251 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24) 252 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24) 253 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24) 254 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24) 255 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24) 256 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24) 257 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24) 258 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24) 259 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24) 260 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24) 261 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24) 262 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24) 263 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24) 264 #define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20) 265 #define LRADC_CTRL4_LRADC5SELECT_OFFSET 20 266 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20) 267 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20) 268 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20) 269 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20) 270 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20) 271 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20) 272 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20) 273 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20) 274 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20) 275 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20) 276 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20) 277 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20) 278 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20) 279 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20) 280 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20) 281 #define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20) 282 #define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16) 283 #define LRADC_CTRL4_LRADC4SELECT_OFFSET 16 284 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16) 285 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16) 286 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16) 287 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16) 288 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16) 289 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16) 290 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16) 291 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16) 292 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16) 293 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16) 294 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16) 295 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16) 296 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16) 297 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16) 298 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16) 299 #define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16) 300 #define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12) 301 #define LRADC_CTRL4_LRADC3SELECT_OFFSET 12 302 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12) 303 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12) 304 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12) 305 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12) 306 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12) 307 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12) 308 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12) 309 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12) 310 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12) 311 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12) 312 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12) 313 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12) 314 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12) 315 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12) 316 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12) 317 #define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12) 318 #define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8) 319 #define LRADC_CTRL4_LRADC2SELECT_OFFSET 8 320 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8) 321 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8) 322 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8) 323 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8) 324 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8) 325 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8) 326 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8) 327 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8) 328 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8) 329 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8) 330 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8) 331 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8) 332 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8) 333 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8) 334 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8) 335 #define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8) 336 #define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4) 337 #define LRADC_CTRL4_LRADC1SELECT_OFFSET 4 338 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4) 339 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4) 340 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4) 341 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4) 342 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4) 343 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4) 344 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4) 345 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4) 346 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4) 347 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4) 348 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4) 349 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4) 350 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4) 351 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4) 352 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4) 353 #define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4) 354 #define LRADC_CTRL4_LRADC0SELECT_MASK 0xf 355 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0) 356 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0) 357 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0) 358 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0) 359 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0) 360 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0) 361 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0) 362 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0) 363 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0) 364 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0) 365 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0) 366 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0) 367 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0) 368 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0) 369 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0) 370 #define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0) 371 372 #define LRADC_THRESHOLD_ENABLE (1 << 24) 373 #define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23) 374 #define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20) 375 #define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20 376 #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20) 377 #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20) 378 #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20) 379 #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20) 380 #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20) 381 #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20) 382 #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20) 383 #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20) 384 #define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18) 385 #define LRADC_THRESHOLD_SETTING_OFFSET 18 386 #define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18) 387 #define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18) 388 #define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18) 389 #define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18) 390 #define LRADC_THRESHOLD_VALUE_MASK 0x3ffff 391 #define LRADC_THRESHOLD_VALUE_OFFSET 0 392 393 #define LRADC_VERSION_MAJOR_MASK (0xff << 24) 394 #define LRADC_VERSION_MAJOR_OFFSET 24 395 #define LRADC_VERSION_MINOR_MASK (0xff << 16) 396 #define LRADC_VERSION_MINOR_OFFSET 16 397 #define LRADC_VERSION_STEP_MASK 0xffff 398 #define LRADC_VERSION_STEP_OFFSET 0 399 400 #endif /* __MX28_REGS_LRADC_H__ */ 401