1 /*
2  * Freescale i.MX28 DIGCTL Register Definitions
3  *
4  * Copyright (C) 2012 Robert Delien <robert@delien.nl>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
19  *
20  */
21 
22 #ifndef __MX28_REGS_DIGCTL_H__
23 #define __MX28_REGS_DIGCTL_H__
24 
25 #include <asm/arch/regs-common.h>
26 
27 #ifndef	__ASSEMBLY__
28 struct mxs_digctl_regs {
29 	mxs_reg_32(hw_digctl_ctrl)				/* 0x000 */
30 	mxs_reg_32(hw_digctl_status)				/* 0x010 */
31 	mxs_reg_32(hw_digctl_hclkcount)			/* 0x020 */
32 	mxs_reg_32(hw_digctl_ramctrl)				/* 0x030 */
33 	mxs_reg_32(hw_digctl_emi_status)			/* 0x040 */
34 	mxs_reg_32(hw_digctl_read_margin)			/* 0x050 */
35 	uint32_t	hw_digctl_writeonce;			/* 0x060 */
36 	uint32_t	reserved_writeonce[3];
37 	mxs_reg_32(hw_digctl_bist_ctl)				/* 0x070 */
38 	mxs_reg_32(hw_digctl_bist_status)			/* 0x080 */
39 	uint32_t	hw_digctl_entropy;			/* 0x090 */
40 	uint32_t	reserved_entropy[3];
41 	uint32_t	hw_digctl_entropy_latched;		/* 0x0a0 */
42 	uint32_t	reserved_entropy_latched[3];
43 
44 	uint32_t	reserved1[4];
45 
46 	mxs_reg_32(hw_digctl_microseconds)			/* 0x0c0 */
47 	uint32_t	hw_digctl_dbgrd;			/* 0x0d0 */
48 	uint32_t	reserved_hw_digctl_dbgrd[3];
49 	uint32_t	hw_digctl_dbg;				/* 0x0e0 */
50 	uint32_t	reserved_hw_digctl_dbg[3];
51 
52 	uint32_t	reserved2[4];
53 
54 	mxs_reg_32(hw_digctl_usb_loopback)			/* 0x100 */
55 	mxs_reg_32(hw_digctl_ocram_status0)			/* 0x110 */
56 	mxs_reg_32(hw_digctl_ocram_status1)			/* 0x120 */
57 	mxs_reg_32(hw_digctl_ocram_status2)			/* 0x130 */
58 	mxs_reg_32(hw_digctl_ocram_status3)			/* 0x140 */
59 	mxs_reg_32(hw_digctl_ocram_status4)			/* 0x150 */
60 	mxs_reg_32(hw_digctl_ocram_status5)			/* 0x160 */
61 	mxs_reg_32(hw_digctl_ocram_status6)			/* 0x170 */
62 	mxs_reg_32(hw_digctl_ocram_status7)			/* 0x180 */
63 	mxs_reg_32(hw_digctl_ocram_status8)			/* 0x190 */
64 	mxs_reg_32(hw_digctl_ocram_status9)			/* 0x1a0 */
65 	mxs_reg_32(hw_digctl_ocram_status10)			/* 0x1b0 */
66 	mxs_reg_32(hw_digctl_ocram_status11)			/* 0x1c0 */
67 	mxs_reg_32(hw_digctl_ocram_status12)			/* 0x1d0 */
68 	mxs_reg_32(hw_digctl_ocram_status13)			/* 0x1e0 */
69 
70 	uint32_t	reserved3[36];
71 
72 	uint32_t	hw_digctl_scratch0;			/* 0x280 */
73 	uint32_t	reserved_hw_digctl_scratch0[3];
74 	uint32_t	hw_digctl_scratch1;			/* 0x290 */
75 	uint32_t	reserved_hw_digctl_scratch1[3];
76 	uint32_t	hw_digctl_armcache;			/* 0x2a0 */
77 	uint32_t	reserved_hw_digctl_armcache[3];
78 	mxs_reg_32(hw_digctl_debug_trap)			/* 0x2b0 */
79 	uint32_t	hw_digctl_debug_trap_l0_addr_low;	/* 0x2c0 */
80 	uint32_t	reserved_hw_digctl_debug_trap_l0_addr_low[3];
81 	uint32_t	hw_digctl_debug_trap_l0_addr_high;	/* 0x2d0 */
82 	uint32_t	reserved_hw_digctl_debug_trap_l0_addr_high[3];
83 	uint32_t	hw_digctl_debug_trap_l3_addr_low;	/* 0x2e0 */
84 	uint32_t	reserved_hw_digctl_debug_trap_l3_addr_low[3];
85 	uint32_t	hw_digctl_debug_trap_l3_addr_high;	/* 0x2f0 */
86 	uint32_t	reserved_hw_digctl_debug_trap_l3_addr_high[3];
87 	uint32_t	hw_digctl_fsl;				/* 0x300 */
88 	uint32_t	reserved_hw_digctl_fsl[3];
89 	uint32_t	hw_digctl_chipid;			/* 0x310 */
90 	uint32_t	reserved_hw_digctl_chipid[3];
91 
92 	uint32_t	reserved4[4];
93 
94 	uint32_t	hw_digctl_ahb_stats_select;		/* 0x330 */
95 	uint32_t	reserved_hw_digctl_ahb_stats_select[3];
96 
97 	uint32_t	reserved5[12];
98 
99 	uint32_t	hw_digctl_l1_ahb_active_cycles;		/* 0x370 */
100 	uint32_t	reserved_hw_digctl_l1_ahb_active_cycles[3];
101 	uint32_t	hw_digctl_l1_ahb_data_stalled;		/* 0x380 */
102 	uint32_t	reserved_hw_digctl_l1_ahb_data_stalled[3];
103 	uint32_t	hw_digctl_l1_ahb_data_cycles;		/* 0x390 */
104 	uint32_t	reserved_hw_digctl_l1_ahb_data_cycles[3];
105 	uint32_t	hw_digctl_l2_ahb_active_cycles;		/* 0x3a0 */
106 	uint32_t	reserved_hw_digctl_l2_ahb_active_cycles[3];
107 	uint32_t	hw_digctl_l2_ahb_data_stalled;		/* 0x3b0 */
108 	uint32_t	reserved_hw_digctl_l2_ahb_data_stalled[3];
109 	uint32_t	hw_digctl_l2_ahb_data_cycles;		/* 0x3c0 */
110 	uint32_t	reserved_hw_digctl_l2_ahb_data_cycles[3];
111 	uint32_t	hw_digctl_l3_ahb_active_cycles;		/* 0x3d0 */
112 	uint32_t	reserved_hw_digctl_l3_ahb_active_cycles[3];
113 	uint32_t	hw_digctl_l3_ahb_data_stalled;		/* 0x3e0 */
114 	uint32_t	reserved_hw_digctl_l3_ahb_data_stalled[3];
115 	uint32_t	hw_digctl_l3_ahb_data_cycles;		/* 0x3f0 */
116 	uint32_t	reserved_hw_digctl_l3_ahb_data_cycles[3];
117 
118 	uint32_t	reserved6[64];
119 
120 	uint32_t	hw_digctl_mpte0_loc;			/* 0x500 */
121 	uint32_t	reserved_hw_digctl_mpte0_loc[3];
122 	uint32_t	hw_digctl_mpte1_loc;			/* 0x510 */
123 	uint32_t	reserved_hw_digctl_mpte1_loc[3];
124 	uint32_t	hw_digctl_mpte2_loc;			/* 0x520 */
125 	uint32_t	reserved_hw_digctl_mpte2_loc[3];
126 	uint32_t	hw_digctl_mpte3_loc;			/* 0x530 */
127 	uint32_t	reserved_hw_digctl_mpte3_loc[3];
128 	uint32_t	hw_digctl_mpte4_loc;			/* 0x540 */
129 	uint32_t	reserved_hw_digctl_mpte4_loc[3];
130 	uint32_t	hw_digctl_mpte5_loc;			/* 0x550 */
131 	uint32_t	reserved_hw_digctl_mpte5_loc[3];
132 	uint32_t	hw_digctl_mpte6_loc;			/* 0x560 */
133 	uint32_t	reserved_hw_digctl_mpte6_loc[3];
134 	uint32_t	hw_digctl_mpte7_loc;			/* 0x570 */
135 	uint32_t	reserved_hw_digctl_mpte7_loc[3];
136 	uint32_t	hw_digctl_mpte8_loc;			/* 0x580 */
137 	uint32_t	reserved_hw_digctl_mpte8_loc[3];
138 	uint32_t	hw_digctl_mpte9_loc;			/* 0x590 */
139 	uint32_t	reserved_hw_digctl_mpte9_loc[3];
140 	uint32_t	hw_digctl_mpte10_loc;			/* 0x5a0 */
141 	uint32_t	reserved_hw_digctl_mpte10_loc[3];
142 	uint32_t	hw_digctl_mpte11_loc;			/* 0x5b0 */
143 	uint32_t	reserved_hw_digctl_mpte11_loc[3];
144 	uint32_t	hw_digctl_mpte12_loc;			/* 0x5c0 */
145 	uint32_t	reserved_hw_digctl_mpte12_loc[3];
146 	uint32_t	hw_digctl_mpte13_loc;			/* 0x5d0 */
147 	uint32_t	reserved_hw_digctl_mpte13_loc[3];
148 	uint32_t	hw_digctl_mpte14_loc;			/* 0x5e0 */
149 	uint32_t	reserved_hw_digctl_mpte14_loc[3];
150 	uint32_t	hw_digctl_mpte15_loc;			/* 0x5f0 */
151 	uint32_t	reserved_hw_digctl_mpte15_loc[3];
152 };
153 #endif
154 
155 /* Product code identification */
156 #define HW_DIGCTL_CHIPID_MASK	(0xffff << 16)
157 #define HW_DIGCTL_CHIPID_MX28	(0x2800 << 16)
158 
159 #endif /* __MX28_REGS_DIGCTL_H__ */
160