1 /* 2 * Freescale i.MX28 DIGCTL Register Definitions 3 * 4 * Copyright (C) 2012 Robert Delien <robert@delien.nl> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __MX28_REGS_DIGCTL_H__ 10 #define __MX28_REGS_DIGCTL_H__ 11 12 #include <asm/mach-imx/regs-common.h> 13 14 #ifndef __ASSEMBLY__ 15 struct mxs_digctl_regs { 16 mxs_reg_32(hw_digctl_ctrl) /* 0x000 */ 17 mxs_reg_32(hw_digctl_status) /* 0x010 */ 18 mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */ 19 mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */ 20 mxs_reg_32(hw_digctl_emi_status) /* 0x040 */ 21 mxs_reg_32(hw_digctl_read_margin) /* 0x050 */ 22 uint32_t hw_digctl_writeonce; /* 0x060 */ 23 uint32_t reserved_writeonce[3]; 24 mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */ 25 mxs_reg_32(hw_digctl_bist_status) /* 0x080 */ 26 uint32_t hw_digctl_entropy; /* 0x090 */ 27 uint32_t reserved_entropy[3]; 28 uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ 29 uint32_t reserved_entropy_latched[3]; 30 31 uint32_t reserved1[4]; 32 33 mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */ 34 uint32_t hw_digctl_dbgrd; /* 0x0d0 */ 35 uint32_t reserved_hw_digctl_dbgrd[3]; 36 uint32_t hw_digctl_dbg; /* 0x0e0 */ 37 uint32_t reserved_hw_digctl_dbg[3]; 38 39 uint32_t reserved2[4]; 40 41 mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */ 42 mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */ 43 mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */ 44 mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */ 45 mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */ 46 mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */ 47 mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */ 48 mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */ 49 mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */ 50 mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */ 51 mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ 52 mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ 53 mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ 54 mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ 55 mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ 56 57 uint32_t reserved3[36]; 58 59 uint32_t hw_digctl_scratch0; /* 0x280 */ 60 uint32_t reserved_hw_digctl_scratch0[3]; 61 uint32_t hw_digctl_scratch1; /* 0x290 */ 62 uint32_t reserved_hw_digctl_scratch1[3]; 63 uint32_t hw_digctl_armcache; /* 0x2a0 */ 64 uint32_t reserved_hw_digctl_armcache[3]; 65 mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ 66 uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ 67 uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; 68 uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ 69 uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; 70 uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ 71 uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; 72 uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ 73 uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; 74 uint32_t hw_digctl_fsl; /* 0x300 */ 75 uint32_t reserved_hw_digctl_fsl[3]; 76 uint32_t hw_digctl_chipid; /* 0x310 */ 77 uint32_t reserved_hw_digctl_chipid[3]; 78 79 uint32_t reserved4[4]; 80 81 uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ 82 uint32_t reserved_hw_digctl_ahb_stats_select[3]; 83 84 uint32_t reserved5[12]; 85 86 uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ 87 uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; 88 uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ 89 uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; 90 uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ 91 uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; 92 uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ 93 uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; 94 uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ 95 uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; 96 uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ 97 uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; 98 uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ 99 uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; 100 uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ 101 uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; 102 uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ 103 uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; 104 105 uint32_t reserved6[64]; 106 107 uint32_t hw_digctl_mpte0_loc; /* 0x500 */ 108 uint32_t reserved_hw_digctl_mpte0_loc[3]; 109 uint32_t hw_digctl_mpte1_loc; /* 0x510 */ 110 uint32_t reserved_hw_digctl_mpte1_loc[3]; 111 uint32_t hw_digctl_mpte2_loc; /* 0x520 */ 112 uint32_t reserved_hw_digctl_mpte2_loc[3]; 113 uint32_t hw_digctl_mpte3_loc; /* 0x530 */ 114 uint32_t reserved_hw_digctl_mpte3_loc[3]; 115 uint32_t hw_digctl_mpte4_loc; /* 0x540 */ 116 uint32_t reserved_hw_digctl_mpte4_loc[3]; 117 uint32_t hw_digctl_mpte5_loc; /* 0x550 */ 118 uint32_t reserved_hw_digctl_mpte5_loc[3]; 119 uint32_t hw_digctl_mpte6_loc; /* 0x560 */ 120 uint32_t reserved_hw_digctl_mpte6_loc[3]; 121 uint32_t hw_digctl_mpte7_loc; /* 0x570 */ 122 uint32_t reserved_hw_digctl_mpte7_loc[3]; 123 uint32_t hw_digctl_mpte8_loc; /* 0x580 */ 124 uint32_t reserved_hw_digctl_mpte8_loc[3]; 125 uint32_t hw_digctl_mpte9_loc; /* 0x590 */ 126 uint32_t reserved_hw_digctl_mpte9_loc[3]; 127 uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ 128 uint32_t reserved_hw_digctl_mpte10_loc[3]; 129 uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ 130 uint32_t reserved_hw_digctl_mpte11_loc[3]; 131 uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ 132 uint32_t reserved_hw_digctl_mpte12_loc[3]; 133 uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ 134 uint32_t reserved_hw_digctl_mpte13_loc[3]; 135 uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ 136 uint32_t reserved_hw_digctl_mpte14_loc[3]; 137 uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ 138 uint32_t reserved_hw_digctl_mpte15_loc[3]; 139 }; 140 #endif 141 142 /* Product code identification */ 143 #define HW_DIGCTL_CHIPID_MASK (0xffff << 16) 144 #define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16) 145 #define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16) 146 147 #endif /* __MX28_REGS_DIGCTL_H__ */ 148