1 /* 2 * Freescale i.MX28 CLKCTRL Register Definitions 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #ifndef __MX28_REGS_CLKCTRL_H__ 27 #define __MX28_REGS_CLKCTRL_H__ 28 29 #include <asm/imx-common/regs-common.h> 30 31 #ifndef __ASSEMBLY__ 32 struct mxs_clkctrl_regs { 33 mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ 34 uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ 35 uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ 36 mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ 37 uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */ 38 uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */ 39 mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ 40 mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */ 41 mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ 42 mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ 43 mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ 44 mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */ 45 mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ 46 mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ 47 mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ 48 mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ 49 mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ 50 mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ 51 mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ 52 mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */ 53 mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */ 54 mxs_reg_32(hw_clkctrl_etm) /* 0x130 */ 55 mxs_reg_32(hw_clkctrl_enet) /* 0x140 */ 56 mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */ 57 mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */ 58 59 uint32_t reserved[16]; 60 61 mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ 62 mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ 63 mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ 64 mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */ 65 mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */ 66 mxs_reg_32(hw_clkctrl_version) /* 0x200 */ 67 }; 68 #endif 69 70 #define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) 71 #define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 72 #define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) 73 #define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) 74 #define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) 75 #define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) 76 #define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) 77 #define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 78 #define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) 79 #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) 80 #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) 81 #define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) 82 #define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) 83 #define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 84 #define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) 85 #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) 86 #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) 87 #define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) 88 #define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) 89 #define CLKCTRL_PLL0CTRL0_POWER (1 << 17) 90 91 #define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) 92 #define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) 93 #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff 94 #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 95 96 #define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) 97 #define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) 98 #define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 99 #define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) 100 #define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) 101 #define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) 102 #define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) 103 #define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) 104 #define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 105 #define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) 106 #define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) 107 #define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) 108 #define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) 109 #define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) 110 #define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 111 #define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) 112 #define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) 113 #define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) 114 #define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) 115 #define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) 116 #define CLKCTRL_PLL1CTRL0_POWER (1 << 17) 117 118 #define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) 119 #define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) 120 #define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff 121 #define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 122 123 #define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) 124 #define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) 125 #define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 126 #define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) 127 #define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) 128 #define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 129 #define CLKCTRL_PLL2CTRL0_POWER (1 << 23) 130 131 #define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) 132 #define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) 133 #define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) 134 #define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) 135 #define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 136 #define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) 137 #define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) 138 #define CLKCTRL_CPU_DIV_CPU_MASK 0x3f 139 #define CLKCTRL_CPU_DIV_CPU_OFFSET 0 140 141 #define CLKCTRL_HBUS_ASM_BUSY (1 << 31) 142 #define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) 143 #define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) 144 #define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) 145 #define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) 146 #define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) 147 #define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) 148 #define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) 149 #define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) 150 #define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) 151 #define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) 152 #define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) 153 #define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) 154 #define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 155 #define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) 156 #define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) 157 #define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) 158 #define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) 159 #define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) 160 #define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) 161 #define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) 162 #define CLKCTRL_HBUS_DIV_MASK 0x1f 163 #define CLKCTRL_HBUS_DIV_OFFSET 0 164 165 #define CLKCTRL_XBUS_BUSY (1 << 31) 166 #define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) 167 #define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) 168 #define CLKCTRL_XBUS_DIV_MASK 0x3ff 169 #define CLKCTRL_XBUS_DIV_OFFSET 0 170 171 #define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) 172 #define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) 173 #define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) 174 #define CLKCTRL_XTAL_DIV_UART_MASK 0x3 175 #define CLKCTRL_XTAL_DIV_UART_OFFSET 0 176 177 #define CLKCTRL_SSP_CLKGATE (1 << 31) 178 #define CLKCTRL_SSP_BUSY (1 << 29) 179 #define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) 180 #define CLKCTRL_SSP_DIV_MASK 0x1ff 181 #define CLKCTRL_SSP_DIV_OFFSET 0 182 183 #define CLKCTRL_GPMI_CLKGATE (1 << 31) 184 #define CLKCTRL_GPMI_BUSY (1 << 29) 185 #define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) 186 #define CLKCTRL_GPMI_DIV_MASK 0x3ff 187 #define CLKCTRL_GPMI_DIV_OFFSET 0 188 189 #define CLKCTRL_SPDIF_CLKGATE (1 << 31) 190 191 #define CLKCTRL_EMI_CLKGATE (1 << 31) 192 #define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) 193 #define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) 194 #define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) 195 #define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) 196 #define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) 197 #define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) 198 #define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) 199 #define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) 200 #define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 201 #define CLKCTRL_EMI_DIV_EMI_MASK 0x3f 202 #define CLKCTRL_EMI_DIV_EMI_OFFSET 0 203 204 #define CLKCTRL_SAIF0_CLKGATE (1 << 31) 205 #define CLKCTRL_SAIF0_BUSY (1 << 29) 206 #define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) 207 #define CLKCTRL_SAIF0_DIV_MASK 0xffff 208 #define CLKCTRL_SAIF0_DIV_OFFSET 0 209 210 #define CLKCTRL_SAIF1_CLKGATE (1 << 31) 211 #define CLKCTRL_SAIF1_BUSY (1 << 29) 212 #define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) 213 #define CLKCTRL_SAIF1_DIV_MASK 0xffff 214 #define CLKCTRL_SAIF1_DIV_OFFSET 0 215 216 #define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) 217 #define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) 218 #define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) 219 #define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff 220 #define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 221 222 #define CLKCTRL_ETM_CLKGATE (1 << 31) 223 #define CLKCTRL_ETM_BUSY (1 << 29) 224 #define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) 225 #define CLKCTRL_ETM_DIV_MASK 0x7f 226 #define CLKCTRL_ETM_DIV_OFFSET 0 227 228 #define CLKCTRL_ENET_SLEEP (1 << 31) 229 #define CLKCTRL_ENET_DISABLE (1 << 30) 230 #define CLKCTRL_ENET_STATUS (1 << 29) 231 #define CLKCTRL_ENET_BUSY_TIME (1 << 27) 232 #define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) 233 #define CLKCTRL_ENET_DIV_TIME_OFFSET 21 234 #define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) 235 #define CLKCTRL_ENET_TIME_SEL_OFFSET 19 236 #define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) 237 #define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) 238 #define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) 239 #define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) 240 #define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) 241 #define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) 242 #define CLKCTRL_ENET_RESET_BY_SW (1 << 16) 243 244 #define CLKCTRL_HSADC_RESETB (1 << 30) 245 #define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) 246 #define CLKCTRL_HSADC_FREQDIV_OFFSET 28 247 248 #define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) 249 #define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) 250 #define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) 251 #define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) 252 253 #define CLKCTRL_FRAC_CLKGATE (1 << 7) 254 #define CLKCTRL_FRAC_STABLE (1 << 6) 255 #define CLKCTRL_FRAC_FRAC_MASK 0x3f 256 #define CLKCTRL_FRAC_FRAC_OFFSET 0 257 #define CLKCTRL_FRAC0_CPU 0 258 #define CLKCTRL_FRAC0_EMI 1 259 #define CLKCTRL_FRAC0_IO1 2 260 #define CLKCTRL_FRAC0_IO0 3 261 #define CLKCTRL_FRAC1_PIX 0 262 #define CLKCTRL_FRAC1_HSADC 1 263 #define CLKCTRL_FRAC1_GPMI 2 264 265 #define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) 266 #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) 267 #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) 268 #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) 269 #define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) 270 #define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) 271 #define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) 272 #define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) 273 #define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) 274 #define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) 275 #define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) 276 #define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) 277 #define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) 278 279 #define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) 280 #define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) 281 #define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) 282 #define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) 283 #define CLKCTRL_RESET_CHIP (1 << 1) 284 #define CLKCTRL_RESET_DIG (1 << 0) 285 286 #define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) 287 #define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 288 289 #define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) 290 #define CLKCTRL_VERSION_MAJOR_OFFSET 24 291 #define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) 292 #define CLKCTRL_VERSION_MINOR_OFFSET 16 293 #define CLKCTRL_VERSION_STEP_MASK 0xffff 294 #define CLKCTRL_VERSION_STEP_OFFSET 0 295 296 #endif /* __MX28_REGS_CLKCTRL_H__ */ 297