1 /*
2  * Freescale i.MX23 CLKCTRL Register Definitions
3  *
4  * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * Based on code from LTIB:
8  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef __MX23_REGS_CLKCTRL_H__
14 #define __MX23_REGS_CLKCTRL_H__
15 
16 #include <asm/mach-imx/regs-common.h>
17 
18 #ifndef	__ASSEMBLY__
19 struct mxs_clkctrl_regs {
20 	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
21 	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
22 	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
23 	mxs_reg_32(hw_clkctrl_cpu)		/* 0x20 */
24 	mxs_reg_32(hw_clkctrl_hbus)		/* 0x30 */
25 	mxs_reg_32(hw_clkctrl_xbus)		/* 0x40 */
26 	mxs_reg_32(hw_clkctrl_xtal)		/* 0x50 */
27 	mxs_reg_32(hw_clkctrl_pix)		/* 0x60 */
28 	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x70 */
29 	mxs_reg_32(hw_clkctrl_gpmi)		/* 0x80 */
30 	mxs_reg_32(hw_clkctrl_spdif)		/* 0x90 */
31 	mxs_reg_32(hw_clkctrl_emi)		/* 0xa0 */
32 
33 	uint32_t	reserved1[4];
34 
35 	mxs_reg_32(hw_clkctrl_saif0)		/* 0xc0 */
36 	mxs_reg_32(hw_clkctrl_tv)		/* 0xd0 */
37 	mxs_reg_32(hw_clkctrl_etm)		/* 0xe0 */
38 	mxs_reg_8(hw_clkctrl_frac0)		/* 0xf0 */
39 	mxs_reg_8(hw_clkctrl_frac1)		/* 0x100 */
40 	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x110 */
41 	mxs_reg_32(hw_clkctrl_reset)		/* 0x120 */
42 	mxs_reg_32(hw_clkctrl_status)		/* 0x130 */
43 	mxs_reg_32(hw_clkctrl_version)		/* 0x140 */
44 };
45 #endif
46 
47 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
48 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
49 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
50 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
51 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
52 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
53 #define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
54 #define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
55 #define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
56 #define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
57 #define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
58 #define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
59 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
60 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
61 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
62 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
63 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
64 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
65 #define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
66 #define	CLKCTRL_PLL0CTRL0_POWER			(1 << 16)
67 
68 #define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
69 #define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
70 #define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
71 #define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
72 
73 #define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
74 #define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
75 #define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
76 #define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
77 #define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
78 #define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
79 #define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
80 #define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
81 #define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
82 
83 #define	CLKCTRL_HBUS_BUSY			(1 << 29)
84 #define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 28)
85 #define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 27)
86 #define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
87 #define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
88 #define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
89 #define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
90 #define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
91 #define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
92 #define	CLKCTRL_HBUS_AUTO_SLOW_MODE		(1 << 20)
93 #define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
94 #define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
95 #define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
96 #define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
97 #define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
98 #define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
99 #define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
100 #define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
101 #define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
102 #define	CLKCTRL_HBUS_DIV_MASK			0x1f
103 #define	CLKCTRL_HBUS_DIV_OFFSET			0
104 
105 #define	CLKCTRL_XBUS_BUSY			(1 << 31)
106 #define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
107 #define	CLKCTRL_XBUS_DIV_MASK			0x3ff
108 #define	CLKCTRL_XBUS_DIV_OFFSET			0
109 
110 #define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
111 #define	CLKCTRL_XTAL_FILT_CLK24M_GATE		(1 << 30)
112 #define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
113 #define	CLKCTRL_XTAL_DRI_CLK24M_GATE		(1 << 28)
114 #define	CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE		(1 << 27)
115 #define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
116 #define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
117 #define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
118 
119 #define	CLKCTRL_PIX_CLKGATE			(1 << 31)
120 #define	CLKCTRL_PIX_BUSY			(1 << 29)
121 #define	CLKCTRL_PIX_DIV_FRAC_EN			(1 << 12)
122 #define	CLKCTRL_PIX_DIV_MASK			0xfff
123 #define	CLKCTRL_PIX_DIV_OFFSET			0
124 
125 #define	CLKCTRL_SSP_CLKGATE			(1 << 31)
126 #define	CLKCTRL_SSP_BUSY			(1 << 29)
127 #define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
128 #define	CLKCTRL_SSP_DIV_MASK			0x1ff
129 #define	CLKCTRL_SSP_DIV_OFFSET			0
130 
131 #define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
132 #define	CLKCTRL_GPMI_BUSY			(1 << 29)
133 #define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
134 #define	CLKCTRL_GPMI_DIV_MASK			0x3ff
135 #define	CLKCTRL_GPMI_DIV_OFFSET			0
136 
137 #define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
138 
139 #define	CLKCTRL_EMI_CLKGATE			(1 << 31)
140 #define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
141 #define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
142 #define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
143 #define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
144 #define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
145 #define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
146 #define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
147 #define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
148 #define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
149 #define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
150 #define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
151 
152 #define	CLKCTRL_IR_CLKGATE			(1 << 31)
153 #define	CLKCTRL_IR_AUTO_DIV			(1 << 29)
154 #define	CLKCTRL_IR_IR_BUSY			(1 << 28)
155 #define	CLKCTRL_IR_IROV_BUSY			(1 << 27)
156 #define	CLKCTRL_IR_IROV_DIV_MASK		(0x1ff << 16)
157 #define	CLKCTRL_IR_IROV_DIV_OFFSET		16
158 #define	CLKCTRL_IR_IR_DIV_MASK			0x3ff
159 #define	CLKCTRL_IR_IR_DIV_OFFSET		0
160 
161 #define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
162 #define	CLKCTRL_SAIF0_BUSY			(1 << 29)
163 #define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
164 #define	CLKCTRL_SAIF0_DIV_MASK			0xffff
165 #define	CLKCTRL_SAIF0_DIV_OFFSET		0
166 
167 #define	CLKCTRL_TV_CLK_TV108M_GATE		(1 << 31)
168 #define	CLKCTRL_TV_CLK_TV_GATE			(1 << 30)
169 
170 #define	CLKCTRL_ETM_CLKGATE			(1 << 31)
171 #define	CLKCTRL_ETM_BUSY			(1 << 29)
172 #define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 6)
173 #define	CLKCTRL_ETM_DIV_MASK			0x3f
174 #define	CLKCTRL_ETM_DIV_OFFSET			0
175 
176 #define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
177 #define	CLKCTRL_FRAC_STABLE			(1 << 6)
178 #define	CLKCTRL_FRAC_FRAC_MASK			0x3f
179 #define	CLKCTRL_FRAC_FRAC_OFFSET		0
180 #define	CLKCTRL_FRAC0_CPU			0
181 #define	CLKCTRL_FRAC0_EMI			1
182 #define	CLKCTRL_FRAC0_PIX			2
183 #define	CLKCTRL_FRAC0_IO0			3
184 #define	CLKCTRL_FRAC1_VID			3
185 
186 #define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
187 #define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 7)
188 #define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 6)
189 #define	CLKCTRL_CLKSEQ_BYPASS_SSP0		(1 << 5)
190 #define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 4)
191 #define	CLKCTRL_CLKSEQ_BYPASS_IR		(1 << 3)
192 #define	CLKCTRL_CLKSEQ_BYPASS_PIX		(1 << 1)
193 #define	CLKCTRL_CLKSEQ_BYPASS_SAIF		(1 << 0)
194 
195 #define	CLKCTRL_RESET_CHIP			(1 << 1)
196 #define	CLKCTRL_RESET_DIG			(1 << 0)
197 
198 #define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
199 #define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
200 
201 #define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
202 #define	CLKCTRL_VERSION_MAJOR_OFFSET		24
203 #define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
204 #define	CLKCTRL_VERSION_MINOR_OFFSET		16
205 #define	CLKCTRL_VERSION_STEP_MASK		0xffff
206 #define	CLKCTRL_VERSION_STEP_OFFSET		0
207 
208 #endif /* __MX23_REGS_CLKCTRL_H__ */
209