1 /*
2  * Freescale i.MX23 CLKCTRL Register Definitions
3  *
4  * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * Based on code from LTIB:
8  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  */
25 
26 #ifndef __MX23_REGS_CLKCTRL_H__
27 #define __MX23_REGS_CLKCTRL_H__
28 
29 #include <asm/imx-common/regs-common.h>
30 
31 #ifndef	__ASSEMBLY__
32 struct mxs_clkctrl_regs {
33 	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
34 	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
35 	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
36 	mxs_reg_32(hw_clkctrl_cpu)		/* 0x20 */
37 	mxs_reg_32(hw_clkctrl_hbus)		/* 0x30 */
38 	mxs_reg_32(hw_clkctrl_xbus)		/* 0x40 */
39 	mxs_reg_32(hw_clkctrl_xtal)		/* 0x50 */
40 	mxs_reg_32(hw_clkctrl_pix)		/* 0x60 */
41 	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x70 */
42 	mxs_reg_32(hw_clkctrl_gpmi)		/* 0x80 */
43 	mxs_reg_32(hw_clkctrl_spdif)		/* 0x90 */
44 	mxs_reg_32(hw_clkctrl_emi)		/* 0xa0 */
45 
46 	uint32_t	reserved1[4];
47 
48 	mxs_reg_32(hw_clkctrl_saif0)		/* 0xc0 */
49 	mxs_reg_32(hw_clkctrl_tv)		/* 0xd0 */
50 	mxs_reg_32(hw_clkctrl_etm)		/* 0xe0 */
51 	mxs_reg_8(hw_clkctrl_frac0)		/* 0xf0 */
52 	mxs_reg_8(hw_clkctrl_frac1)		/* 0x100 */
53 	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x110 */
54 	mxs_reg_32(hw_clkctrl_reset)		/* 0x120 */
55 	mxs_reg_32(hw_clkctrl_status)		/* 0x130 */
56 	mxs_reg_32(hw_clkctrl_version)		/* 0x140 */
57 };
58 #endif
59 
60 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
61 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
62 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
63 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
64 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
65 #define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
66 #define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
67 #define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
68 #define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
69 #define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
70 #define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
71 #define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
72 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
73 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
74 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
75 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
76 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
77 #define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
78 #define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
79 #define	CLKCTRL_PLL0CTRL0_POWER			(1 << 16)
80 
81 #define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
82 #define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
83 #define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
84 #define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
85 
86 #define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
87 #define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
88 #define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
89 #define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
90 #define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
91 #define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
92 #define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
93 #define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
94 #define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
95 
96 #define	CLKCTRL_HBUS_BUSY			(1 << 29)
97 #define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 28)
98 #define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 27)
99 #define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
100 #define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
101 #define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
102 #define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
103 #define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
104 #define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
105 #define	CLKCTRL_HBUS_AUTO_SLOW_MODE		(1 << 20)
106 #define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
107 #define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
108 #define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
109 #define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
110 #define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
111 #define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
112 #define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
113 #define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
114 #define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
115 #define	CLKCTRL_HBUS_DIV_MASK			0x1f
116 #define	CLKCTRL_HBUS_DIV_OFFSET			0
117 
118 #define	CLKCTRL_XBUS_BUSY			(1 << 31)
119 #define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
120 #define	CLKCTRL_XBUS_DIV_MASK			0x3ff
121 #define	CLKCTRL_XBUS_DIV_OFFSET			0
122 
123 #define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
124 #define	CLKCTRL_XTAL_FILT_CLK24M_GATE		(1 << 30)
125 #define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
126 #define	CLKCTRL_XTAL_DRI_CLK24M_GATE		(1 << 28)
127 #define	CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE		(1 << 27)
128 #define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
129 #define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
130 #define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
131 
132 #define	CLKCTRL_PIX_CLKGATE			(1 << 31)
133 #define	CLKCTRL_PIX_BUSY			(1 << 29)
134 #define	CLKCTRL_PIX_DIV_FRAC_EN			(1 << 12)
135 #define	CLKCTRL_PIX_DIV_MASK			0xfff
136 #define	CLKCTRL_PIX_DIV_OFFSET			0
137 
138 #define	CLKCTRL_SSP_CLKGATE			(1 << 31)
139 #define	CLKCTRL_SSP_BUSY			(1 << 29)
140 #define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
141 #define	CLKCTRL_SSP_DIV_MASK			0x1ff
142 #define	CLKCTRL_SSP_DIV_OFFSET			0
143 
144 #define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
145 #define	CLKCTRL_GPMI_BUSY			(1 << 29)
146 #define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
147 #define	CLKCTRL_GPMI_DIV_MASK			0x3ff
148 #define	CLKCTRL_GPMI_DIV_OFFSET			0
149 
150 #define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
151 
152 #define	CLKCTRL_EMI_CLKGATE			(1 << 31)
153 #define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
154 #define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
155 #define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
156 #define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
157 #define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
158 #define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
159 #define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
160 #define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
161 #define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
162 #define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
163 #define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
164 
165 #define	CLKCTRL_IR_CLKGATE			(1 << 31)
166 #define	CLKCTRL_IR_AUTO_DIV			(1 << 29)
167 #define	CLKCTRL_IR_IR_BUSY			(1 << 28)
168 #define	CLKCTRL_IR_IROV_BUSY			(1 << 27)
169 #define	CLKCTRL_IR_IROV_DIV_MASK		(0x1ff << 16)
170 #define	CLKCTRL_IR_IROV_DIV_OFFSET		16
171 #define	CLKCTRL_IR_IR_DIV_MASK			0x3ff
172 #define	CLKCTRL_IR_IR_DIV_OFFSET		0
173 
174 #define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
175 #define	CLKCTRL_SAIF0_BUSY			(1 << 29)
176 #define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
177 #define	CLKCTRL_SAIF0_DIV_MASK			0xffff
178 #define	CLKCTRL_SAIF0_DIV_OFFSET		0
179 
180 #define	CLKCTRL_TV_CLK_TV108M_GATE		(1 << 31)
181 #define	CLKCTRL_TV_CLK_TV_GATE			(1 << 30)
182 
183 #define	CLKCTRL_ETM_CLKGATE			(1 << 31)
184 #define	CLKCTRL_ETM_BUSY			(1 << 29)
185 #define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 6)
186 #define	CLKCTRL_ETM_DIV_MASK			0x3f
187 #define	CLKCTRL_ETM_DIV_OFFSET			0
188 
189 #define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
190 #define	CLKCTRL_FRAC_STABLE			(1 << 6)
191 #define	CLKCTRL_FRAC_FRAC_MASK			0x3f
192 #define	CLKCTRL_FRAC_FRAC_OFFSET		0
193 #define	CLKCTRL_FRAC0_CPU			0
194 #define	CLKCTRL_FRAC0_EMI			1
195 #define	CLKCTRL_FRAC0_PIX			2
196 #define	CLKCTRL_FRAC0_IO0			3
197 #define	CLKCTRL_FRAC1_VID			3
198 
199 #define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
200 #define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 7)
201 #define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 6)
202 #define	CLKCTRL_CLKSEQ_BYPASS_SSP0		(1 << 5)
203 #define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 4)
204 #define	CLKCTRL_CLKSEQ_BYPASS_IR		(1 << 3)
205 #define	CLKCTRL_CLKSEQ_BYPASS_PIX		(1 << 1)
206 #define	CLKCTRL_CLKSEQ_BYPASS_SAIF		(1 << 0)
207 
208 #define	CLKCTRL_RESET_CHIP			(1 << 1)
209 #define	CLKCTRL_RESET_DIG			(1 << 0)
210 
211 #define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
212 #define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
213 
214 #define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
215 #define	CLKCTRL_VERSION_MAJOR_OFFSET		24
216 #define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
217 #define	CLKCTRL_VERSION_MINOR_OFFSET		16
218 #define	CLKCTRL_VERSION_STEP_MASK		0xffff
219 #define	CLKCTRL_VERSION_STEP_OFFSET		0
220 
221 #endif /* __MX23_REGS_CLKCTRL_H__ */
222