1*7bc1ca39SPeng Fan /* 2*7bc1ca39SPeng Fan * Copyright (C) 2016 Freescale Semiconductor, Inc. 3*7bc1ca39SPeng Fan * 4*7bc1ca39SPeng Fan * SPDX-License-Identifier: GPL-2.0+ 5*7bc1ca39SPeng Fan */ 6*7bc1ca39SPeng Fan 7*7bc1ca39SPeng Fan #ifndef _MX7ULP_REGS_H_ 8*7bc1ca39SPeng Fan #define _MX7ULP_REGS_H_ 9*7bc1ca39SPeng Fan 10*7bc1ca39SPeng Fan #include <linux/sizes.h> 11*7bc1ca39SPeng Fan 12*7bc1ca39SPeng Fan #define CAAM_SEC_SRAM_BASE (0x26000000) 13*7bc1ca39SPeng Fan #define CAAM_SEC_SRAM_SIZE (SZ_32K) 14*7bc1ca39SPeng Fan #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) 15*7bc1ca39SPeng Fan 16*7bc1ca39SPeng Fan #define OCRAM_0_BASE (0x2F000000) 17*7bc1ca39SPeng Fan #define OCRAM_0_SIZE (SZ_128K) 18*7bc1ca39SPeng Fan #define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) 19*7bc1ca39SPeng Fan 20*7bc1ca39SPeng Fan #define OCRAM_1_BASE (0x2F020000) 21*7bc1ca39SPeng Fan #define OCRAM_1_SIZE (SZ_128K) 22*7bc1ca39SPeng Fan #define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1) 23*7bc1ca39SPeng Fan 24*7bc1ca39SPeng Fan #define TCML_BASE (0x1FFD0000) 25*7bc1ca39SPeng Fan #define TCMU_BASE (0x20000000) 26*7bc1ca39SPeng Fan 27*7bc1ca39SPeng Fan #define AIPS3_BASE (0x40800000UL) 28*7bc1ca39SPeng Fan #define AIPS3_SLOT_SIZE (SZ_64K) 29*7bc1ca39SPeng Fan #define AIPS2_BASE (0x40000000UL) 30*7bc1ca39SPeng Fan #define AIPS2_SLOT_SIZE (SZ_64K) 31*7bc1ca39SPeng Fan #define AIPS1_BASE (0x41080000UL) 32*7bc1ca39SPeng Fan #define AIPS1_SLOT_SIZE (SZ_4K) 33*7bc1ca39SPeng Fan #define AIPS0_BASE (0x41000000UL) 34*7bc1ca39SPeng Fan #define AIPS0_SLOT_SIZE (SZ_4K) 35*7bc1ca39SPeng Fan #define IOMUXC0_AIPS0_SLOT (61) 36*7bc1ca39SPeng Fan #define WDG0_AIPS0_SLOT (37) 37*7bc1ca39SPeng Fan #define WDG1_AIPS2_SLOT (61) 38*7bc1ca39SPeng Fan #define WDG2_AIPS2_SLOT (67) 39*7bc1ca39SPeng Fan #define WDG0_PCC0_SLOT (37) 40*7bc1ca39SPeng Fan #define IOMUXC1_AIPS3_SLOT (44) 41*7bc1ca39SPeng Fan #define CMC0_AIPS1_SLOT (36) 42*7bc1ca39SPeng Fan #define CMC1_AIPS2_SLOT (65) 43*7bc1ca39SPeng Fan #define SCG0_AIPS0_SLOT (39) 44*7bc1ca39SPeng Fan #define PCC0_AIPS0_SLOT (38) 45*7bc1ca39SPeng Fan #define PCC1_AIPS1_SLOT (50) 46*7bc1ca39SPeng Fan #define PCC2_AIPS2_SLOT (63) 47*7bc1ca39SPeng Fan #define PCC3_AIPS3_SLOT (51) 48*7bc1ca39SPeng Fan #define SCG1_AIPS2_SLOT (62) 49*7bc1ca39SPeng Fan #define SIM0_AIPS1_SLOT (35) 50*7bc1ca39SPeng Fan #define SIM1_AIPS1_SLOT (48) 51*7bc1ca39SPeng Fan #define USBOTG0_AIPS2_SLOT (51) 52*7bc1ca39SPeng Fan #define USBOTG1_AIPS2_SLOT (52) 53*7bc1ca39SPeng Fan #define USBPHY_AIPS2_SLOT (53) 54*7bc1ca39SPeng Fan #define USDHC0_AIPS2_SLOT (55) 55*7bc1ca39SPeng Fan #define USDHC1_AIPS2_SLOT (56) 56*7bc1ca39SPeng Fan #define RGPIO2P0_AIPS0_SLOT (15) 57*7bc1ca39SPeng Fan #define RGPIO2P1_AIPS2_SLOT (15) 58*7bc1ca39SPeng Fan #define IOMUXC0_AIPS0_SLOT (61) 59*7bc1ca39SPeng Fan #define OCOTP_CTRL_AIPS1_SLOT (38) 60*7bc1ca39SPeng Fan #define OCOTP_CTRL_PCC1_SLOT (38) 61*7bc1ca39SPeng Fan #define SIM1_PCC1_SLOT (48) 62*7bc1ca39SPeng Fan #define MMDC0_AIPS3_SLOT (43) 63*7bc1ca39SPeng Fan #define IOMUXC_DDR_AIPS3_SLOT (45) 64*7bc1ca39SPeng Fan 65*7bc1ca39SPeng Fan #define LPI2C0_AIPS0_SLOT (51) 66*7bc1ca39SPeng Fan #define LPI2C1_AIPS0_SLOT (52) 67*7bc1ca39SPeng Fan #define LPI2C2_AIPS0_SLOT (53) 68*7bc1ca39SPeng Fan #define LPI2C3_AIPS0_SLOT (54) 69*7bc1ca39SPeng Fan #define LPI2C4_AIPS2_SLOT (43) 70*7bc1ca39SPeng Fan #define LPI2C5_AIPS2_SLOT (44) 71*7bc1ca39SPeng Fan #define LPI2C6_AIPS3_SLOT (36) 72*7bc1ca39SPeng Fan #define LPI2C7_AIPS3_SLOT (37) 73*7bc1ca39SPeng Fan 74*7bc1ca39SPeng Fan #define LPUART0_PCC0_SLOT (58) 75*7bc1ca39SPeng Fan #define LPUART1_PCC0_SLOT (59) 76*7bc1ca39SPeng Fan #define LPUART2_PCC1_SLOT (43) 77*7bc1ca39SPeng Fan #define LPUART3_PCC1_SLOT (44) 78*7bc1ca39SPeng Fan #define LPUART0_AIPS0_SLOT (58) 79*7bc1ca39SPeng Fan #define LPUART1_AIPS0_SLOT (59) 80*7bc1ca39SPeng Fan #define LPUART2_AIPS1_SLOT (43) 81*7bc1ca39SPeng Fan #define LPUART3_AIPS1_SLOT (44) 82*7bc1ca39SPeng Fan #define LPUART4_AIPS2_SLOT (45) 83*7bc1ca39SPeng Fan #define LPUART5_AIPS2_SLOT (46) 84*7bc1ca39SPeng Fan #define LPUART6_AIPS3_SLOT (38) 85*7bc1ca39SPeng Fan #define LPUART7_AIPS3_SLOT (39) 86*7bc1ca39SPeng Fan 87*7bc1ca39SPeng Fan #define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) 88*7bc1ca39SPeng Fan #define CORE_B_ROM_BASE (0x00000000) 89*7bc1ca39SPeng Fan 90*7bc1ca39SPeng Fan #define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE 91*7bc1ca39SPeng Fan #define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE 92*7bc1ca39SPeng Fan #define IRAM_BASE_ADDR OCRAM_0_BASE 93*7bc1ca39SPeng Fan #define IRAM_SIZE (SZ_128K + SZ_128K) 94*7bc1ca39SPeng Fan 95*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT0 (0<<8) 96*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT1 (1<<8) 97*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT2 (2<<8) 98*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT3 (3<<8) 99*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT4 (4<<8) 100*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT5 (5<<8) 101*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT6 (6<<8) 102*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT7 (7<<8) 103*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT8 (8<<8) 104*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT9 (9<<8) 105*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT10 (10<<8) 106*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT11 (11<<8) 107*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT12 (12<<8) 108*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT13 (13<<8) 109*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT14 (14<<8) 110*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT15 (15<<8) 111*7bc1ca39SPeng Fan 112*7bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT0 (0x0) 113*7bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT1 (0x1) 114*7bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT2 (0x2) 115*7bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT3 (0x3) 116*7bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT4 (0x4) 117*7bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT5 (0x5) 118*7bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT6 (0x6) 119*7bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT7 (0x7) 120*7bc1ca39SPeng Fan 121*7bc1ca39SPeng Fan 122*7bc1ca39SPeng Fan #define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) 123*7bc1ca39SPeng Fan #define SIM_SOPT1_PMIC_STBY_REQ (1<<2) 124*7bc1ca39SPeng Fan #define SIM_SOPT1_A7_SW_RESET (1<<0) 125*7bc1ca39SPeng Fan 126*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT_SHIFT (8) 127*7bc1ca39SPeng Fan #define IOMUXC_PCR_MUX_ALT_MASK (0xF00) 128*7bc1ca39SPeng Fan #define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) 129*7bc1ca39SPeng Fan 130*7bc1ca39SPeng Fan #define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) 131*7bc1ca39SPeng Fan #define IOMUXC1_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT))) 132*7bc1ca39SPeng Fan #define WDG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT))) 133*7bc1ca39SPeng Fan #define WDG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT))) 134*7bc1ca39SPeng Fan #define WDG2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT))) 135*7bc1ca39SPeng Fan #define SCG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT))) 136*7bc1ca39SPeng Fan #define SCG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT))) 137*7bc1ca39SPeng Fan #define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT))) 138*7bc1ca39SPeng Fan #define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT))) 139*7bc1ca39SPeng Fan #define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT))) 140*7bc1ca39SPeng Fan #define PCC3_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT))) 141*7bc1ca39SPeng Fan #define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) 142*7bc1ca39SPeng Fan #define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */ 143*7bc1ca39SPeng Fan #define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT))) 144*7bc1ca39SPeng Fan #define CMC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT))) 145*7bc1ca39SPeng Fan #define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT))) 146*7bc1ca39SPeng Fan #define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT))) 147*7bc1ca39SPeng Fan #define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT))) 148*7bc1ca39SPeng Fan #define MMDC0_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT))) 149*7bc1ca39SPeng Fan 150*7bc1ca39SPeng Fan #define USBOTG0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT))) 151*7bc1ca39SPeng Fan #define USBOTG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT))) 152*7bc1ca39SPeng Fan #define USBPHY_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT))) 153*7bc1ca39SPeng Fan #define USB_PHY0_BASE_ADDR USBPHY_RBASE 154*7bc1ca39SPeng Fan #define USB_BASE_ADDR USBOTG0_RBASE 155*7bc1ca39SPeng Fan 156*7bc1ca39SPeng Fan #define LPI2C1_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT))) 157*7bc1ca39SPeng Fan #define LPI2C2_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT))) 158*7bc1ca39SPeng Fan #define LPI2C3_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT))) 159*7bc1ca39SPeng Fan #define LPI2C4_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT))) 160*7bc1ca39SPeng Fan #define LPI2C5_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT))) 161*7bc1ca39SPeng Fan #define LPI2C6_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT))) 162*7bc1ca39SPeng Fan #define LPI2C7_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT))) 163*7bc1ca39SPeng Fan #define LPI2C8_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT))) 164*7bc1ca39SPeng Fan 165*7bc1ca39SPeng Fan #define LPUART0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT))) 166*7bc1ca39SPeng Fan #define LPUART1_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT))) 167*7bc1ca39SPeng Fan #define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT))) 168*7bc1ca39SPeng Fan #define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT))) 169*7bc1ca39SPeng Fan #define LPUART4_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT))) 170*7bc1ca39SPeng Fan #define LPUART5_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT))) 171*7bc1ca39SPeng Fan #define LPUART6_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT))) 172*7bc1ca39SPeng Fan #define LPUART7_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT))) 173*7bc1ca39SPeng Fan 174*7bc1ca39SPeng Fan #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) 175*7bc1ca39SPeng Fan #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) 176*7bc1ca39SPeng Fan 177*7bc1ca39SPeng Fan #define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) 178*7bc1ca39SPeng Fan #define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) 179*7bc1ca39SPeng Fan 180*7bc1ca39SPeng Fan #define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT)) 181*7bc1ca39SPeng Fan #define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT)) 182*7bc1ca39SPeng Fan #define CMC0_SRS (CMC0_RBASE + 0x20) 183*7bc1ca39SPeng Fan #define CMC0_SSRS (CMC0_RBASE + 0x28) 184*7bc1ca39SPeng Fan #define CMC1_SRS (CMC1_RBASE + 0x20) 185*7bc1ca39SPeng Fan #define CMC1_SSRS (CMC1_RBASE + 0x28) 186*7bc1ca39SPeng Fan 187*7bc1ca39SPeng Fan #define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0)) 188*7bc1ca39SPeng Fan #define IOMUXC0_PCR1 (IOMUXC0_RBASE + (4 * 1)) 189*7bc1ca39SPeng Fan #define IOMUXC0_PCR2 (IOMUXC0_RBASE + (4 * 2)) 190*7bc1ca39SPeng Fan #define IOMUXC0_PCR3 (IOMUXC0_RBASE + (4 * 3)) 191*7bc1ca39SPeng Fan #define IOMUXC0_PSMI62 (PSMI0_RBASE + (4 * 62)) 192*7bc1ca39SPeng Fan #define IOMUXC0_PSMI63 (PSMI0_RBASE + (4 * 63)) 193*7bc1ca39SPeng Fan #define IOMUXC0_PSMI64 (PSMI0_RBASE + (4 * 64)) 194*7bc1ca39SPeng Fan 195*7bc1ca39SPeng Fan #define SCG_CSR (SCG0_RBASE + 0x010) 196*7bc1ca39SPeng Fan #define SCG_RCCR (SCG0_RBASE + 0x014) 197*7bc1ca39SPeng Fan #define SCG_VCCR (SCG0_RBASE + 0x018) 198*7bc1ca39SPeng Fan #define SCG_HCCR (SCG0_RBASE + 0x01c) 199*7bc1ca39SPeng Fan 200*7bc1ca39SPeng Fan #define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT)) 201*7bc1ca39SPeng Fan #define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT)) 202*7bc1ca39SPeng Fan #define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT)) 203*7bc1ca39SPeng Fan #define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT)) 204*7bc1ca39SPeng Fan #define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT)) 205*7bc1ca39SPeng Fan #define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT)) 206*7bc1ca39SPeng Fan #define LPUART6_PCC_REG (PCC3_RBASE + (4 * LPUART6_PCC3_SLOT)) 207*7bc1ca39SPeng Fan #define LPUART7_PCC_REG (PCC3_RBASE + (4 * LPUART7_PCC3_SLOT)) 208*7bc1ca39SPeng Fan 209*7bc1ca39SPeng Fan #define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT)) 210*7bc1ca39SPeng Fan #define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT)) 211*7bc1ca39SPeng Fan 212*7bc1ca39SPeng Fan #define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT)) 213*7bc1ca39SPeng Fan #define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT)) 214*7bc1ca39SPeng Fan 215*7bc1ca39SPeng Fan #define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT)) 216*7bc1ca39SPeng Fan 217*7bc1ca39SPeng Fan #define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) 218*7bc1ca39SPeng Fan #define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) 219*7bc1ca39SPeng Fan 220*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) 221*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) 222*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) 223*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) 224*7bc1ca39SPeng Fan 225*7bc1ca39SPeng Fan 226*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) 227*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) 228*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) 229*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ3 ((IOMUXC_DDR_RBASE + (4 * 3))) 230*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ4 ((IOMUXC_DDR_RBASE + (4 * 4))) 231*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ5 ((IOMUXC_DDR_RBASE + (4 * 5))) 232*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ6 ((IOMUXC_DDR_RBASE + (4 * 6))) 233*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ7 ((IOMUXC_DDR_RBASE + (4 * 7))) 234*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ8 ((IOMUXC_DDR_RBASE + (4 * 8))) 235*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ9 ((IOMUXC_DDR_RBASE + (4 * 9))) 236*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ10 ((IOMUXC_DDR_RBASE + (4 * 10))) 237*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ11 ((IOMUXC_DDR_RBASE + (4 * 11))) 238*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ12 ((IOMUXC_DDR_RBASE + (4 * 12))) 239*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ13 ((IOMUXC_DDR_RBASE + (4 * 13))) 240*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ14 ((IOMUXC_DDR_RBASE + (4 * 14))) 241*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ15 ((IOMUXC_DDR_RBASE + (4 * 15))) 242*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ16 ((IOMUXC_DDR_RBASE + (4 * 16))) 243*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ17 ((IOMUXC_DDR_RBASE + (4 * 17))) 244*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ18 ((IOMUXC_DDR_RBASE + (4 * 18))) 245*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ19 ((IOMUXC_DDR_RBASE + (4 * 19))) 246*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ20 ((IOMUXC_DDR_RBASE + (4 * 20))) 247*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ21 ((IOMUXC_DDR_RBASE + (4 * 21))) 248*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ22 ((IOMUXC_DDR_RBASE + (4 * 22))) 249*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ23 ((IOMUXC_DDR_RBASE + (4 * 23))) 250*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ24 ((IOMUXC_DDR_RBASE + (4 * 24))) 251*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ25 ((IOMUXC_DDR_RBASE + (4 * 25))) 252*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ26 ((IOMUXC_DDR_RBASE + (4 * 26))) 253*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ27 ((IOMUXC_DDR_RBASE + (4 * 27))) 254*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ28 ((IOMUXC_DDR_RBASE + (4 * 28))) 255*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ29 ((IOMUXC_DDR_RBASE + (4 * 29))) 256*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ30 ((IOMUXC_DDR_RBASE + (4 * 30))) 257*7bc1ca39SPeng Fan #define IOMUXC_DPCR_DDR_DQ31 ((IOMUXC_DDR_RBASE + (4 * 31))) 258*7bc1ca39SPeng Fan 259*7bc1ca39SPeng Fan /* Remap the rgpio2p registers addr to driver's addr */ 260*7bc1ca39SPeng Fan #define RGPIO2P_GPIO1_BASE_ADDR RGPIO2P0_RBASE 261*7bc1ca39SPeng Fan #define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40) 262*7bc1ca39SPeng Fan #define RGPIO2P_GPIO3_BASE_ADDR (RGPIO2P1_RBASE) 263*7bc1ca39SPeng Fan #define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40) 264*7bc1ca39SPeng Fan #define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80) 265*7bc1ca39SPeng Fan #define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0) 266*7bc1ca39SPeng Fan 267*7bc1ca39SPeng Fan /* MMDC registers addresses */ 268*7bc1ca39SPeng Fan #define MMDC_MDCTL_OFFSET (0x000) 269*7bc1ca39SPeng Fan #define MMDC_MDPDC_OFFSET (0x004) 270*7bc1ca39SPeng Fan #define MMDC_MDOTC_OFFSET (0x008) 271*7bc1ca39SPeng Fan #define MMDC_MDCFG0_OFFSET (0x00C) 272*7bc1ca39SPeng Fan #define MMDC_MDCFG1_OFFSET (0x010) 273*7bc1ca39SPeng Fan #define MMDC_MDCFG2_OFFSET (0x014) 274*7bc1ca39SPeng Fan #define MMDC_MDMISC_OFFSET (0x018) 275*7bc1ca39SPeng Fan #define MMDC_MDSCR_OFFSET (0x01C) 276*7bc1ca39SPeng Fan #define MMDC_MDREF_OFFSET (0x020) 277*7bc1ca39SPeng Fan #define MMDC_MDRWD_OFFSET (0x02C) 278*7bc1ca39SPeng Fan #define MMDC_MDOR_OFFSET (0x030) 279*7bc1ca39SPeng Fan #define MMDC_MDMRR_OFFSET (0x034) 280*7bc1ca39SPeng Fan #define MMDC_MDCFG3LP_OFFSET (0x038) 281*7bc1ca39SPeng Fan #define MMDC_MDMR4_OFFSET (0x03C) 282*7bc1ca39SPeng Fan #define MMDC_MDASP_OFFSET (0x040) 283*7bc1ca39SPeng Fan 284*7bc1ca39SPeng Fan #define MMDC_MAARCR_OFFSET (0x400) 285*7bc1ca39SPeng Fan #define MMDC_MAPSR_OFFSET (0x404) 286*7bc1ca39SPeng Fan #define MMDC_MAEXIDR0_OFFSET (0x408) 287*7bc1ca39SPeng Fan #define MMDC_MAEXIDR1_OFFSET (0x40C) 288*7bc1ca39SPeng Fan #define MMDC_MADPCR0_OFFSET (0x410) 289*7bc1ca39SPeng Fan #define MMDC_MADPCR1_OFFSET (0x414) 290*7bc1ca39SPeng Fan #define MMDC_MADPSR0_OFFSET (0x418) 291*7bc1ca39SPeng Fan #define MMDC_MADPSR1_OFFSET (0x41C) 292*7bc1ca39SPeng Fan #define MMDC_MADPSR2_OFFSET (0x420) 293*7bc1ca39SPeng Fan #define MMDC_MADPSR3_OFFSET (0x424) 294*7bc1ca39SPeng Fan #define MMDC_MADPSR4_OFFSET (0x428) 295*7bc1ca39SPeng Fan #define MMDC_MADPSR5_OFFSET (0x42C) 296*7bc1ca39SPeng Fan #define MMDC_MASBS0_OFFSET (0x430) 297*7bc1ca39SPeng Fan #define MMDC_MASBS1_OFFSET (0x434) 298*7bc1ca39SPeng Fan #define MMDC_MAGENP_OFFSET (0x440) 299*7bc1ca39SPeng Fan 300*7bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL_OFFSET (0x800) 301*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_OFFSET (0x804) 302*7bc1ca39SPeng Fan #define MMDC_MPWLGCR_OFFSET (0x808) 303*7bc1ca39SPeng Fan #define MMDC_MPWLDECTRL0_OFFSET (0x80C) 304*7bc1ca39SPeng Fan #define MMDC_MPWLDECTRL1_OFFSET (0x810) 305*7bc1ca39SPeng Fan #define MMDC_MPWLDLST_OFFSET (0x814) 306*7bc1ca39SPeng Fan #define MMDC_MPODTCTRL_OFFSET (0x818) 307*7bc1ca39SPeng Fan #define MMDC_MPREDQBY0DL_OFFSET (0x81C) 308*7bc1ca39SPeng Fan #define MMDC_MPREDQBY1DL_OFFSET (0x820) 309*7bc1ca39SPeng Fan #define MMDC_MPREDQBY2DL_OFFSET (0x824) 310*7bc1ca39SPeng Fan #define MMDC_MPREDQBY3DL_OFFSET (0x828) 311*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_OFFSET (0x82C) 312*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_OFFSET (0x830) 313*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_OFFSET (0x834) 314*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_OFFSET (0x838) 315*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_OFFSET (0x83C) 316*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL1_OFFSET (0x840) 317*7bc1ca39SPeng Fan #define MMDC_MPDGDLST_OFFSET (0x844) 318*7bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_OFFSET (0x848) 319*7bc1ca39SPeng Fan #define MMDC_MPRDDLST_OFFSET (0x84C) 320*7bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_OFFSET (0x850) 321*7bc1ca39SPeng Fan #define MMDC_MPWRDLST_OFFSET (0x854) 322*7bc1ca39SPeng Fan #define MMDC_MPSDCTRL_OFFSET (0x858) 323*7bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_OFFSET (0x85C) 324*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_OFFSET (0x860) 325*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_OFFSET (0x864) 326*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWST0_OFFSET (0x868) 327*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWST1_OFFSET (0x86C) 328*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWST0_OFFSET (0x870) 329*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWST1_OFFSET (0x874) 330*7bc1ca39SPeng Fan #define MMDC_MPWLHWERR_OFFSET (0x878) 331*7bc1ca39SPeng Fan #define MMDC_MPDGHWST0_OFFSET (0x87C) 332*7bc1ca39SPeng Fan #define MMDC_MPDGHWST1_OFFSET (0x880) 333*7bc1ca39SPeng Fan #define MMDC_MPDGHWST2_OFFSET (0x884) 334*7bc1ca39SPeng Fan #define MMDC_MPDGHWST3_OFFSET (0x888) 335*7bc1ca39SPeng Fan #define MMDC_MPPDCMPR1_OFFSET (0x88C) 336*7bc1ca39SPeng Fan #define MMDC_MPPDCMPR2_OFFSET (0x890) 337*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_OFFSET (0x894) 338*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR0_OFFSET (0x898) 339*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR1_OFFSET (0x89C) 340*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR2_OFFSET (0x8A0) 341*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR3_OFFSET (0x8A4) 342*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR4_OFFSET (0x8A8) 343*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR5_OFFSET (0x8AC) 344*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR6_OFFSET (0x8B0) 345*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR7_OFFSET (0x8B4) 346*7bc1ca39SPeng Fan #define MMDC_MPMUR_OFFSET (0x8B8) 347*7bc1ca39SPeng Fan #define MMDC_MPWRCADL_OFFSET (0x8BC) 348*7bc1ca39SPeng Fan #define MMDC_MPDCCR_OFFSET (0x8C0) 349*7bc1ca39SPeng Fan #define MMDC_MPBC_OFFSET (0x8C4) 350*7bc1ca39SPeng Fan #define MMDC_MPSWDRAR_OFFSET (0x8C8) 351*7bc1ca39SPeng Fan 352*7bc1ca39SPeng Fan /* First MMDC invalid IPS address */ 353*7bc1ca39SPeng Fan #define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC) 354*7bc1ca39SPeng Fan #define MMDC_REGS_BASE MMDC0_RBASE 355*7bc1ca39SPeng Fan 356*7bc1ca39SPeng Fan #define MMDC_MDCTL ((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET)) 357*7bc1ca39SPeng Fan #define MMDC_MDPDC ((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET)) 358*7bc1ca39SPeng Fan #define MMDC_MDOTC ((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET)) 359*7bc1ca39SPeng Fan #define MMDC_MDCFG0 ((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET)) 360*7bc1ca39SPeng Fan #define MMDC_MDCFG1 ((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET)) 361*7bc1ca39SPeng Fan #define MMDC_MDCFG2 ((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET)) 362*7bc1ca39SPeng Fan #define MMDC_MDMISC ((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET)) 363*7bc1ca39SPeng Fan #define MMDC_MDSCR ((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET)) 364*7bc1ca39SPeng Fan #define MMDC_MDREF ((MMDC_REGS_BASE + MMDC_MDREF_OFFSET)) 365*7bc1ca39SPeng Fan #define MMDC_MDRWD ((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET)) 366*7bc1ca39SPeng Fan #define MMDC_MDOR ((MMDC_REGS_BASE + MMDC_MDOR_OFFSET)) 367*7bc1ca39SPeng Fan #define MMDC_MDMRR ((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET)) 368*7bc1ca39SPeng Fan #define MMDC_MDCFG3LP ((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET)) 369*7bc1ca39SPeng Fan #define MMDC_MDMR4 ((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET)) 370*7bc1ca39SPeng Fan #define MMDC_MDASP ((MMDC_REGS_BASE + MMDC_MDASP_OFFSET)) 371*7bc1ca39SPeng Fan 372*7bc1ca39SPeng Fan #define MMDC_MAARCR ((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET)) 373*7bc1ca39SPeng Fan #define MMDC_MAPSR ((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET)) 374*7bc1ca39SPeng Fan #define MMDC_MAEXIDR0 ((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET)) 375*7bc1ca39SPeng Fan #define MMDC_MAEXIDR1 ((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET)) 376*7bc1ca39SPeng Fan #define MMDC_MADPCR0 ((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET)) 377*7bc1ca39SPeng Fan #define MMDC_MADPCR1 ((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET)) 378*7bc1ca39SPeng Fan #define MMDC_MADPSR0 ((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET)) 379*7bc1ca39SPeng Fan #define MMDC_MADPSR1 ((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET)) 380*7bc1ca39SPeng Fan #define MMDC_MADPSR2 ((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET)) 381*7bc1ca39SPeng Fan #define MMDC_MADPSR3 ((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET)) 382*7bc1ca39SPeng Fan #define MMDC_MADPSR4 ((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET)) 383*7bc1ca39SPeng Fan #define MMDC_MADPSR5 ((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET)) 384*7bc1ca39SPeng Fan #define MMDC_MASBS0 ((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET)) 385*7bc1ca39SPeng Fan #define MMDC_MASBS1 ((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET)) 386*7bc1ca39SPeng Fan #define MMDC_MAGENP ((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET)) 387*7bc1ca39SPeng Fan 388*7bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET)) 389*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL ((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET)) 390*7bc1ca39SPeng Fan #define MMDC_MPWLGCR ((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET)) 391*7bc1ca39SPeng Fan #define MMDC_MPWLDECTRL0 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET)) 392*7bc1ca39SPeng Fan #define MMDC_MPWLDECTRL1 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET)) 393*7bc1ca39SPeng Fan #define MMDC_MPWLDLST ((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET)) 394*7bc1ca39SPeng Fan #define MMDC_MPODTCTRL ((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET)) 395*7bc1ca39SPeng Fan #define MMDC_MPREDQBY0DL ((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET)) 396*7bc1ca39SPeng Fan #define MMDC_MPREDQBY1DL ((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET)) 397*7bc1ca39SPeng Fan #define MMDC_MPREDQBY2DL ((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET)) 398*7bc1ca39SPeng Fan #define MMDC_MPREDQBY3DL ((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET)) 399*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET)) 400*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET)) 401*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET)) 402*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET)) 403*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0 ((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET)) 404*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) 405*7bc1ca39SPeng Fan #define MMDC_MPDGDLST ((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET)) 406*7bc1ca39SPeng Fan #define MMDC_MPRDDLCTL ((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET)) 407*7bc1ca39SPeng Fan #define MMDC_MPRDDLST ((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET)) 408*7bc1ca39SPeng Fan #define MMDC_MPWRDLCTL ((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET)) 409*7bc1ca39SPeng Fan #define MMDC_MPWRDLST ((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET)) 410*7bc1ca39SPeng Fan #define MMDC_MPSDCTRL ((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET)) 411*7bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL ((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET)) 412*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL ((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET)) 413*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL ((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET)) 414*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWST0 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET)) 415*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWST1 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET)) 416*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWST0 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET)) 417*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWST1 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET)) 418*7bc1ca39SPeng Fan #define MMDC_MPWLHWERR ((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET)) 419*7bc1ca39SPeng Fan #define MMDC_MPDGHWST0 ((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET)) 420*7bc1ca39SPeng Fan #define MMDC_MPDGHWST1 ((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET)) 421*7bc1ca39SPeng Fan #define MMDC_MPDGHWST2 ((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET)) 422*7bc1ca39SPeng Fan #define MMDC_MPDGHWST3 ((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET)) 423*7bc1ca39SPeng Fan #define MMDC_MPPDCMPR1 ((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET)) 424*7bc1ca39SPeng Fan #define MMDC_MPPDCMPR2 ((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET)) 425*7bc1ca39SPeng Fan #define MMDC_MPSWDAR ((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET)) 426*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR0 ((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET)) 427*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR1 ((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET)) 428*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR2 ((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET)) 429*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR3 ((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET)) 430*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR4 ((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET)) 431*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR5 ((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET)) 432*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR6 ((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET)) 433*7bc1ca39SPeng Fan #define MMDC_MPSWDRDR7 ((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET)) 434*7bc1ca39SPeng Fan #define MMDC_MPMUR ((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET)) 435*7bc1ca39SPeng Fan #define MMDC_MPWRCADL ((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET)) 436*7bc1ca39SPeng Fan #define MMDC_MPDCCR ((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET)) 437*7bc1ca39SPeng Fan #define MMDC_MPBC ((MMDC_REGS_BASE + MMDC_MPBC_OFFSET)) 438*7bc1ca39SPeng Fan #define MMDC_MPSWDRAR ((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET)) 439*7bc1ca39SPeng Fan 440*7bc1ca39SPeng Fan /* MMDC registers bit defines */ 441*7bc1ca39SPeng Fan #define MMDC_MDCTL_SDE_0 (31) 442*7bc1ca39SPeng Fan #define MMDC_MDCTL_SDE_1 (30) 443*7bc1ca39SPeng Fan #define MMDC_MDCTL_ROW (24) 444*7bc1ca39SPeng Fan #define MMDC_MDCTL_COL (20) 445*7bc1ca39SPeng Fan #define MMDC_MDCTL_BL (19) 446*7bc1ca39SPeng Fan #define MMDC_MDCTL_DSIZ (16) 447*7bc1ca39SPeng Fan 448*7bc1ca39SPeng Fan /* MDMISC */ 449*7bc1ca39SPeng Fan #define MMDC_MDMISC_CS0_RDY (31) 450*7bc1ca39SPeng Fan #define MMDC_MDMISC_CS1_RDY (30) 451*7bc1ca39SPeng Fan #define MMDC_MDMISC_CK1_DEL (22) 452*7bc1ca39SPeng Fan #define MMDC_MDMISC_CK1_GATING (21) 453*7bc1ca39SPeng Fan #define MMDC_MDMISC_CALIB_PER_CS (20) 454*7bc1ca39SPeng Fan #define MMDC_MDMISC_ADDR_MIRROR (19) 455*7bc1ca39SPeng Fan #define MMDC_MDMISC_LHD (18) 456*7bc1ca39SPeng Fan #define MMDC_MDMISC_WALAT (16) 457*7bc1ca39SPeng Fan #define MMDC_MDMISC_BI (12) 458*7bc1ca39SPeng Fan #define MMDC_MDMISC_LPDDR2_S (11) 459*7bc1ca39SPeng Fan #define MMDC_MDMISC_MIF3_MODE (9) 460*7bc1ca39SPeng Fan #define MMDC_MDMISC_RALAT (6) 461*7bc1ca39SPeng Fan #define MMDC_MDMISC_DDR_4_BANK (5) 462*7bc1ca39SPeng Fan #define MMDC_MDMISC_DDR_TYPE (3) 463*7bc1ca39SPeng Fan #define MMDC_MDMISC_RST (1) 464*7bc1ca39SPeng Fan 465*7bc1ca39SPeng Fan /* MPWLGCR */ 466*7bc1ca39SPeng Fan #define MMDC_MPWLGCR_WL_HW_ERR (8) 467*7bc1ca39SPeng Fan 468*7bc1ca39SPeng Fan /* MDSCR */ 469*7bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_ADDR_MSB (24) 470*7bc1ca39SPeng Fan #define MMDC_MDSCR_MR_OP (24) 471*7bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_ADDR_LSB (16) 472*7bc1ca39SPeng Fan #define MMDC_MDSCR_MR_ADDR (16) 473*7bc1ca39SPeng Fan #define MMDC_MDSCR_CON_REQ (15) 474*7bc1ca39SPeng Fan #define MMDC_MDSCR_CON_ACK (14) 475*7bc1ca39SPeng Fan #define MMDC_MDSCR_MRR_READ_DATA_VALID (10) 476*7bc1ca39SPeng Fan #define MMDC_MDSCR_WL_EN (9) 477*7bc1ca39SPeng Fan #define MMDC_MDSCR_CMD (4) 478*7bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_CS (3) 479*7bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_BA (0) 480*7bc1ca39SPeng Fan 481*7bc1ca39SPeng Fan /* MPZQHWCTRL */ 482*7bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL_ZQ_HW_FOR (16) 483*7bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL_ZQ_MODE (0) 484*7bc1ca39SPeng Fan 485*7bc1ca39SPeng Fan /* MPZQSWCTRL */ 486*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP (16) 487*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL (13) 488*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PD (12) 489*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL (7) 490*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL (2) 491*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_RES (1) 492*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0) 493*7bc1ca39SPeng Fan 494*7bc1ca39SPeng Fan /* MPDGCTRL0 */ 495*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_RST_RD_FIFO (31) 496*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_DG_CMP_CYC (30) 497*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_DG_DIS (29) 498*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_HW_DG_EN (28) 499*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_HW_DG_ERR (12) 500*7bc1ca39SPeng Fan 501*7bc1ca39SPeng Fan /* MPRDDLHWCTL */ 502*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC (5) 503*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN (4) 504*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0) 505*7bc1ca39SPeng Fan 506*7bc1ca39SPeng Fan /* MPWRDLHWCTL */ 507*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC (5) 508*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN (4) 509*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0) 510*7bc1ca39SPeng Fan 511*7bc1ca39SPeng Fan /* MPSWDAR */ 512*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_TEST_DUMMY_EN (6) 513*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP3 (5) 514*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP2 (4) 515*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP1 (3) 516*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP0 (2) 517*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUMMY_RD (1) 518*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUMMY_WR (0) 519*7bc1ca39SPeng Fan 520*7bc1ca39SPeng Fan /* MADPCR0 */ 521*7bc1ca39SPeng Fan #define MMDC_MADPCR0_SBS (9) 522*7bc1ca39SPeng Fan #define MMDC_MADPCR0_SBS_EN (8) 523*7bc1ca39SPeng Fan 524*7bc1ca39SPeng Fan /* MASBS1 */ 525*7bc1ca39SPeng Fan #define MMDC_MASBS1_SBS_VLD (0) 526*7bc1ca39SPeng Fan #define MMDC_MASBS1_SBS_TYPE (1) 527*7bc1ca39SPeng Fan 528*7bc1ca39SPeng Fan /* MDREF */ 529*7bc1ca39SPeng Fan #define MMDC_MDREF_REF_CNT (16) 530*7bc1ca39SPeng Fan #define MMDC_MDREF_REF_SEL (14) 531*7bc1ca39SPeng Fan #define MMDC_MDREF_REFR (11) 532*7bc1ca39SPeng Fan #define MMDC_MDREF_START_REF (0) 533*7bc1ca39SPeng Fan 534*7bc1ca39SPeng Fan /* MPWLGCR */ 535*7bc1ca39SPeng Fan #define MMDC_MPWLGCR_HW_WL_EN (0) 536*7bc1ca39SPeng Fan 537*7bc1ca39SPeng Fan /* MPBC */ 538*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DM_LP_EN (0) 539*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_CA0_LP_EN (1) 540*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ0_LP_EN (3) 541*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ1_LP_EN (4) 542*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ2_LP_EN (5) 543*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ3_LP_EN (6) 544*7bc1ca39SPeng Fan 545*7bc1ca39SPeng Fan /* MPMUR */ 546*7bc1ca39SPeng Fan #define MMDC_MPMUR_FRC_MSR (11) 547*7bc1ca39SPeng Fan 548*7bc1ca39SPeng Fan /* MPODTCTRL */ 549*7bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_RD_ACT_EN (3) 550*7bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_RD_PAS_EN (2) 551*7bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_WR_ACT_EN (1) 552*7bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0) 553*7bc1ca39SPeng Fan 554*7bc1ca39SPeng Fan /* MAPSR */ 555*7bc1ca39SPeng Fan #define MMDC_MAPSR_DVACK (25) 556*7bc1ca39SPeng Fan #define MMDC_MAPSR_LPACK (24) 557*7bc1ca39SPeng Fan #define MMDC_MAPSR_DVFS (21) 558*7bc1ca39SPeng Fan #define MMDC_MAPSR_LPMD (20) 559*7bc1ca39SPeng Fan 560*7bc1ca39SPeng Fan /* MAARCR */ 561*7bc1ca39SPeng Fan #define MMDC_MAARCR_ARCR_EXC_ERR_EN (28) 562*7bc1ca39SPeng Fan 563*7bc1ca39SPeng Fan /* MPZQLP2CTL */ 564*7bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS (24) 565*7bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL (16) 566*7bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0) 567*7bc1ca39SPeng Fan 568*7bc1ca39SPeng Fan /* MDCFG3LP */ 569*7bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRC_LP (16) 570*7bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRCD_LP (8) 571*7bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRPpb_LP (4) 572*7bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRPab_LP (0) 573*7bc1ca39SPeng Fan 574*7bc1ca39SPeng Fan /* MDOR */ 575*7bc1ca39SPeng Fan #define MMDC_MDOR_tXPR (16) 576*7bc1ca39SPeng Fan #define MMDC_MDOR_SDE_to_RST (8) 577*7bc1ca39SPeng Fan #define MMDC_MDOR_RST_to_CKE (0) 578*7bc1ca39SPeng Fan 579*7bc1ca39SPeng Fan /* MDCFG0 */ 580*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tRFC (24) 581*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tXS (16) 582*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tXP (13) 583*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tXPDLL (9) 584*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tFAW (4) 585*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tCL (0) 586*7bc1ca39SPeng Fan 587*7bc1ca39SPeng Fan /* MDCFG1 */ 588*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tRCD (29) 589*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tRP (26) 590*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tRC (21) 591*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tRAS (16) 592*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tRPA (15) 593*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tWR (9) 594*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tMRD (5) 595*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tCWL (0) 596*7bc1ca39SPeng Fan 597*7bc1ca39SPeng Fan /* MDCFG2 */ 598*7bc1ca39SPeng Fan #define MMDC_MDCFG2_tDLLK (16) 599*7bc1ca39SPeng Fan #define MMDC_MDCFG2_tRTP (6) 600*7bc1ca39SPeng Fan #define MMDC_MDCFG2_tWTR (3) 601*7bc1ca39SPeng Fan #define MMDC_MDCFG2_tRRD (0) 602*7bc1ca39SPeng Fan 603*7bc1ca39SPeng Fan /* MDRWD */ 604*7bc1ca39SPeng Fan #define MMDC_MDRWD_tDAI (16) 605*7bc1ca39SPeng Fan #define MMDC_MDRWD_RTW_SAME (12) 606*7bc1ca39SPeng Fan #define MMDC_MDRWD_WTR_DIFF (9) 607*7bc1ca39SPeng Fan #define MMDC_MDRWD_WTW_DIFF (6) 608*7bc1ca39SPeng Fan #define MMDC_MDRWD_RTW_DIFF (3) 609*7bc1ca39SPeng Fan #define MMDC_MDRWD_RTR_DIFF (0) 610*7bc1ca39SPeng Fan 611*7bc1ca39SPeng Fan /* MDPDC */ 612*7bc1ca39SPeng Fan #define MMDC_MDPDC_PRCT_1 (28) 613*7bc1ca39SPeng Fan #define MMDC_MDPDC_PRCT_0 (24) 614*7bc1ca39SPeng Fan #define MMDC_MDPDC_tCKE (16) 615*7bc1ca39SPeng Fan #define MMDC_MDPDC_PWDT_1 (12) 616*7bc1ca39SPeng Fan #define MMDC_MDPDC_PWDT_0 (8) 617*7bc1ca39SPeng Fan #define MMDC_MDPDC_SLOW_PD (7) 618*7bc1ca39SPeng Fan #define MMDC_MDPDC_BOTH_CS_PD (6) 619*7bc1ca39SPeng Fan #define MMDC_MDPDC_tCKSRX (3) 620*7bc1ca39SPeng Fan #define MMDC_MDPDC_tCKSRE (0) 621*7bc1ca39SPeng Fan 622*7bc1ca39SPeng Fan /* MDASP */ 623*7bc1ca39SPeng Fan #define MMDC_MDASP_CS0_END (0) 624*7bc1ca39SPeng Fan 625*7bc1ca39SPeng Fan /* MAEXIDR0 */ 626*7bc1ca39SPeng Fan #define MMDC_MAEXIDR0_EXC_ID_MONITOR1 (16) 627*7bc1ca39SPeng Fan #define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0) 628*7bc1ca39SPeng Fan 629*7bc1ca39SPeng Fan /* MAEXIDR1 */ 630*7bc1ca39SPeng Fan #define MMDC_MAEXIDR1_EXC_ID_MONITOR3 (16) 631*7bc1ca39SPeng Fan #define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0) 632*7bc1ca39SPeng Fan 633*7bc1ca39SPeng Fan /* MPWRDLCTL */ 634*7bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3 (24) 635*7bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2 (16) 636*7bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1 (8) 637*7bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0) 638*7bc1ca39SPeng Fan 639*7bc1ca39SPeng Fan /* MPRDDLCTL */ 640*7bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3 (24) 641*7bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2 (16) 642*7bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1 (8) 643*7bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0) 644*7bc1ca39SPeng Fan 645*7bc1ca39SPeng Fan /* MPWRDQBY0DL */ 646*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DM0_DEL (30) 647*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL (28) 648*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL (24) 649*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL (20) 650*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL (16) 651*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL (12) 652*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL (8) 653*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL (4) 654*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0) 655*7bc1ca39SPeng Fan 656*7bc1ca39SPeng Fan /* MPWRDQBY1DL */ 657*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DM1_DEL (30) 658*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL (28) 659*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL (24) 660*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL (20) 661*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL (16) 662*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL (12) 663*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL (8) 664*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL (4) 665*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0) 666*7bc1ca39SPeng Fan 667*7bc1ca39SPeng Fan /* MPWRDQBY2DL */ 668*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DM2_DEL (30) 669*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL (28) 670*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL (24) 671*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL (20) 672*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL (16) 673*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL (12) 674*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL (8) 675*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL (4) 676*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0) 677*7bc1ca39SPeng Fan 678*7bc1ca39SPeng Fan /* MPWRDQBY3DL */ 679*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DM3_DEL (30) 680*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL (28) 681*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL (24) 682*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL (20) 683*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL (16) 684*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL (12) 685*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL (8) 686*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL (4) 687*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0) 688*7bc1ca39SPeng Fan 689*7bc1ca39SPeng Fan /* Fields masks */ 690*7bc1ca39SPeng Fan #define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0)) 691*7bc1ca39SPeng Fan #define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1)) 692*7bc1ca39SPeng Fan #define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL)) 693*7bc1ca39SPeng Fan #define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW)) 694*7bc1ca39SPeng Fan #define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL)) 695*7bc1ca39SPeng Fan #define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ)) 696*7bc1ca39SPeng Fan 697*7bc1ca39SPeng Fan /* MDMISC */ 698*7bc1ca39SPeng Fan #define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY)) 699*7bc1ca39SPeng Fan #define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY)) 700*7bc1ca39SPeng Fan #define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL)) 701*7bc1ca39SPeng Fan #define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING)) 702*7bc1ca39SPeng Fan #define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS)) 703*7bc1ca39SPeng Fan #define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR)) 704*7bc1ca39SPeng Fan #define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD)) 705*7bc1ca39SPeng Fan #define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT)) 706*7bc1ca39SPeng Fan #define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI)) 707*7bc1ca39SPeng Fan #define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S)) 708*7bc1ca39SPeng Fan #define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE)) 709*7bc1ca39SPeng Fan #define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT)) 710*7bc1ca39SPeng Fan #define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK)) 711*7bc1ca39SPeng Fan #define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE)) 712*7bc1ca39SPeng Fan #define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST)) 713*7bc1ca39SPeng Fan 714*7bc1ca39SPeng Fan /* MPWLGCR */ 715*7bc1ca39SPeng Fan #define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR)) 716*7bc1ca39SPeng Fan 717*7bc1ca39SPeng Fan /* MDSCR */ 718*7bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB)) 719*7bc1ca39SPeng Fan #define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP)) 720*7bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB)) 721*7bc1ca39SPeng Fan #define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR)) 722*7bc1ca39SPeng Fan #define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ)) 723*7bc1ca39SPeng Fan #define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK)) 724*7bc1ca39SPeng Fan #define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID)) 725*7bc1ca39SPeng Fan #define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN)) 726*7bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD)) 727*7bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS)) 728*7bc1ca39SPeng Fan #define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA)) 729*7bc1ca39SPeng Fan 730*7bc1ca39SPeng Fan /* MPZQHWCTRL */ 731*7bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR)) 732*7bc1ca39SPeng Fan #define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE)) 733*7bc1ca39SPeng Fan 734*7bc1ca39SPeng Fan /* MPZQSWCTRL */ 735*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP)) 736*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL)) 737*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD)) 738*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL)) 739*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL)) 740*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES)) 741*7bc1ca39SPeng Fan #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR)) 742*7bc1ca39SPeng Fan 743*7bc1ca39SPeng Fan /* MPDGCTRL0 */ 744*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO)) 745*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC)) 746*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS)) 747*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN)) 748*7bc1ca39SPeng Fan #define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR)) 749*7bc1ca39SPeng Fan 750*7bc1ca39SPeng Fan /* MPRDDLHWCTL */ 751*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC)) 752*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN)) 753*7bc1ca39SPeng Fan #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR)) 754*7bc1ca39SPeng Fan 755*7bc1ca39SPeng Fan /* MPWRDLHWCTL */ 756*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC)) 757*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN)) 758*7bc1ca39SPeng Fan #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR)) 759*7bc1ca39SPeng Fan 760*7bc1ca39SPeng Fan /* MPSWDAR */ 761*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN)) 762*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3)) 763*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2)) 764*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1)) 765*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0)) 766*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD)) 767*7bc1ca39SPeng Fan #define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR)) 768*7bc1ca39SPeng Fan 769*7bc1ca39SPeng Fan /* MADPCR0 */ 770*7bc1ca39SPeng Fan #define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS)) 771*7bc1ca39SPeng Fan #define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN)) 772*7bc1ca39SPeng Fan 773*7bc1ca39SPeng Fan /* MASBS1 */ 774*7bc1ca39SPeng Fan #define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD)) 775*7bc1ca39SPeng Fan #define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE)) 776*7bc1ca39SPeng Fan 777*7bc1ca39SPeng Fan /* MDREF */ 778*7bc1ca39SPeng Fan #define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT)) 779*7bc1ca39SPeng Fan #define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL)) 780*7bc1ca39SPeng Fan #define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR)) 781*7bc1ca39SPeng Fan #define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF)) 782*7bc1ca39SPeng Fan 783*7bc1ca39SPeng Fan /* MPWLGCR */ 784*7bc1ca39SPeng Fan #define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN)) 785*7bc1ca39SPeng Fan 786*7bc1ca39SPeng Fan /* MPBC */ 787*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN)) 788*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN)) 789*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN)) 790*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN)) 791*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN)) 792*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN)) 793*7bc1ca39SPeng Fan #define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN)) 794*7bc1ca39SPeng Fan 795*7bc1ca39SPeng Fan /* MPMUR */ 796*7bc1ca39SPeng Fan #define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR)) 797*7bc1ca39SPeng Fan 798*7bc1ca39SPeng Fan /* MPODTCTRL */ 799*7bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN)) 800*7bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN)) 801*7bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN)) 802*7bc1ca39SPeng Fan #define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN)) 803*7bc1ca39SPeng Fan 804*7bc1ca39SPeng Fan /* MAPSR */ 805*7bc1ca39SPeng Fan #define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK)) 806*7bc1ca39SPeng Fan #define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK)) 807*7bc1ca39SPeng Fan #define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS)) 808*7bc1ca39SPeng Fan #define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD)) 809*7bc1ca39SPeng Fan 810*7bc1ca39SPeng Fan /* MAARCR */ 811*7bc1ca39SPeng Fan #define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN)) 812*7bc1ca39SPeng Fan 813*7bc1ca39SPeng Fan /* MPZQLP2CTL */ 814*7bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS)) 815*7bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL)) 816*7bc1ca39SPeng Fan #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT)) 817*7bc1ca39SPeng Fan 818*7bc1ca39SPeng Fan /* MDCFG3LP */ 819*7bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP)) 820*7bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP)) 821*7bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP)) 822*7bc1ca39SPeng Fan #define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP)) 823*7bc1ca39SPeng Fan 824*7bc1ca39SPeng Fan /* MDOR */ 825*7bc1ca39SPeng Fan #define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR)) 826*7bc1ca39SPeng Fan #define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST)) 827*7bc1ca39SPeng Fan #define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE)) 828*7bc1ca39SPeng Fan 829*7bc1ca39SPeng Fan /* MDCFG0 */ 830*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC)) 831*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS)) 832*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP)) 833*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL)) 834*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW)) 835*7bc1ca39SPeng Fan #define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL)) 836*7bc1ca39SPeng Fan 837*7bc1ca39SPeng Fan /* MDCFG1 */ 838*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD)) 839*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP)) 840*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC)) 841*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS)) 842*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA)) 843*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR)) 844*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD)) 845*7bc1ca39SPeng Fan #define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL)) 846*7bc1ca39SPeng Fan 847*7bc1ca39SPeng Fan /* MDCFG2 */ 848*7bc1ca39SPeng Fan #define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK)) 849*7bc1ca39SPeng Fan #define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP)) 850*7bc1ca39SPeng Fan #define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR)) 851*7bc1ca39SPeng Fan #define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD)) 852*7bc1ca39SPeng Fan 853*7bc1ca39SPeng Fan /* MDRWD */ 854*7bc1ca39SPeng Fan #define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI)) 855*7bc1ca39SPeng Fan #define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME)) 856*7bc1ca39SPeng Fan #define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF)) 857*7bc1ca39SPeng Fan #define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF)) 858*7bc1ca39SPeng Fan #define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF)) 859*7bc1ca39SPeng Fan #define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF)) 860*7bc1ca39SPeng Fan 861*7bc1ca39SPeng Fan /* MDPDC */ 862*7bc1ca39SPeng Fan #define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1)) 863*7bc1ca39SPeng Fan #define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0)) 864*7bc1ca39SPeng Fan #define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE)) 865*7bc1ca39SPeng Fan #define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1)) 866*7bc1ca39SPeng Fan #define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0)) 867*7bc1ca39SPeng Fan #define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD)) 868*7bc1ca39SPeng Fan #define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD)) 869*7bc1ca39SPeng Fan #define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX)) 870*7bc1ca39SPeng Fan #define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE)) 871*7bc1ca39SPeng Fan 872*7bc1ca39SPeng Fan /* MDASP */ 873*7bc1ca39SPeng Fan #define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END)) 874*7bc1ca39SPeng Fan 875*7bc1ca39SPeng Fan /* MAEXIDR0 */ 876*7bc1ca39SPeng Fan #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1)) 877*7bc1ca39SPeng Fan #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0)) 878*7bc1ca39SPeng Fan 879*7bc1ca39SPeng Fan /* MAEXIDR1 */ 880*7bc1ca39SPeng Fan #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3)) 881*7bc1ca39SPeng Fan #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2)) 882*7bc1ca39SPeng Fan 883*7bc1ca39SPeng Fan /* MPWRDLCTL */ 884*7bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3)) 885*7bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2)) 886*7bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1)) 887*7bc1ca39SPeng Fan #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0)) 888*7bc1ca39SPeng Fan 889*7bc1ca39SPeng Fan /* MPRDDLCTL */ 890*7bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3)) 891*7bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2)) 892*7bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1)) 893*7bc1ca39SPeng Fan #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0)) 894*7bc1ca39SPeng Fan 895*7bc1ca39SPeng Fan /* MPWRDQBY0DL */ 896*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL)) 897*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL)) 898*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL)) 899*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL)) 900*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL)) 901*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL)) 902*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL)) 903*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL)) 904*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL)) 905*7bc1ca39SPeng Fan 906*7bc1ca39SPeng Fan /* MPWRDQBY1DL */ 907*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL)) 908*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL)) 909*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL)) 910*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL)) 911*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL)) 912*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL)) 913*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL)) 914*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL)) 915*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL)) 916*7bc1ca39SPeng Fan 917*7bc1ca39SPeng Fan /* MPWRDQBY2DL */ 918*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL)) 919*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL)) 920*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL)) 921*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL)) 922*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL)) 923*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL)) 924*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL)) 925*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL)) 926*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL)) 927*7bc1ca39SPeng Fan 928*7bc1ca39SPeng Fan /* MPWRDQBY3DL */ 929*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL)) 930*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL)) 931*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL)) 932*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL)) 933*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL)) 934*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL)) 935*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL)) 936*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) 937*7bc1ca39SPeng Fan #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) 938*7bc1ca39SPeng Fan 939*7bc1ca39SPeng Fan #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 940*7bc1ca39SPeng Fan 941*7bc1ca39SPeng Fan #include <asm/types.h> 942*7bc1ca39SPeng Fan 943*7bc1ca39SPeng Fan struct fuse_word { 944*7bc1ca39SPeng Fan u32 fuse; 945*7bc1ca39SPeng Fan u32 rsvd[3]; 946*7bc1ca39SPeng Fan }; 947*7bc1ca39SPeng Fan 948*7bc1ca39SPeng Fan struct ocotp_regs { 949*7bc1ca39SPeng Fan u32 ctrl; 950*7bc1ca39SPeng Fan u32 ctrl_set; 951*7bc1ca39SPeng Fan u32 ctrl_clr; 952*7bc1ca39SPeng Fan u32 ctrl_tog; 953*7bc1ca39SPeng Fan u32 pdn; 954*7bc1ca39SPeng Fan u32 rsvd0[3]; 955*7bc1ca39SPeng Fan u32 data; 956*7bc1ca39SPeng Fan u32 rsvd1[3]; 957*7bc1ca39SPeng Fan u32 read_ctrl; 958*7bc1ca39SPeng Fan u32 rsvd2[3]; 959*7bc1ca39SPeng Fan u32 read_fuse_data; 960*7bc1ca39SPeng Fan u32 rsvd3[3]; 961*7bc1ca39SPeng Fan u32 sw_sticky; 962*7bc1ca39SPeng Fan u32 rsvd4[3]; 963*7bc1ca39SPeng Fan u32 scs; 964*7bc1ca39SPeng Fan u32 scs_set; 965*7bc1ca39SPeng Fan u32 scs_clr; 966*7bc1ca39SPeng Fan u32 scs_tog; 967*7bc1ca39SPeng Fan u32 out_status; 968*7bc1ca39SPeng Fan u32 out_status_set; 969*7bc1ca39SPeng Fan u32 out_status_clr; 970*7bc1ca39SPeng Fan u32 out_status_tog; 971*7bc1ca39SPeng Fan u32 startword; 972*7bc1ca39SPeng Fan u32 rsvd5[3]; 973*7bc1ca39SPeng Fan u32 version; 974*7bc1ca39SPeng Fan u32 rsvd6[19]; 975*7bc1ca39SPeng Fan struct fuse_word mem_repair[8]; 976*7bc1ca39SPeng Fan u32 rsvd7[0xa8]; 977*7bc1ca39SPeng Fan 978*7bc1ca39SPeng Fan /* fuse banks */ 979*7bc1ca39SPeng Fan struct fuse_bank { 980*7bc1ca39SPeng Fan u32 fuse_regs[0x20]; 981*7bc1ca39SPeng Fan } bank[0]; 982*7bc1ca39SPeng Fan }; 983*7bc1ca39SPeng Fan 984*7bc1ca39SPeng Fan struct fuse_bank1_regs { 985*7bc1ca39SPeng Fan u32 lock0; 986*7bc1ca39SPeng Fan u32 rsvd0[3]; 987*7bc1ca39SPeng Fan u32 lock1; 988*7bc1ca39SPeng Fan u32 rsvd1[3]; 989*7bc1ca39SPeng Fan u32 lock2; 990*7bc1ca39SPeng Fan u32 rsvd2[3]; 991*7bc1ca39SPeng Fan u32 cfg0; 992*7bc1ca39SPeng Fan u32 rsvd3[3]; 993*7bc1ca39SPeng Fan u32 cfg1; 994*7bc1ca39SPeng Fan u32 rsvd4[3]; 995*7bc1ca39SPeng Fan u32 cfg2; 996*7bc1ca39SPeng Fan u32 rsvd5[3]; 997*7bc1ca39SPeng Fan u32 cfg3; 998*7bc1ca39SPeng Fan u32 rsvd6[3]; 999*7bc1ca39SPeng Fan u32 cfg4; 1000*7bc1ca39SPeng Fan u32 rsvd7[3]; 1001*7bc1ca39SPeng Fan }; 1002*7bc1ca39SPeng Fan 1003*7bc1ca39SPeng Fan struct fuse_bank2_regs { 1004*7bc1ca39SPeng Fan struct fuse_word boot[8]; 1005*7bc1ca39SPeng Fan }; 1006*7bc1ca39SPeng Fan 1007*7bc1ca39SPeng Fan struct fuse_bank3_regs { 1008*7bc1ca39SPeng Fan u32 mem0; 1009*7bc1ca39SPeng Fan u32 rsvd0[3]; 1010*7bc1ca39SPeng Fan u32 mem1; 1011*7bc1ca39SPeng Fan u32 rsvd1[3]; 1012*7bc1ca39SPeng Fan u32 mem2; 1013*7bc1ca39SPeng Fan u32 rsvd2[3]; 1014*7bc1ca39SPeng Fan u32 mem3; 1015*7bc1ca39SPeng Fan u32 rsvd3[3]; 1016*7bc1ca39SPeng Fan u32 ana0; 1017*7bc1ca39SPeng Fan u32 rsvd4[3]; 1018*7bc1ca39SPeng Fan u32 ana1; 1019*7bc1ca39SPeng Fan u32 rsvd5[3]; 1020*7bc1ca39SPeng Fan u32 ana2; 1021*7bc1ca39SPeng Fan u32 rsvd6[3]; 1022*7bc1ca39SPeng Fan u32 ana3; 1023*7bc1ca39SPeng Fan u32 rsvd7[3]; 1024*7bc1ca39SPeng Fan }; 1025*7bc1ca39SPeng Fan 1026*7bc1ca39SPeng Fan struct fuse_bank7_regs { 1027*7bc1ca39SPeng Fan u32 sjc_resp0; 1028*7bc1ca39SPeng Fan u32 rsvd0[3]; 1029*7bc1ca39SPeng Fan u32 sjc_resp1; 1030*7bc1ca39SPeng Fan u32 rsvd1[3]; 1031*7bc1ca39SPeng Fan u32 gp0; 1032*7bc1ca39SPeng Fan u32 rsvd2[3]; 1033*7bc1ca39SPeng Fan u32 gp1; 1034*7bc1ca39SPeng Fan u32 rsvd3[3]; 1035*7bc1ca39SPeng Fan u32 gp2; 1036*7bc1ca39SPeng Fan u32 rsvd4[3]; 1037*7bc1ca39SPeng Fan u32 gp3; 1038*7bc1ca39SPeng Fan u32 rsvd5[3]; 1039*7bc1ca39SPeng Fan u32 gp4; 1040*7bc1ca39SPeng Fan u32 rsvd6[3]; 1041*7bc1ca39SPeng Fan u32 gp5; 1042*7bc1ca39SPeng Fan u32 rsvd7[3]; 1043*7bc1ca39SPeng Fan }; 1044*7bc1ca39SPeng Fan 1045*7bc1ca39SPeng Fan struct usbphy_regs { 1046*7bc1ca39SPeng Fan u32 usbphy_pwd; /* 0x000 */ 1047*7bc1ca39SPeng Fan u32 usbphy_pwd_set; /* 0x004 */ 1048*7bc1ca39SPeng Fan u32 usbphy_pwd_clr; /* 0x008 */ 1049*7bc1ca39SPeng Fan u32 usbphy_pwd_tog; /* 0x00c */ 1050*7bc1ca39SPeng Fan u32 usbphy_tx; /* 0x010 */ 1051*7bc1ca39SPeng Fan u32 usbphy_tx_set; /* 0x014 */ 1052*7bc1ca39SPeng Fan u32 usbphy_tx_clr; /* 0x018 */ 1053*7bc1ca39SPeng Fan u32 usbphy_tx_tog; /* 0x01c */ 1054*7bc1ca39SPeng Fan u32 usbphy_rx; /* 0x020 */ 1055*7bc1ca39SPeng Fan u32 usbphy_rx_set; /* 0x024 */ 1056*7bc1ca39SPeng Fan u32 usbphy_rx_clr; /* 0x028 */ 1057*7bc1ca39SPeng Fan u32 usbphy_rx_tog; /* 0x02c */ 1058*7bc1ca39SPeng Fan u32 usbphy_ctrl; /* 0x030 */ 1059*7bc1ca39SPeng Fan u32 usbphy_ctrl_set; /* 0x034 */ 1060*7bc1ca39SPeng Fan u32 usbphy_ctrl_clr; /* 0x038 */ 1061*7bc1ca39SPeng Fan u32 usbphy_ctrl_tog; /* 0x03c */ 1062*7bc1ca39SPeng Fan u32 usbphy_status; /* 0x040 */ 1063*7bc1ca39SPeng Fan u32 reserved0[3]; 1064*7bc1ca39SPeng Fan u32 usbphy_debug0; /* 0x050 */ 1065*7bc1ca39SPeng Fan u32 usbphy_debug0_set; /* 0x054 */ 1066*7bc1ca39SPeng Fan u32 usbphy_debug0_clr; /* 0x058 */ 1067*7bc1ca39SPeng Fan u32 usbphy_debug0_tog; /* 0x05c */ 1068*7bc1ca39SPeng Fan u32 reserved1[4]; 1069*7bc1ca39SPeng Fan u32 usbphy_debug1; /* 0x070 */ 1070*7bc1ca39SPeng Fan u32 usbphy_debug1_set; /* 0x074 */ 1071*7bc1ca39SPeng Fan u32 usbphy_debug1_clr; /* 0x078 */ 1072*7bc1ca39SPeng Fan u32 usbphy_debug1_tog; /* 0x07c */ 1073*7bc1ca39SPeng Fan u32 usbphy_version; /* 0x080 */ 1074*7bc1ca39SPeng Fan u32 reserved2[7]; 1075*7bc1ca39SPeng Fan u32 usb1_pll_480_ctrl; /* 0x0a0 */ 1076*7bc1ca39SPeng Fan u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ 1077*7bc1ca39SPeng Fan u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ 1078*7bc1ca39SPeng Fan u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ 1079*7bc1ca39SPeng Fan u32 reserved3[4]; 1080*7bc1ca39SPeng Fan u32 usb1_vbus_detect; /* 0xc0 */ 1081*7bc1ca39SPeng Fan u32 usb1_vbus_detect_set; /* 0xc4 */ 1082*7bc1ca39SPeng Fan u32 usb1_vbus_detect_clr; /* 0xc8 */ 1083*7bc1ca39SPeng Fan u32 usb1_vbus_detect_tog; /* 0xcc */ 1084*7bc1ca39SPeng Fan u32 usb1_vbus_det_stat; /* 0xd0 */ 1085*7bc1ca39SPeng Fan u32 reserved4[3]; 1086*7bc1ca39SPeng Fan u32 usb1_chrg_detect; /* 0xe0 */ 1087*7bc1ca39SPeng Fan u32 usb1_chrg_detect_set; /* 0xe4 */ 1088*7bc1ca39SPeng Fan u32 usb1_chrg_detect_clr; /* 0xe8 */ 1089*7bc1ca39SPeng Fan u32 usb1_chrg_detect_tog; /* 0xec */ 1090*7bc1ca39SPeng Fan u32 usb1_chrg_det_stat; /* 0xf0 */ 1091*7bc1ca39SPeng Fan u32 reserved5[3]; 1092*7bc1ca39SPeng Fan u32 usbphy_anactrl; /* 0x100 */ 1093*7bc1ca39SPeng Fan u32 usbphy_anactrl_set; /* 0x104 */ 1094*7bc1ca39SPeng Fan u32 usbphy_anactrl_clr; /* 0x108 */ 1095*7bc1ca39SPeng Fan u32 usbphy_anactrl_tog; /* 0x10c */ 1096*7bc1ca39SPeng Fan u32 usb1_loopback; /* 0x110 */ 1097*7bc1ca39SPeng Fan u32 usb1_loopback_set; /* 0x114 */ 1098*7bc1ca39SPeng Fan u32 usb1_loopback_clr; /* 0x118 */ 1099*7bc1ca39SPeng Fan u32 usb1_loopback_tog; /* 0x11c */ 1100*7bc1ca39SPeng Fan u32 usb1_loopback_hsfscnt; /* 0x120 */ 1101*7bc1ca39SPeng Fan u32 usb1_loopback_hsfscnt_set; /* 0x124 */ 1102*7bc1ca39SPeng Fan u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ 1103*7bc1ca39SPeng Fan u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ 1104*7bc1ca39SPeng Fan u32 usphy_trim_override_en; /* 0x130 */ 1105*7bc1ca39SPeng Fan u32 usphy_trim_override_en_set; /* 0x134 */ 1106*7bc1ca39SPeng Fan u32 usphy_trim_override_en_clr; /* 0x138 */ 1107*7bc1ca39SPeng Fan u32 usphy_trim_override_en_tog; /* 0x13c */ 1108*7bc1ca39SPeng Fan u32 usb1_pfda_ctrl1; /* 0x140 */ 1109*7bc1ca39SPeng Fan u32 usb1_pfda_ctrl1_set; /* 0x144 */ 1110*7bc1ca39SPeng Fan u32 usb1_pfda_ctrl1_clr; /* 0x148 */ 1111*7bc1ca39SPeng Fan u32 usb1_pfda_ctrl1_tog; /* 0x14c */ 1112*7bc1ca39SPeng Fan }; 1113*7bc1ca39SPeng Fan 1114*7bc1ca39SPeng Fan 1115*7bc1ca39SPeng Fan #define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) 1116*7bc1ca39SPeng Fan #define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) 1117*7bc1ca39SPeng Fan 1118*7bc1ca39SPeng Fan #endif 1119*7bc1ca39SPeng Fan 1120*7bc1ca39SPeng Fan #endif /* _MX7ULP_REGS_H_*/ 1121