1 /*
2  * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ASM_ARCH_MX7_IMX_REGS_H__
8 #define __ASM_ARCH_MX7_IMX_REGS_H__
9 
10 #define ARCH_MXC
11 
12 #define ROM_SW_INFO_ADDR                0x000001E8
13 #define ROMCP_ARB_BASE_ADDR             0x00000000
14 #define ROMCP_ARB_END_ADDR              0x00017FFF
15 #define BOOT_ROM_BASE_ADDR              ROMCP_ARB_BASE_ADDR
16 #define CAAM_ARB_BASE_ADDR              0x00100000
17 #define CAAM_ARB_END_ADDR               0x00107FFF
18 #define GIC400_ARB_BASE_ADDR            0x31000000
19 #define GIC400_ARB_END_ADDR             0x31007FFF
20 #define APBH_DMA_ARB_BASE_ADDR          0x33000000
21 #define APBH_DMA_ARB_END_ADDR           0x33007FFF
22 #define M4_BOOTROM_BASE_ADDR            0x00180000
23 
24 #define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
25 #define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
26 #define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
27 
28 /* GPV - PL301 configuration ports */
29 #define GPV0_BASE_ADDR                  0x32000000
30 #define GPV1_BASE_ADDR                  0x32100000
31 #define GPV2_BASE_ADDR                  0x32200000
32 #define GPV3_BASE_ADDR                  0x32300000
33 #define GPV4_BASE_ADDR                  0x32400000
34 #define GPV5_BASE_ADDR                  0x32500000
35 #define GPV6_BASE_ADDR                  0x32600000
36 #define GPV7_BASE_ADDR                  0x32700000
37 
38 #define OCRAM_ARB_BASE_ADDR             0x00900000
39 #define OCRAM_ARB_END_ADDR              0x0091FFFF
40 #define OCRAM_EPDC_BASE_ADDR            0x00920000
41 #define OCRAM_EPDC_END_ADDR             0x0093FFFF
42 #define OCRAM_PXP_BASE_ADDR             0x00940000
43 #define OCRAM_PXP_END_ADDR              0x00947FFF
44 #define IRAM_BASE_ADDR                  OCRAM_ARB_BASE_ADDR
45 #define IRAM_SIZE			0x00020000
46 
47 #define AIPS1_ARB_BASE_ADDR             0x30000000
48 #define AIPS1_ARB_END_ADDR              0x303FFFFF
49 #define AIPS2_ARB_BASE_ADDR             0x30400000
50 #define AIPS2_ARB_END_ADDR              0x307FFFFF
51 #define AIPS3_ARB_BASE_ADDR             0x30800000
52 #define AIPS3_ARB_END_ADDR              0x30BFFFFF
53 
54 #define WEIM_ARB_BASE_ADDR              0x28000000
55 #define WEIM_ARB_END_ADDR               0x2FFFFFFF
56 
57 #define QSPI0_ARB_BASE_ADDR             0x60000000
58 #define QSPI0_ARB_END_ADDR              0x6FFFFFFF
59 #define PCIE_ARB_BASE_ADDR              0x40000000
60 #define PCIE_ARB_END_ADDR               0x4FFFFFFF
61 #define PCIE_REG_BASE_ADDR              0x33800000
62 #define PCIE_REG_END_ADDR               0x33803FFF
63 
64 #define MMDC0_ARB_BASE_ADDR             0x80000000
65 #define MMDC0_ARB_END_ADDR              0xBFFFFFFF
66 #define MMDC1_ARB_BASE_ADDR             0xC0000000
67 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
68 
69 /* Cortex-A9 MPCore private memory region */
70 #define ARM_PERIPHBASE                  0x31000000
71 #define SCU_BASE_ADDR                   ARM_PERIPHBASE
72 #define GLOBAL_TIMER_BASE_ADDR          (ARM_PERIPHBASE + 0x0200)
73 #define PRIVATE_TIMERS_WD_BASE_ADDR     (ARM_PERIPHBASE + 0x0600)
74 
75 
76 /* Defines for Blocks connected via AIPS (SkyBlue) */
77 #define AIPS_TZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
78 #define AIPS_TZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
79 #define AIPS_TZ3_BASE_ADDR              AIPS3_ARB_BASE_ADDR
80 
81 /* DAP base-address */
82 #define ARM_IPS_BASE_ADDR               AIPS1_ARB_BASE_ADDR
83 
84 /* AIPS_TZ#1- On Platform */
85 #define AIPS1_ON_BASE_ADDR              (AIPS_TZ1_BASE_ADDR+0x1F0000)
86 /* AIPS_TZ#1- Off Platform */
87 #define AIPS1_OFF_BASE_ADDR             (AIPS_TZ1_BASE_ADDR+0x200000)
88 
89 #define GPIO1_BASE_ADDR                 AIPS1_OFF_BASE_ADDR
90 #define GPIO2_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x10000)
91 #define GPIO3_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x20000)
92 #define GPIO4_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x30000)
93 #define GPIO5_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x40000)
94 #define GPIO6_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x50000)
95 #define GPIO7_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x60000)
96 #define IOMUXC_LPSR_GPR_BASE_ADDR      (AIPS1_OFF_BASE_ADDR+0x70000)
97 #define WDOG1_BASE_ADDR                (AIPS1_OFF_BASE_ADDR+0x80000)
98 #define WDOG2_BASE_ADDR                (AIPS1_OFF_BASE_ADDR+0x90000)
99 #define WDOG3_BASE_ADDR                (AIPS1_OFF_BASE_ADDR+0xA0000)
100 #define WDOG4_BASE_ADDR                (AIPS1_OFF_BASE_ADDR+0xB0000)
101 #define IOMUXC_LPSR_BASE_ADDR          (AIPS1_OFF_BASE_ADDR+0xC0000)
102 #define GPT_IPS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR+0xD0000)
103 #define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR
104 #define GPT2_IPS_BASE_ADDR             (AIPS1_OFF_BASE_ADDR+0xE0000)
105 #define GPT3_IPS_BASE_ADDR             (AIPS1_OFF_BASE_ADDR+0xF0000)
106 #define GPT4_IPS_BASE_ADDR             (AIPS1_OFF_BASE_ADDR+0x100000)
107 #define ROMCP_IPS_BASE_ADDR            (AIPS1_OFF_BASE_ADDR+0x110000)
108 #define KPP_IPS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR+0x120000)
109 #define IOMUXC_IPS_BASE_ADDR           (AIPS1_OFF_BASE_ADDR+0x130000)
110 #define IOMUXC_BASE_ADDR               IOMUXC_IPS_BASE_ADDR
111 #define IOMUXC_GPR_BASE_ADDR           (AIPS1_OFF_BASE_ADDR+0x140000)
112 #define OCOTP_BASE_ADDR                (AIPS1_OFF_BASE_ADDR+0x150000)
113 #define ANATOP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR+0x160000)
114 #define SNVS_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x170000)
115 #define CCM_BASE_ADDR                  (AIPS1_OFF_BASE_ADDR+0x180000)
116 #define SRC_BASE_ADDR                  (AIPS1_OFF_BASE_ADDR+0x190000)
117 #define GPC_IPS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR+0x1A0000)
118 #define SEMA41_IPS_BASE_ADDR           (AIPS1_OFF_BASE_ADDR+0x1B0000)
119 #define SEMA42_IPS_BASE_ADDR           (AIPS1_OFF_BASE_ADDR+0x1C0000)
120 #define RDC_IPS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR+0x1D0000)
121 #define CSU_IPS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR+0x1E0000)
122 
123 /* AIPS_TZ#2- On Platform */
124 #define AIPS2_ON_BASE_ADDR              (AIPS_TZ2_BASE_ADDR+0x1F0000)
125 /* AIPS_TZ#2- Off Platform */
126 #define AIPS2_OFF_BASE_ADDR             (AIPS_TZ2_BASE_ADDR+0x200000)
127 #define ADC1_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x10000)
128 #define ADC2_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x20000)
129 #define ECSPI4_BASE_ADDR                (AIPS2_OFF_BASE_ADDR+0x30000)
130 #define FTM1_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x40000)
131 #define FTM2_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x50000)
132 #define PWM1_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x60000)
133 #define PWM2_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x70000)
134 #define PWM3_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x80000)
135 #define PWM4_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x90000)
136 #define SYSCNT_RD_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR+0xA0000)
137 #define SYSCNT_CMP_IPS_BASE_ADDR        (AIPS2_OFF_BASE_ADDR+0xB0000)
138 #define SYSCNT_CTRL_IPS_BASE_ADDR       (AIPS2_OFF_BASE_ADDR+0xC0000)
139 #define PCIE_PHY_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR+0xD0000)
140 #define EPDC_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0xF0000)
141 #define EPDC_BASE_ADDR                  EPDC_IPS_BASE_ADDR
142 #define EPXP_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x100000)
143 #define CSI1_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x110000)
144 #define ELCDIF1_IPS_BASE_ADDR           (AIPS2_OFF_BASE_ADDR+0x130000)
145 #define MIPI_CSI2_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR+0x150000)
146 #define MIPI_DSI_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR+0x160000)
147 #define IP2APB_TZASC1_IPS_BASE_ADDR     (AIPS2_OFF_BASE_ADDR+0x180000)
148 #define DDRPHY_IPS_BASE_ADDR            (AIPS2_OFF_BASE_ADDR+0x190000)
149 #define DDRC_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x1A0000)
150 #define IP2APB_PERFMON1_IPS_BASE_ADDR   (AIPS2_OFF_BASE_ADDR+0x1C0000)
151 #define IP2APB_PERFMON2_IPS_BASE_ADDR   (AIPS2_OFF_BASE_ADDR+0x1D0000)
152 #define IP2APB_AXIMON_IPS_BASE_ADDR     (AIPS2_OFF_BASE_ADDR+0x1E0000)
153 #define QOSC_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x1F0000)
154 
155 /* AIPS_TZ#3  - Global enable (0) */
156 #define ECSPI1_BASE_ADDR                (AIPS_TZ3_BASE_ADDR+0x20000)
157 #define ECSPI2_BASE_ADDR                (AIPS_TZ3_BASE_ADDR+0x30000)
158 #define ECSPI3_BASE_ADDR                (AIPS_TZ3_BASE_ADDR+0x40000)
159 #define UART1_IPS_BASE_ADDR             (AIPS_TZ3_BASE_ADDR+0x60000)
160 #define UART3_IPS_BASE_ADDR             (AIPS_TZ3_BASE_ADDR+0x80000)
161 #define UART2_IPS_BASE_ADDR             (AIPS_TZ3_BASE_ADDR+0x90000)
162 #define SAI1_IPS_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0xA0000)
163 #define SAI2_IPS_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0xB0000)
164 #define SAI3_IPS_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0xC0000)
165 #define SPBA_IPS_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0xF0000)
166 #define CAAM_IPS_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0x100000)
167 
168 /* AIPS_TZ#3- On Platform */
169 #define AIPS3_ON_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0x1F0000)
170 /* AIPS_TZ#3- Off Platform */
171 #define AIPS3_OFF_BASE_ADDR             (AIPS_TZ3_BASE_ADDR+0x200000)
172 #define CAN1_IPS_BASE_ADDR              AIPS3_OFF_BASE_ADDR
173 #define CAN2_IPS_BASE_ADDR              (AIPS3_OFF_BASE_ADDR+0x10000)
174 #define I2C1_BASE_ADDR                  (AIPS3_OFF_BASE_ADDR+0x20000)
175 #define I2C2_BASE_ADDR                  (AIPS3_OFF_BASE_ADDR+0x30000)
176 #define I2C3_BASE_ADDR                  (AIPS3_OFF_BASE_ADDR+0x40000)
177 #define I2C4_BASE_ADDR                  (AIPS3_OFF_BASE_ADDR+0x50000)
178 #define UART4_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x60000)
179 #define UART5_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x70000)
180 #define UART6_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x80000)
181 #define UART7_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x90000)
182 #define MUCPU_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0xA0000)
183 #define MUDSP_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0xB0000)
184 #define HS_IPS_BASE_ADDR                (AIPS3_OFF_BASE_ADDR+0xC0000)
185 #define USBOH2_PL301_IPS_BASE_ADDR      (AIPS3_OFF_BASE_ADDR+0xD0000)
186 #define USBOTG1_IPS_BASE_ADDR		(AIPS3_OFF_BASE_ADDR+0x110000)
187 #define USBOTG2_IPS_BASE_ADDR		(AIPS3_OFF_BASE_ADDR+0x120000)
188 #define USBHSIC_IPS_BASE_ADDR		(AIPS3_OFF_BASE_ADDR+0x130000)
189 #define USDHC1_BASE_ADDR                (AIPS3_OFF_BASE_ADDR+0x140000)
190 #define USDHC2_BASE_ADDR                (AIPS3_OFF_BASE_ADDR+0x150000)
191 #define USDHC3_BASE_ADDR                (AIPS3_OFF_BASE_ADDR+0x160000)
192 #define EMVSIM1_IPS_BASE_ADDR           (AIPS3_OFF_BASE_ADDR+0x190000)
193 #define EMVSIM2_IPS_BASE_ADDR           (AIPS3_OFF_BASE_ADDR+0x1A0000)
194 #define SIM1_IPS_BASE_ADDR              (AIPS3_OFF_BASE_ADDR+0x190000)
195 #define SIM2_IPS_BASE_ADDR              (AIPS3_OFF_BASE_ADDR+0x1A0000)
196 #define QSPI1_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x1B0000)
197 #define WEIM_IPS_BASE_ADDR              (AIPS3_OFF_BASE_ADDR+0x1C0000)
198 #define SDMA_PORT_IPS_HOST_BASE_ADDR    (AIPS3_OFF_BASE_ADDR+0x1D0000)
199 #define ENET_IPS_BASE_ADDR              (AIPS3_OFF_BASE_ADDR+0x1E0000)
200 #define ENET2_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x1F0000)
201 
202 #define AIPS1_BASE_ADDR			AIPS1_ON_BASE_ADDR
203 #define AIPS2_BASE_ADDR			AIPS2_ON_BASE_ADDR
204 #define AIPS3_BASE_ADDR			AIPS3_ON_BASE_ADDR
205 
206 #define SDMA_IPS_HOST_BASE_ADDR         SDMA_PORT_IPS_HOST_BASE_ADDR
207 #define SDMA_IPS_HOST_IPS_BASE_ADDR     SDMA_PORT_IPS_HOST_BASE_ADDR
208 
209 #define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR
210 #define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR
211 
212 #define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR
213 #define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR
214 #define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR
215 #define RDC_BASE_ADDR RDC_IPS_BASE_ADDR
216 
217 #define FEC_QUIRK_ENET_MAC
218 #define SNVS_LPGPR	0x68
219 #define CONFIG_SYS_FSL_SEC_OFFSET       0
220 #define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
221 					 CONFIG_SYS_FSL_SEC_OFFSET)
222 #define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
223 #define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
224 					 CONFIG_SYS_FSL_JR0_OFFSET)
225 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
226 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
227 #include <asm/mach-imx/regs-lcdif.h>
228 #include <asm/types.h>
229 
230 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
231 
232 /* System Reset Controller (SRC) */
233 struct src {
234 	u32	scr;
235 	u32 a7rcr0;
236 	u32 a7rcr1;
237 	u32 m4rcr;
238 	u32 reserved1;
239 	u32 ercr;
240 	u32 reserved2;
241 	u32 hsicphy_rcr;
242 	u32 usbophy1_rcr;
243 	u32 usbophy2_rcr;
244 	u32 mipiphy_rcr;
245 	u32 pciephy_rcr;
246 	u32 reserved3[10];
247 	u32	sbmr1;
248 	u32	srsr;
249 	u32	reserved4[2];
250 	u32	sisr;
251 	u32	simr;
252 	u32 sbmr2;
253 	u32 gpr1;
254 	u32 gpr2;
255 	u32 gpr3;
256 	u32 gpr4;
257 	u32 gpr5;
258 	u32 gpr6;
259 	u32 gpr7;
260 	u32 gpr8;
261 	u32 gpr9;
262 	u32 gpr10;
263 	u32 reserved5[985];
264 	u32 ddrc_rcr;
265 };
266 
267 #define SRC_M4_REG_OFFSET		0xC
268 #define SRC_M4C_NON_SCLR_RST_OFFSET	0
269 #define SRC_M4C_NON_SCLR_RST_MASK	BIT(0)
270 #define SRC_M4_ENABLE_OFFSET		3
271 #define SRC_M4_ENABLE_MASK		BIT(3)
272 
273 #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET	1
274 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK		(1 << 1)
275 
276 /* GPR0 Bit Fields */
277 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK     0x1u
278 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT    0
279 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK     0x2u
280 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT    1
281 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK     0x4u
282 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT    2
283 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK     0x8u
284 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT    3
285 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK     0x10u
286 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT    4
287 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK     0x20u
288 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT    5
289 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK     0x40u
290 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT    6
291 #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7)
292 #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7
293 /* GPR1 Bit Fields */
294 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK    0x1u
295 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT   0
296 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK     0x6u
297 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT    1
298 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK)
299 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK    0x8u
300 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT   3
301 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK     0x30u
302 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT    4
303 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK)
304 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK    0x40u
305 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT   6
306 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK     0x180u
307 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT    7
308 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK)
309 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK    0x200u
310 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT   9
311 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK     0xC00u
312 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT    10
313 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK)
314 #define IOMUXC_GPR_GPR1_GPR_IRQ_MASK             0x1000u
315 #define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT            12
316 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
317 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
318 #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u
319 #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14
320 #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u
321 #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15
322 #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK      0x10000u
323 #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT     16
324 #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK   0x20000u
325 #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT  17
326 #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK   0x40000u
327 #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT  18
328 #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u
329 #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22
330 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u
331 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23
332 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK         0x30000000u
333 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT        28
334 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK)
335 #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u
336 #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30
337 /* GPR2 Bit Fields */
338 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u
339 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0
340 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK      0x2u
341 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT     1
342 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK      0x4u
343 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT     2
344 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK      0x8u
345 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT     3
346 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u
347 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4
348 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK    0x20u
349 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT   5
350 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK    0x40u
351 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT   6
352 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK    0x80u
353 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT   7
354 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u
355 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8
356 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK     0x200u
357 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT    9
358 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK     0x400u
359 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT    10
360 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK     0x800u
361 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT    11
362 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u
363 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12
364 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK      0x2000u
365 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT     13
366 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK      0x4000u
367 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT     14
368 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK      0x8000u
369 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT     15
370 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK     0xFF0000u
371 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT    16
372 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK)
373 #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK      0x1000000u
374 #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT     24
375 #define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK          0x2000000u
376 #define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT         25
377 #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK  0x4000000u
378 #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26
379 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u
380 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27
381 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK      0x10000000u
382 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT     28
383 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK       0x20000000u
384 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT      29
385 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK       0x40000000u
386 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT      30
387 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u
388 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31
389 /* GPR3 Bit Fields */
390 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u
391 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0
392 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u
393 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1
394 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u
395 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2
396 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u
397 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3
398 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u
399 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4
400 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u
401 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5
402 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u
403 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6
404 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u
405 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7
406 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u
407 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8
408 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u
409 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9
410 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u
411 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10
412 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u
413 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11
414 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u
415 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12
416 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u
417 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13
418 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u
419 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14
420 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u
421 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15
422 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u
423 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16
424 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u
425 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17
426 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u
427 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18
428 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u
429 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19
430 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u
431 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20
432 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u
433 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21
434 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u
435 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22
436 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u
437 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23
438 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u
439 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24
440 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u
441 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25
442 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u
443 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26
444 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u
445 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27
446 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u
447 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28
448 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u
449 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29
450 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u
451 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30
452 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u
453 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31
454 /* GPR4 Bit Fields */
455 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK   0x1u
456 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT  0
457 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK   0x2u
458 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT  1
459 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK   0x4u
460 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT  2
461 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK  0x8u
462 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3
463 #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK  0x10u
464 #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4
465 #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK   0x20u
466 #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT  5
467 #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK   0x40u
468 #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT  6
469 #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK   0x80u
470 #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT  7
471 #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK   0x10000u
472 #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT  16
473 #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK   0x20000u
474 #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT  17
475 #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK   0x40000u
476 #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT  18
477 #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK  0x80000u
478 #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19
479 #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK  0x100000u
480 #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20
481 #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK   0x200000u
482 #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT  21
483 #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK   0x400000u
484 #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT  22
485 #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK   0x800000u
486 #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT  23
487 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK      0x6000000u
488 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT     25
489 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK)
490 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK      0x18000000u
491 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT     27
492 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK)
493 /* GPR5 Bit Fields */
494 #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u
495 #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4
496 #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u
497 #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5
498 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK      0x40u
499 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT     6
500 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK      0x80u
501 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT     7
502 #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u
503 #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12
504 #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK     0x80000u
505 #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT    19
506 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK      0x100000u
507 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT     20
508 #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u
509 #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21
510 #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK      0x400000u
511 #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT     22
512 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u
513 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24
514 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u
515 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25
516 #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u
517 #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26
518 #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u
519 #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27
520 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u
521 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28
522 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u
523 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29
524 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u
525 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30
526 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u
527 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31
528 /* GPR6 Bit Fields */
529 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK    0x1u
530 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT   0
531 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK    0x2u
532 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT   1
533 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u
534 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2
535 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u
536 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3
537 /* GPR7 Bit Fields */
538 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u
539 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0
540 #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u
541 #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1
542 #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u
543 #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2
544 #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u
545 #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3
546 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u
547 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4
548 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK)
549 #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u
550 #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6
551 #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u
552 #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7
553 #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u
554 #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8
555 #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u
556 #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9
557 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u
558 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10
559 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK)
560 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u
561 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12
562 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u
563 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13
564 /* GPR8 Bit Fields */
565 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u
566 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3
567 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK)
568 #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u
569 #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8
570 /* GPR9 Bit Fields */
571 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u
572 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0
573 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK     0x3Eu
574 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT    1
575 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK)
576 /* GPR10 Bit Fields */
577 #define IOMUXC_GPR_GPR10_GPR0_BF0_MASK           0x1u
578 #define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT          0
579 #define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK         0x2u
580 #define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT        1
581 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u
582 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2
583 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u
584 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3
585 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u
586 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4
587 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK)
588 /* GPR11 Bit Fields */
589 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u
590 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0
591 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu
592 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1
593 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK)
594 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u
595 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6
596 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u
597 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7
598 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK)
599 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u
600 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10
601 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u
602 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11
603 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK)
604 /* GPR12 Bit Fields */
605 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u
606 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0
607 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u
608 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1
609 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u
610 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3
611 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u
612 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4
613 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u
614 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5
615 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u
616 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12
617 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK)
618 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
619 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17
620 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
621 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u
622 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21
623 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK)
624 /* GPR13 Bit Fields */
625 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK  0x1u
626 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0
627 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK  0x2u
628 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1
629 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK    0x4u
630 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT   2
631 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK    0x8u
632 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT   3
633 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK   0x10u
634 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT  4
635 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK   0x20u
636 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT  5
637 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK  0x40u
638 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6
639 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK   0x80u
640 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT  7
641 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u
642 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8
643 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u
644 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9
645 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u
646 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10
647 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u
648 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11
649 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u
650 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12
651 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u
652 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13
653 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK   0x4000u
654 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT  14
655 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u
656 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15
657 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u
658 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16
659 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK)
660 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u
661 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24
662 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK)
663 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u
664 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28
665 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u
666 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29
667 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u
668 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30
669 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u
670 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31
671 /* GPR14 Bit Fields */
672 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u
673 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0
674 #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u
675 #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1
676 /* GPR15 Bit Fields */
677 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u
678 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0
679 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u
680 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1
681 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu
682 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2
683 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK)
684 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u
685 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16
686 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK)
687 /* GPR16 Bit Fields */
688 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u
689 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0
690 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK)
691 #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u
692 #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2
693 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u
694 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3
695 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u
696 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4
697 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK   0x20u
698 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT  5
699 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK   0x3C0u
700 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT  6
701 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK)
702 #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u
703 #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10
704 #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK  0x800u
705 #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11
706 #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK    0x1000u
707 #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT   12
708 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK   0xE000u
709 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT  13
710 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK)
711 #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK   0x10000u
712 #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT  16
713 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u
714 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17
715 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u
716 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19
717 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK)
718 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u
719 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21
720 #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK   0x400000u
721 #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT  22
722 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u
723 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23
724 /* GPR17 Bit Fields */
725 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu
726 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0
727 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK)
728 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u
729 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8
730 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK)
731 /* GPR18 Bit Fields */
732 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u
733 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0
734 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK)
735 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u
736 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3
737 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK)
738 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u
739 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5
740 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK)
741 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u
742 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8
743 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK)
744 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u
745 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14
746 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u
747 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16
748 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK)
749 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u
750 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24
751 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK)
752 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u
753 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26
754 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u
755 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27
756 #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK  0x10000000u
757 #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28
758 #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u
759 #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29
760 /* GPR19 Bit Fields */
761 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u
762 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0
763 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u
764 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8
765 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK)
766 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u
767 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16
768 #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u
769 #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17
770 /* GPR20 Bit Fields */
771 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK         0x3Fu
772 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT        0
773 #define IOMUXC_GPR_GPR20_GPR_LVDS_P(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK)
774 #define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK         0x3F00u
775 #define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT        8
776 #define IOMUXC_GPR_GPR20_GPR_LVDS_M(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK)
777 #define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK         0x30000u
778 #define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT        16
779 #define IOMUXC_GPR_GPR20_GPR_LVDS_S(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK)
780 #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK      0x1000000u
781 #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT     24
782 #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u
783 #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25
784 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u
785 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27
786 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK)
787 /* GPR21 Bit Fields */
788 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK      0x7u
789 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT     0
790 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK)
791 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK      0x38u
792 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT     3
793 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK)
794 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK      0x1C0u
795 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT     6
796 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK)
797 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK     0xE00u
798 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT    9
799 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK)
800 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK      0x7000u
801 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT     12
802 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK)
803 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK      0x38000u
804 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT     15
805 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK)
806 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK  0x40000u
807 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18
808 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK  0x80000u
809 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19
810 /* GPR22 Bit Fields */
811 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK  0xFF0000u
812 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16
813 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK)
814 #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u
815 #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24
816 #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u
817 #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25
818 #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u
819 #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26
820 #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u
821 #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27
822 #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u
823 #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28
824 #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u
825 #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29
826 #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u
827 #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31
828 
829 #define IMX7D_GPR5_CSI1_MUX_CTRL_MASK			(0x1 << 4)
830 #define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI		(0x0 << 4)
831 #define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI		(0x1 << 4)
832 
833 struct iomuxc {
834 	u32 gpr[23];
835 	/* mux and pad registers */
836 };
837 
838 struct iomuxc_gpr_base_regs {
839 	u32 gpr[23];        /* 0x000 */
840 };
841 
842 /* ECSPI registers */
843 struct cspi_regs {
844 	u32 rxdata;
845 	u32 txdata;
846 	u32 ctrl;
847 	u32 cfg;
848 	u32 intr;
849 	u32 dma;
850 	u32 stat;
851 	u32 period;
852 };
853 
854 /*
855  * CSPI register definitions
856  */
857 #define MXC_ECSPI
858 #define MXC_CSPICTRL_EN		(1 << 0)
859 #define MXC_CSPICTRL_MODE	(1 << 1)
860 #define MXC_CSPICTRL_XCH	(1 << 2)
861 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
862 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
863 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
864 #define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
865 #define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
866 #define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
867 #define MXC_CSPICTRL_MAXBITS	0xfff
868 #define MXC_CSPICTRL_TC		(1 << 7)
869 #define MXC_CSPICTRL_RXOVF	(1 << 6)
870 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
871 #define MAX_SPI_BYTES	32
872 
873 /* Bit position inside CTRL register to be associated with SS */
874 #define MXC_CSPICTRL_CHAN	18
875 
876 /* Bit position inside CON register to be associated with SS */
877 #define MXC_CSPICON_PHA		0  /* SCLK phase control */
878 #define MXC_CSPICON_POL		4  /* SCLK polarity */
879 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
880 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
881 
882 #define MXC_SPI_BASE_ADDRESSES \
883 	ECSPI1_BASE_ADDR, \
884 	ECSPI2_BASE_ADDR, \
885 	ECSPI3_BASE_ADDR, \
886 	ECSPI4_BASE_ADDR
887 
888 #define CSU_INIT_SEC_LEVEL0	0x00FF00FF
889 #define CSU_NUM_REGS		64
890 
891 struct ocotp_regs {
892 	u32 ctrl;
893 	u32 ctrl_set;
894 	u32 ctrl_clr;
895 	u32 ctrl_tog;
896 	u32 timing;
897 	u32 rsvd0[3];
898 	u32 data0;
899 	u32 rsvd1[3];
900 	u32 data1;
901 	u32 rsvd2[3];
902 	u32 data2;
903 	u32 rsvd3[3];
904 	u32 data3;
905 	u32 rsvd4[3];
906 	u32 read_ctrl;
907 	u32 rsvd5[3];
908 	u32 read_fuse_data0;
909 	u32 rsvd6[3];
910 	u32 read_fuse_data1;
911 	u32 rsvd7[3];
912 	u32 read_fuse_data2;
913 	u32 rsvd8[3];
914 	u32 read_fuse_data3;
915 	u32 rsvd9[3];
916 	u32 sw_sticky;
917 	u32 rsvd10[3];
918 	u32 scs;
919 	u32 scs_set;
920 	u32 scs_clr;
921 	u32 scs_tog;
922 	u32 crc_addr;
923 	u32 rsvd11[3];
924 	u32 crc_value;
925 	u32 rsvd12[3];
926 	u32 version;
927 	u32 rsvd13[0xc3];
928 
929 	struct fuse_bank {	/* offset 0x400 */
930 		u32 fuse_regs[0x10];
931 	} bank[16];
932 };
933 
934 struct fuse_bank0_regs {
935 	u32 lock;
936 	u32 rsvd0[3];
937 	u32 tester0;
938 	u32 rsvd1[3];
939 	u32 tester1;
940 	u32 rsvd2[3];
941 	u32 tester2;
942 	u32 rsvd3[3];
943 };
944 
945 struct fuse_bank1_regs {
946 	u32 tester3;
947 	u32 rsvd0[3];
948 	u32 tester4;
949 	u32 rsvd1[3];
950 	u32 tester5;
951 	u32 rsvd2[3];
952 	u32 cfg0;
953 	u32 rsvd3[3];
954 };
955 
956 struct fuse_bank2_regs {
957 	u32 cfg1;
958 	u32 rsvd0[3];
959 	u32 cfg2;
960 	u32 rsvd1[3];
961 	u32 cfg3;
962 	u32 rsvd2[3];
963 	u32 cfg4;
964 	u32 rsvd3[3];
965 };
966 
967 struct fuse_bank3_regs {
968 	u32 mem_trim0;
969 	u32 rsvd0[3];
970 	u32 mem_trim1;
971 	u32 rsvd1[3];
972 	u32 ana0;
973 	u32 rsvd2[3];
974 	u32 ana1;
975 	u32 rsvd3[3];
976 };
977 
978 struct fuse_bank8_regs {
979 	u32 sjc_resp_low;
980 	u32 rsvd0[3];
981 	u32 sjc_resp_high;
982 	u32 rsvd1[3];
983 	u32 usb_id;
984 	u32 rsvd2[3];
985 	u32 field_return;
986 	u32 rsvd3[3];
987 };
988 
989 struct fuse_bank9_regs {
990 	u32 mac_addr0;
991 	u32 rsvd0[3];
992 	u32 mac_addr1;
993 	u32 rsvd1[3];
994 	u32 mac_addr2;
995 	u32 rsvd2[7];
996 };
997 
998 struct aipstz_regs {
999 	u32	mprot0;
1000 	u32	mprot1;
1001 	u32	rsvd[0xe];
1002 	u32	opacr0;
1003 	u32	opacr1;
1004 	u32	opacr2;
1005 	u32	opacr3;
1006 	u32	opacr4;
1007 };
1008 
1009 struct wdog_regs {
1010 	u16	wcr;	/* Control */
1011 	u16	wsr;	/* Service */
1012 	u16	wrsr;	/* Reset Status */
1013 	u16	wicr;	/* Interrupt Control */
1014 	u16	wmcr;	/* Miscellaneous Control */
1015 };
1016 
1017 struct dbg_monitor_regs {
1018 	u32	ctrl[4];		/* Control */
1019 	u32	master_en[4];		/* Master enable */
1020 	u32	irq[4];			/* IRQ */
1021 	u32	trap_addr_low[4];	/* Trap address low */
1022 	u32	trap_addr_high[4];	/* Trap address high */
1023 	u32	trap_id[4];		/* Trap ID */
1024 	u32	snvs_addr[4];		/* SNVS address */
1025 	u32	snvs_data[4];		/* SNVS data */
1026 	u32	snvs_info[4];		/* SNVS info */
1027 	u32	version[4];		/* Version */
1028 };
1029 
1030 struct rdc_regs {
1031 	u32	vir;		/* Version information */
1032 	u32	reserved1[8];
1033 	u32	stat;		/* Status */
1034 	u32	intctrl;	/* Interrupt and Control */
1035 	u32	intstat;	/* Interrupt Status */
1036 	u32	reserved2[116];
1037 	u32	mda[27];		/* Master Domain Assignment */
1038 	u32	reserved3[101];
1039 	u32	pdap[118];		/* Peripheral Domain Access Permissions */
1040 	u32	reserved4[138];
1041 	struct {
1042 		u32 mrsa;		/* Memory Region Start Address */
1043 		u32 mrea;		/* Memory Region End Address */
1044 		u32 mrc;		/* Memory Region Control */
1045 		u32 mrvs;		/* Memory Region Violation Status */
1046 	} mem_region[52];
1047 };
1048 
1049 struct rdc_sema_regs {
1050 	u8	gate[64];	/* Gate */
1051 	u16	rstgt;		/* Reset Gate */
1052 };
1053 
1054 #define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR
1055 
1056 #define	LCDIF_CTRL_SFTRST					(1 << 31)
1057 #define	LCDIF_CTRL_CLKGATE					(1 << 30)
1058 #define	LCDIF_CTRL_YCBCR422_INPUT				(1 << 29)
1059 #define	LCDIF_CTRL_READ_WRITEB					(1 << 28)
1060 #define	LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE				(1 << 27)
1061 #define	LCDIF_CTRL_DATA_SHIFT_DIR				(1 << 26)
1062 #define	LCDIF_CTRL_SHIFT_NUM_BITS_MASK				(0x1f << 21)
1063 #define	LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET			21
1064 #define	LCDIF_CTRL_DVI_MODE					(1 << 20)
1065 #define	LCDIF_CTRL_BYPASS_COUNT					(1 << 19)
1066 #define	LCDIF_CTRL_VSYNC_MODE					(1 << 18)
1067 #define	LCDIF_CTRL_DOTCLK_MODE					(1 << 17)
1068 #define	LCDIF_CTRL_DATA_SELECT					(1 << 16)
1069 #define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK			(0x3 << 14)
1070 #define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET			14
1071 #define	LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK			(0x3 << 12)
1072 #define	LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET			12
1073 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK			(0x3 << 10)
1074 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET			10
1075 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT			(0 << 10)
1076 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT			(1 << 10)
1077 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT			(2 << 10)
1078 #define	LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT			(3 << 10)
1079 #define	LCDIF_CTRL_WORD_LENGTH_MASK				(0x3 << 8)
1080 #define	LCDIF_CTRL_WORD_LENGTH_OFFSET				8
1081 #define	LCDIF_CTRL_WORD_LENGTH_16BIT				(0 << 8)
1082 #define	LCDIF_CTRL_WORD_LENGTH_8BIT				(1 << 8)
1083 #define	LCDIF_CTRL_WORD_LENGTH_18BIT				(2 << 8)
1084 #define	LCDIF_CTRL_WORD_LENGTH_24BIT				(3 << 8)
1085 #define	LCDIF_CTRL_RGB_TO_YCBCR422_CSC				(1 << 7)
1086 #define	LCDIF_CTRL_LCDIF_MASTER					(1 << 5)
1087 #define	LCDIF_CTRL_DATA_FORMAT_16_BIT				(1 << 3)
1088 #define	LCDIF_CTRL_DATA_FORMAT_18_BIT				(1 << 2)
1089 #define	LCDIF_CTRL_DATA_FORMAT_24_BIT				(1 << 1)
1090 #define	LCDIF_CTRL_RUN						(1 << 0)
1091 
1092 #define	LCDIF_CTRL1_COMBINE_MPU_WR_STRB				(1 << 27)
1093 #define	LCDIF_CTRL1_BM_ERROR_IRQ_EN				(1 << 26)
1094 #define	LCDIF_CTRL1_BM_ERROR_IRQ				(1 << 25)
1095 #define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW			(1 << 24)
1096 #define	LCDIF_CTRL1_INTERLACE_FIELDS				(1 << 23)
1097 #define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD		(1 << 22)
1098 #define	LCDIF_CTRL1_FIFO_CLEAR					(1 << 21)
1099 #define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS			(1 << 20)
1100 #define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK			(0xf << 16)
1101 #define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET			16
1102 #define	LCDIF_CTRL1_OVERFLOW_IRQ_EN				(1 << 15)
1103 #define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN				(1 << 14)
1104 #define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN			(1 << 13)
1105 #define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN				(1 << 12)
1106 #define	LCDIF_CTRL1_OVERFLOW_IRQ				(1 << 11)
1107 #define	LCDIF_CTRL1_UNDERFLOW_IRQ				(1 << 10)
1108 #define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ				(1 << 9)
1109 #define	LCDIF_CTRL1_VSYNC_EDGE_IRQ				(1 << 8)
1110 #define	LCDIF_CTRL1_BUSY_ENABLE					(1 << 2)
1111 #define	LCDIF_CTRL1_MODE86					(1 << 1)
1112 #define	LCDIF_CTRL1_RESET					(1 << 0)
1113 
1114 #define	LCDIF_CTRL2_OUTSTANDING_REQS_MASK			(0x7 << 21)
1115 #define	LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET			21
1116 #define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1			(0x0 << 21)
1117 #define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2			(0x1 << 21)
1118 #define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4			(0x2 << 21)
1119 #define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8			(0x3 << 21)
1120 #define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16			(0x4 << 21)
1121 #define	LCDIF_CTRL2_BURST_LEN_8					(1 << 20)
1122 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_MASK			(0x7 << 16)
1123 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET			16
1124 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_RGB			(0x0 << 16)
1125 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_RBG			(0x1 << 16)
1126 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_GBR			(0x2 << 16)
1127 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_GRB			(0x3 << 16)
1128 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_BRG			(0x4 << 16)
1129 #define	LCDIF_CTRL2_ODD_LINE_PATTERN_BGR			(0x5 << 16)
1130 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK			(0x7 << 12)
1131 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET			12
1132 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB			(0x0 << 12)
1133 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG			(0x1 << 12)
1134 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR			(0x2 << 12)
1135 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB			(0x3 << 12)
1136 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG			(0x4 << 12)
1137 #define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR			(0x5 << 12)
1138 #define	LCDIF_CTRL2_READ_PACK_DIR				(1 << 10)
1139 #define	LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT		(1 << 9)
1140 #define	LCDIF_CTRL2_READ_MODE_6_BIT_INPUT			(1 << 8)
1141 #define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK		(0x7 << 4)
1142 #define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET	4
1143 #define	LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK			(0x7 << 1)
1144 #define	LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET			1
1145 
1146 #define	LCDIF_TRANSFER_COUNT_V_COUNT_MASK			(0xffff << 16)
1147 #define	LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET			16
1148 #define	LCDIF_TRANSFER_COUNT_H_COUNT_MASK			(0xffff << 0)
1149 #define	LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET			0
1150 
1151 #define	LCDIF_CUR_BUF_ADDR_MASK					0xffffffff
1152 #define	LCDIF_CUR_BUF_ADDR_OFFSET				0
1153 
1154 #define	LCDIF_NEXT_BUF_ADDR_MASK				0xffffffff
1155 #define	LCDIF_NEXT_BUF_ADDR_OFFSET				0
1156 
1157 #define	LCDIF_TIMING_CMD_HOLD_MASK				(0xff << 24)
1158 #define	LCDIF_TIMING_CMD_HOLD_OFFSET				24
1159 #define	LCDIF_TIMING_CMD_SETUP_MASK				(0xff << 16)
1160 #define	LCDIF_TIMING_CMD_SETUP_OFFSET				16
1161 #define	LCDIF_TIMING_DATA_HOLD_MASK				(0xff << 8)
1162 #define	LCDIF_TIMING_DATA_HOLD_OFFSET				8
1163 #define	LCDIF_TIMING_DATA_SETUP_MASK				(0xff << 0)
1164 #define	LCDIF_TIMING_DATA_SETUP_OFFSET				0
1165 
1166 #define	LCDIF_VDCTRL0_VSYNC_OEB					(1 << 29)
1167 #define	LCDIF_VDCTRL0_ENABLE_PRESENT				(1 << 28)
1168 #define	LCDIF_VDCTRL0_VSYNC_POL					(1 << 27)
1169 #define	LCDIF_VDCTRL0_HSYNC_POL					(1 << 26)
1170 #define	LCDIF_VDCTRL0_DOTCLK_POL				(1 << 25)
1171 #define	LCDIF_VDCTRL0_ENABLE_POL				(1 << 24)
1172 #define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT				(1 << 21)
1173 #define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT			(1 << 20)
1174 #define	LCDIF_VDCTRL0_HALF_LINE					(1 << 19)
1175 #define	LCDIF_VDCTRL0_HALF_LINE_MODE				(1 << 18)
1176 #define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK			0x3ffff
1177 #define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET			0
1178 
1179 #define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK				0xffffffff
1180 #define	LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET			0
1181 
1182 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0x3fff << 18)
1183 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			18
1184 #define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK				0x3ffff
1185 #define	LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET			0
1186 
1187 #define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS				(1 << 29)
1188 #define	LCDIF_VDCTRL3_VSYNC_ONLY				(1 << 28)
1189 #define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK			(0xfff << 16)
1190 #define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET		16
1191 #define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK			(0xffff << 0)
1192 #define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET			0
1193 
1194 #define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK			(0x7 << 29)
1195 #define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET			29
1196 #define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON				(1 << 18)
1197 #define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK		0x3ffff
1198 #define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET		0
1199 
1200 
1201 extern void check_cpu_temperature(void);
1202 
1203 extern void pcie_power_up(void);
1204 extern void pcie_power_off(void);
1205 
1206 /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
1207  * If boot from the other mode, USB0_PWD will keep reset value
1208  */
1209 #define	is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
1210 	readl(USBOTG2_IPS_BASE_ADDR + 0x158))
1211 #define	disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
1212 
1213 struct bootrom_sw_info {
1214 	u8 reserved_1;
1215 	u8 boot_dev_instance;
1216 	u8 boot_dev_type;
1217 	u8 reserved_2;
1218 	u32 arm_core_freq;
1219 	u32 axi_freq;
1220 	u32 ddr_freq;
1221 	u32 gpt1_freq;
1222 	u32 reserved_3[3];
1223 };
1224 
1225 #endif /* __ASSEMBLER__*/
1226 #endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */
1227