1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * Author: 5 * Peng Fan <Peng.Fan@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__ 11 #define __ARCH_ARM_MACH_MX7_CCM_REGS_H__ 12 13 #include <asm/arch/imx-regs.h> 14 #include <asm/io.h> 15 16 #define CCM_GPR0_OFFSET 0x0 17 #define CCM_OBSERVE0_OFFSET 0x0400 18 #define CCM_SCTRL0_OFFSET 0x0800 19 #define CCM_CCGR0_OFFSET 0x4000 20 #define CCM_ROOT0_TARGET_OFFSET 0x8000 21 22 #ifndef __ASSEMBLY__ 23 24 struct mxc_ccm_ccgr { 25 uint32_t ccgr; 26 uint32_t ccgr_set; 27 uint32_t ccgr_clr; 28 uint32_t ccgr_tog; 29 }; 30 31 struct mxc_ccm_root_slice { 32 uint32_t target_root; 33 uint32_t target_root_set; 34 uint32_t target_root_clr; 35 uint32_t target_root_tog; 36 uint32_t reserved_0[4]; 37 uint32_t post; 38 uint32_t post_root_set; 39 uint32_t post_root_clr; 40 uint32_t post_root_tog; 41 uint32_t pre; 42 uint32_t pre_root_set; 43 uint32_t pre_root_clr; 44 uint32_t pre_root_tog; 45 uint32_t reserved_1[12]; 46 uint32_t access_ctrl; 47 uint32_t access_ctrl_root_set; 48 uint32_t access_ctrl_root_clr; 49 uint32_t access_ctrl_root_tog; 50 }; 51 52 /** CCM - Peripheral register structure */ 53 struct mxc_ccm_reg { 54 uint32_t gpr0; 55 uint32_t gpr0_set; 56 uint32_t gpr0_clr; 57 uint32_t gpr0_tog; 58 uint32_t reserved_0[4092]; 59 struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */ 60 uint32_t reserved_1[3332]; 61 struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */ 62 63 }; 64 65 struct mxc_ccm_anatop_reg { 66 uint32_t ctrl_24m; /* offset 0x0000 */ 67 uint32_t ctrl_24m_set; 68 uint32_t ctrl_24m_clr; 69 uint32_t ctrl_24m_tog; 70 uint32_t rcosc_config0; /* offset 0x0010 */ 71 uint32_t rcosc_config0_set; 72 uint32_t rcosc_config0_clr; 73 uint32_t rcosc_config0_tog; 74 uint32_t rcosc_config1; /* offset 0x0020 */ 75 uint32_t rcosc_config1_set; 76 uint32_t rcosc_config1_clr; 77 uint32_t rcosc_config1_tog; 78 uint32_t rcosc_config2; /* offset 0x0030 */ 79 uint32_t rcosc_config2_set; 80 uint32_t rcosc_config2_clr; 81 uint32_t rcosc_config2_tog; 82 uint8_t reserved_0[16]; 83 uint32_t osc_32k; /* offset 0x0050 */ 84 uint32_t osc_32k_set; 85 uint32_t osc_32k_clr; 86 uint32_t osc_32k_tog; 87 uint32_t pll_arm; /* offset 0x0060 */ 88 uint32_t pll_arm_set; 89 uint32_t pll_arm_clr; 90 uint32_t pll_arm_tog; 91 uint32_t pll_ddr; /* offset 0x0070 */ 92 uint32_t pll_ddr_set; 93 uint32_t pll_ddr_clr; 94 uint32_t pll_ddr_tog; 95 uint32_t pll_ddr_ss; /* offset 0x0080 */ 96 uint8_t reserved_1[12]; 97 uint32_t pll_ddr_num; /* offset 0x0090 */ 98 uint8_t reserved_2[12]; 99 uint32_t pll_ddr_denom; /* offset 0x00a0 */ 100 uint8_t reserved_3[12]; 101 uint32_t pll_480; /* offset 0x00b0 */ 102 uint32_t pll_480_set; 103 uint32_t pll_480_clr; 104 uint32_t pll_480_tog; 105 uint32_t pfd_480a; /* offset 0x00c0 */ 106 uint32_t pfd_480a_set; 107 uint32_t pfd_480a_clr; 108 uint32_t pfd_480a_tog; 109 uint32_t pfd_480b; /* offset 0x00d0 */ 110 uint32_t pfd_480b_set; 111 uint32_t pfd_480b_clr; 112 uint32_t pfd_480b_tog; 113 uint32_t pll_enet; /* offset 0x00e0 */ 114 uint32_t pll_enet_set; 115 uint32_t pll_enet_clr; 116 uint32_t pll_enet_tog; 117 uint32_t pll_audio; /* offset 0x00f0 */ 118 uint32_t pll_audio_set; 119 uint32_t pll_audio_clr; 120 uint32_t pll_audio_tog; 121 uint32_t pll_audio_ss; /* offset 0x0100 */ 122 uint8_t reserved_4[12]; 123 uint32_t pll_audio_num; /* offset 0x0110 */ 124 uint8_t reserved_5[12]; 125 uint32_t pll_audio_denom; /* offset 0x0120 */ 126 uint8_t reserved_6[12]; 127 uint32_t pll_video; /* offset 0x0130 */ 128 uint32_t pll_video_set; 129 uint32_t pll_video_clr; 130 uint32_t pll_video_tog; 131 uint32_t pll_video_ss; /* offset 0x0140 */ 132 uint8_t reserved_7[12]; 133 uint32_t pll_video_num; /* offset 0x0150 */ 134 uint8_t reserved_8[12]; 135 uint32_t pll_video_denom; /* offset 0x0160 */ 136 uint8_t reserved_9[12]; 137 uint32_t clk_misc0; /* offset 0x0170 */ 138 uint32_t clk_misc0_set; 139 uint32_t clk_misc0_clr; 140 uint32_t clk_misc0_tog; 141 uint32_t clk_rsvd; /* offset 0x0180 */ 142 uint8_t reserved_10[124]; 143 uint32_t reg_1p0a; /* offset 0x0200 */ 144 uint32_t reg_1p0a_set; 145 uint32_t reg_1p0a_clr; 146 uint32_t reg_1p0a_tog; 147 uint32_t reg_1p0d; /* offsest 0x0210 */ 148 uint32_t reg_1p0d_set; 149 uint32_t reg_1p0d_clr; 150 uint32_t reg_1p0d_tog; 151 uint32_t reg_hsic_1p2; /* offset 0x0220 */ 152 uint32_t reg_hsic_1p2_set; 153 uint32_t reg_hsic_1p2_clr; 154 uint32_t reg_hsic_1p2_tog; 155 uint32_t reg_lpsr_1p0; /* offset 0x0230 */ 156 uint32_t reg_lpsr_1p0_set; 157 uint32_t reg_lpsr_1p0_clr; 158 uint32_t reg_lpsr_1p0_tog; 159 uint32_t reg_3p0; /* offset 0x0240 */ 160 uint32_t reg_3p0_set; 161 uint32_t reg_3p0_clr; 162 uint32_t reg_3p0_tog; 163 uint32_t reg_snvs; /* offset 0x0250 */ 164 uint32_t reg_snvs_set; 165 uint32_t reg_snvs_clr; 166 uint32_t reg_snvs_tog; 167 uint32_t analog_debug_misc0; /* offset 0x0260 */ 168 uint32_t analog_debug_misc0_set; 169 uint32_t analog_debug_misc0_clr; 170 uint32_t analog_debug_misc0_tog; 171 uint32_t ref; /* offset 0x0270 */ 172 uint32_t ref_set; 173 uint32_t ref_clr; 174 uint32_t ref_tog; 175 uint8_t reserved_11[128]; 176 uint32_t tempsense0; /* offset 0x0300 */ 177 uint32_t tempsense0_set; 178 uint32_t tempsense0_clr; 179 uint32_t tempsense0_tog; 180 uint32_t tempsense1; /* offset 0x0310 */ 181 uint32_t tempsense1_set; 182 uint32_t tempsense1_clr; 183 uint32_t tempsense1_tog; 184 uint32_t tempsense_trim; /* offset 0x0320 */ 185 uint32_t tempsense_trim_set; 186 uint32_t tempsense_trim_clr; 187 uint32_t tempsense_trim_tog; 188 uint32_t lowpwr_ctrl; /* offset 0x0330 */ 189 uint32_t lowpwr_ctrl_set; 190 uint32_t lowpwr_ctrl_clr; 191 uint32_t lowpwr_ctrl_tog; 192 uint32_t snvs_tamper_offset_ctrl; /* offset 0x0340 */ 193 uint32_t snvs_tamper_offset_ctrl_set; 194 uint32_t snvs_tamper_offset_ctrl_clr; 195 uint32_t snvs_tamper_offset_ctrl_tog; 196 uint32_t snvs_tamper_pull_ctrl; /* offset 0x0350 */ 197 uint32_t snvs_tamper_pull_ctrl_set; 198 uint32_t snvs_tamper_pull_ctrl_clr; 199 uint32_t snvs_tamper_pull_ctrl_tog; 200 uint32_t snvs_test; /* offset 0x0360 */ 201 uint32_t snvs_test_set; 202 uint32_t snvs_test_clr; 203 uint32_t snvs_test_tog; 204 uint32_t snvs_tamper_trim_ctrl; /* offset 0x0370 */ 205 uint32_t snvs_tamper_trim_ctrl_set; 206 uint32_t snvs_tamper_trim_ctrl_ctrl; 207 uint32_t snvs_tamper_trim_ctrl_tog; 208 uint32_t snvs_misc_ctrl; /* offset 0x0380 */ 209 uint32_t snvs_misc_ctrl_set; 210 uint32_t snvs_misc_ctrl_clr; 211 uint32_t snvs_misc_ctrl_tog; 212 uint8_t reserved_12[112]; 213 uint32_t misc; /* offset 0x0400 */ 214 uint8_t reserved_13[252]; 215 uint32_t adc0; /* offset 0x0500 */ 216 uint8_t reserved_14[12]; 217 uint32_t adc1; /* offset 0x0510 */ 218 uint8_t reserved_15[748]; 219 uint32_t digprog; /* offset 0x0800 */ 220 }; 221 #endif 222 223 #define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK (0x01 << 17) 224 225 #define ANADIG_PLL_LOCK 0x80000000 226 227 #define ANADIG_PLL_ARM_PWDN_MASK (0x01 << 12) 228 #define ANADIG_PLL_480_PWDN_MASK (0x01 << 12) 229 #define ANADIG_PLL_DDR_PWDN_MASK (0x01 << 20) 230 #define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5) 231 #define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12) 232 233 234 #define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f 235 #define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B 236 #define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016 237 #define ANATOP_PFD480B_PFD4_FRAC_432M_VAL 0x00000014 238 239 /* PLL_ARM Bit Fields */ 240 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7F 241 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 242 #define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80 243 #define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7 244 #define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100 245 #define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8 246 #define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200 247 #define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9 248 #define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400 249 #define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10 250 #define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800 251 #define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11 252 #define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000 253 #define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12 254 #define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000 255 #define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13 256 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000 257 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14 258 #define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000 259 #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16 260 #define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000 261 #define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17 262 #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000 263 #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18 264 #define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000 265 #define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19 266 #define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000 267 #define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20 268 #define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000 269 #define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21 270 #define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000 271 #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31 272 273 /* PLL_DDR Bit Fields */ 274 #define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7F 275 #define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0 276 #define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80 277 #define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7 278 #define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100 279 #define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8 280 #define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200 281 #define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9 282 #define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400 283 #define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10 284 #define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800 285 #define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11 286 #define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000 287 #define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12 288 #define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000 289 #define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13 290 #define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000 291 #define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14 292 #define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000 293 #define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16 294 #define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000 295 #define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17 296 #define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000 297 #define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18 298 #define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000 299 #define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19 300 #define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000 301 #define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20 302 #define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000 303 #define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21 304 #define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000 305 #define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23 306 #define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000 307 #define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31 308 309 /* PLL_480 Bit Fields */ 310 #define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1 311 #define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0 312 #define CCM_ANALOG_PLL_480_RSVD0_MASK 0xE 313 #define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1 314 #define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10 315 #define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4 316 #define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20 317 #define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5 318 #define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40 319 #define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6 320 #define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80 321 #define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7 322 #define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100 323 #define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8 324 #define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200 325 #define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9 326 #define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400 327 #define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10 328 #define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800 329 #define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11 330 #define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000 331 #define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12 332 #define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000 333 #define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13 334 #define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000 335 #define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14 336 #define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000 337 #define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16 338 #define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000 339 #define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17 340 #define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000 341 #define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18 342 #define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000 343 #define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19 344 #define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000 345 #define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20 346 #define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000 347 #define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21 348 #define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000 349 #define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22 350 #define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000 351 #define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23 352 #define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000 353 #define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24 354 #define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000 355 #define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25 356 #define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000 357 #define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26 358 #define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000 359 #define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27 360 #define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000 361 #define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28 362 #define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000 363 #define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29 364 #define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000 365 #define CCM_ANALOG_PLL_480_LOCK_SHIFT 31 366 367 /* PFD_480A Bit Fields */ 368 #define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3F 369 #define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0 370 #define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40 371 #define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6 372 #define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80 373 #define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7 374 #define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00 375 #define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8 376 #define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000 377 #define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14 378 #define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000 379 #define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15 380 #define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000 381 #define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16 382 #define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000 383 #define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22 384 #define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000 385 #define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23 386 #define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000 387 #define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24 388 #define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000 389 #define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30 390 #define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000 391 #define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31 392 /* PFD_480B Bit Fields */ 393 #define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3F 394 #define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0 395 #define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40 396 #define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6 397 #define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80 398 #define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7 399 #define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00 400 #define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8 401 #define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000 402 #define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14 403 #define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000 404 #define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15 405 #define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000 406 #define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16 407 #define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000 408 #define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22 409 #define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000 410 #define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23 411 #define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000 412 #define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24 413 #define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000 414 #define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30 415 #define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000 416 #define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31 417 418 /* PLL_ENET Bit Fields */ 419 #define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1 420 #define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0 421 #define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2 422 #define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1 423 #define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4 424 #define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2 425 #define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8 426 #define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3 427 #define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10 428 #define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4 429 #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20 430 #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5 431 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40 432 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6 433 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80 434 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7 435 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100 436 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8 437 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200 438 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9 439 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400 440 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10 441 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800 442 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11 443 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000 444 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12 445 #define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000 446 #define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13 447 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000 448 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14 449 #define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000 450 #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16 451 #define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000 452 #define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17 453 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000 454 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18 455 #define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000 456 #define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19 457 #define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000 458 #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31 459 460 /* PLL_AUDIO Bit Fields */ 461 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu 462 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0 463 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) 464 #define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK 0x80u 465 #define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT 7 466 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK 0x100u 467 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT 8 468 #define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK 0x200u 469 #define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT 9 470 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK 0x400u 471 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT 10 472 #define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK 0x800u 473 #define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11 474 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u 475 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12 476 #define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK 0x2000u 477 #define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT 13 478 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u 479 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14 480 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) 481 #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u 482 #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16 483 #define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK 0x20000u 484 #define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17 485 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u 486 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18 487 #define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u 488 #define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19 489 #define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK) 490 #define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK 0x200000u 491 #define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT 21 492 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK 0xC00000u 493 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT 22 494 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK) 495 #define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u 496 #define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24 497 #define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK 0x7E000000u 498 #define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT 25 499 #define CCM_ANALOG_PLL_AUDIO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK) 500 #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u 501 #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31 502 /* PLL_AUDIO_SET Bit Fields */ 503 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu 504 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0 505 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) 506 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK 0x80u 507 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT 7 508 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK 0x100u 509 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8 510 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK 0x200u 511 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT 9 512 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK 0x400u 513 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10 514 #define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u 515 #define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11 516 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u 517 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12 518 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u 519 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13 520 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u 521 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14 522 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) 523 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u 524 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16 525 #define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u 526 #define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17 527 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u 528 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18 529 #define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u 530 #define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19 531 #define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK) 532 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK 0x200000u 533 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT 21 534 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u 535 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22 536 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK) 537 #define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u 538 #define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24 539 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK 0x7E000000u 540 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT 25 541 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK) 542 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u 543 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31 544 /* PLL_AUDIO_CLR Bit Fields */ 545 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu 546 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0 547 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) 548 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK 0x80u 549 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT 7 550 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK 0x100u 551 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8 552 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK 0x200u 553 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT 9 554 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK 0x400u 555 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10 556 #define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u 557 #define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11 558 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u 559 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12 560 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u 561 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13 562 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u 563 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14 564 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) 565 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u 566 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16 567 #define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u 568 #define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17 569 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u 570 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18 571 #define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u 572 #define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19 573 #define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK) 574 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK 0x200000u 575 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT 21 576 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u 577 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22 578 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK) 579 #define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u 580 #define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24 581 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK 0x7E000000u 582 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT 25 583 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK) 584 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u 585 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31 586 /* PLL_AUDIO_TOG Bit Fields */ 587 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu 588 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0 589 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) 590 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK 0x80u 591 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT 7 592 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK 0x100u 593 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8 594 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK 0x200u 595 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT 9 596 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK 0x400u 597 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10 598 #define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u 599 #define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11 600 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u 601 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12 602 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u 603 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13 604 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u 605 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14 606 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) 607 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u 608 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16 609 #define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u 610 #define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17 611 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u 612 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18 613 #define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u 614 #define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19 615 #define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK) 616 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK 0x200000u 617 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT 21 618 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u 619 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22 620 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK) 621 #define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u 622 #define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24 623 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK 0x7E000000u 624 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT 25 625 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK) 626 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u 627 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31 628 /* PLL_AUDIO_SS Bit Fields */ 629 #define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK 0x7FFFu 630 #define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT 0 631 #define CCM_ANALOG_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK) 632 #define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK 0x8000u 633 #define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT 15 634 #define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK 0xFFFF0000u 635 #define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT 16 636 #define CCM_ANALOG_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK) 637 /* PLL_AUDIO_NUM Bit Fields */ 638 #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu 639 #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0 640 #define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) 641 #define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK 0xC0000000u 642 #define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT 30 643 #define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK) 644 /* PLL_AUDIO_DENOM Bit Fields */ 645 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu 646 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0 647 #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) 648 #define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK 0xC0000000u 649 #define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT 30 650 #define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK) 651 /* PLL_VIDEO Bit Fields */ 652 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu 653 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0 654 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) 655 #define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK 0x80u 656 #define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT 7 657 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK 0x100u 658 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT 8 659 #define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK 0x200u 660 #define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT 9 661 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK 0x400u 662 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT 10 663 #define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK 0x800u 664 #define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11 665 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u 666 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12 667 #define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK 0x2000u 668 #define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT 13 669 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u 670 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14 671 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) 672 #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u 673 #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16 674 #define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK 0x20000u 675 #define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17 676 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u 677 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18 678 #define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u 679 #define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19 680 #define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK) 681 #define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK 0x200000u 682 #define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT 21 683 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK 0xC00000u 684 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT 22 685 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK) 686 #define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u 687 #define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24 688 #define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK 0x7E000000u 689 #define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT 25 690 #define CCM_ANALOG_PLL_VIDEO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK) 691 #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u 692 #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31 693 /* PLL_VIDEO_SET Bit Fields */ 694 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu 695 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0 696 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) 697 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK 0x80u 698 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT 7 699 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK 0x100u 700 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8 701 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK 0x200u 702 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT 9 703 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK 0x400u 704 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10 705 #define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u 706 #define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11 707 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u 708 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12 709 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u 710 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13 711 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u 712 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14 713 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) 714 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u 715 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16 716 #define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u 717 #define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17 718 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u 719 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18 720 #define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u 721 #define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19 722 #define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK) 723 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK 0x200000u 724 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT 21 725 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u 726 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22 727 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK) 728 #define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u 729 #define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24 730 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK 0x7E000000u 731 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT 25 732 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK) 733 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u 734 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31 735 /* PLL_VIDEO_CLR Bit Fields */ 736 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu 737 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0 738 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) 739 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK 0x80u 740 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT 7 741 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK 0x100u 742 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8 743 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK 0x200u 744 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT 9 745 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK 0x400u 746 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10 747 #define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u 748 #define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11 749 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u 750 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12 751 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u 752 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13 753 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u 754 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14 755 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) 756 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u 757 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16 758 #define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u 759 #define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17 760 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u 761 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18 762 #define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u 763 #define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19 764 #define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK) 765 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK 0x200000u 766 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT 21 767 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u 768 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22 769 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK) 770 #define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u 771 #define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24 772 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK 0x7E000000u 773 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT 25 774 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK) 775 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u 776 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31 777 /* PLL_VIDEO_TOG Bit Fields */ 778 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu 779 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0 780 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) 781 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK 0x80u 782 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT 7 783 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK 0x100u 784 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8 785 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK 0x200u 786 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT 9 787 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK 0x400u 788 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10 789 #define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u 790 #define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11 791 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u 792 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12 793 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u 794 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13 795 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u 796 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14 797 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) 798 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u 799 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16 800 #define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u 801 #define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17 802 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u 803 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18 804 #define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u 805 #define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19 806 #define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK) 807 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK 0x200000u 808 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT 21 809 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u 810 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22 811 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK) 812 #define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u 813 #define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24 814 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK 0x7E000000u 815 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT 25 816 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK) 817 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u 818 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31 819 /* PLL_VIDEO_SS Bit Fields */ 820 #define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK 0x7FFFu 821 #define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT 0 822 #define CCM_ANALOG_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK) 823 #define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK 0x8000u 824 #define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT 15 825 #define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK 0xFFFF0000u 826 #define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT 16 827 #define CCM_ANALOG_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK) 828 /* PLL_VIDEO_NUM Bit Fields */ 829 #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu 830 #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0 831 #define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) 832 #define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK 0xC0000000u 833 #define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT 30 834 #define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK) 835 /* PLL_VIDEO_DENOM Bit Fields */ 836 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu 837 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0 838 #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) 839 #define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK 0xC0000000u 840 #define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT 30 841 #define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK) 842 /* CLK_MISC0 Bit Fields */ 843 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK 0x1Fu 844 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0 845 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK) 846 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK 0x20u 847 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5 848 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK 0x40u 849 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6 850 #define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK 0x80u 851 #define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT 7 852 #define CCM_ANALOG_CLK_MISC0_RSVD0_MASK 0xFFFFFF00u 853 #define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT 8 854 #define CCM_ANALOG_CLK_MISC0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK) 855 /* CLK_MISC0_SET Bit Fields */ 856 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu 857 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0 858 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK) 859 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u 860 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5 861 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u 862 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6 863 #define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u 864 #define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7 865 #define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK 0xFFFFFF00u 866 #define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT 8 867 #define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK) 868 /* CLK_MISC0_CLR Bit Fields */ 869 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu 870 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0 871 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK) 872 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u 873 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5 874 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u 875 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6 876 #define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u 877 #define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7 878 #define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK 0xFFFFFF00u 879 #define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT 8 880 #define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK) 881 /* CLK_MISC0_TOG Bit Fields */ 882 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu 883 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0 884 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK) 885 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u 886 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5 887 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u 888 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6 889 #define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u 890 #define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7 891 #define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK 0xFFFFFF00u 892 #define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT 8 893 #define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK) 894 895 /* REG_1P0A Bit Fields */ 896 #define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u 897 #define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0 898 #define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u 899 #define PMU_REG_1P0A_ENABLE_BO_SHIFT 1 900 #define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u 901 #define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2 902 #define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u 903 #define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3 904 #define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u 905 #define PMU_REG_1P0A_BO_OFFSET_SHIFT 4 906 #define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK) 907 #define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK 0x80u 908 #define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT 7 909 #define PMU_REG_1P0A_OUTPUT_TRG_MASK 0x1F00u 910 #define PMU_REG_1P0A_OUTPUT_TRG_SHIFT 8 911 #define PMU_REG_1P0A_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK) 912 #define PMU_REG_1P0A_RSVD0_MASK 0xE000u 913 #define PMU_REG_1P0A_RSVD0_SHIFT 13 914 #define PMU_REG_1P0A_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK) 915 #define PMU_REG_1P0A_BO_MASK 0x10000u 916 #define PMU_REG_1P0A_BO_SHIFT 16 917 #define PMU_REG_1P0A_OK_MASK 0x20000u 918 #define PMU_REG_1P0A_OK_SHIFT 17 919 #define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK 0x40000u 920 #define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT 18 921 #define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK 0x80000u 922 #define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT 19 923 #define PMU_REG_1P0A_REG_TEST_MASK 0xF00000u 924 #define PMU_REG_1P0A_REG_TEST_SHIFT 20 925 #define PMU_REG_1P0A_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK) 926 #define PMU_REG_1P0A_RSVD1_MASK 0xFF000000u 927 #define PMU_REG_1P0A_RSVD1_SHIFT 24 928 #define PMU_REG_1P0A_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK) 929 /* REG_1P0A_SET Bit Fields */ 930 #define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK 0x1u 931 #define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT 0 932 #define PMU_REG_1P0A_SET_ENABLE_BO_MASK 0x2u 933 #define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT 1 934 #define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK 0x4u 935 #define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT 2 936 #define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK 0x8u 937 #define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT 3 938 #define PMU_REG_1P0A_SET_BO_OFFSET_MASK 0x70u 939 #define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT 4 940 #define PMU_REG_1P0A_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK) 941 #define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK 0x80u 942 #define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT 7 943 #define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK 0x1F00u 944 #define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT 8 945 #define PMU_REG_1P0A_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK) 946 #define PMU_REG_1P0A_SET_RSVD0_MASK 0xE000u 947 #define PMU_REG_1P0A_SET_RSVD0_SHIFT 13 948 #define PMU_REG_1P0A_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK) 949 #define PMU_REG_1P0A_SET_BO_MASK 0x10000u 950 #define PMU_REG_1P0A_SET_BO_SHIFT 16 951 #define PMU_REG_1P0A_SET_OK_MASK 0x20000u 952 #define PMU_REG_1P0A_SET_OK_SHIFT 17 953 #define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u 954 #define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18 955 #define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u 956 #define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19 957 #define PMU_REG_1P0A_SET_REG_TEST_MASK 0xF00000u 958 #define PMU_REG_1P0A_SET_REG_TEST_SHIFT 20 959 #define PMU_REG_1P0A_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK) 960 #define PMU_REG_1P0A_SET_RSVD1_MASK 0xFF000000u 961 #define PMU_REG_1P0A_SET_RSVD1_SHIFT 24 962 #define PMU_REG_1P0A_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK) 963 /* REG_1P0A_CLR Bit Fields */ 964 #define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK 0x1u 965 #define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT 0 966 #define PMU_REG_1P0A_CLR_ENABLE_BO_MASK 0x2u 967 #define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT 1 968 #define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK 0x4u 969 #define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT 2 970 #define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK 0x8u 971 #define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT 3 972 #define PMU_REG_1P0A_CLR_BO_OFFSET_MASK 0x70u 973 #define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT 4 974 #define PMU_REG_1P0A_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK) 975 #define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK 0x80u 976 #define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT 7 977 #define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK 0x1F00u 978 #define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT 8 979 #define PMU_REG_1P0A_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK) 980 #define PMU_REG_1P0A_CLR_RSVD0_MASK 0xE000u 981 #define PMU_REG_1P0A_CLR_RSVD0_SHIFT 13 982 #define PMU_REG_1P0A_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK) 983 #define PMU_REG_1P0A_CLR_BO_MASK 0x10000u 984 #define PMU_REG_1P0A_CLR_BO_SHIFT 16 985 #define PMU_REG_1P0A_CLR_OK_MASK 0x20000u 986 #define PMU_REG_1P0A_CLR_OK_SHIFT 17 987 #define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u 988 #define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18 989 #define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u 990 #define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19 991 #define PMU_REG_1P0A_CLR_REG_TEST_MASK 0xF00000u 992 #define PMU_REG_1P0A_CLR_REG_TEST_SHIFT 20 993 #define PMU_REG_1P0A_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK) 994 #define PMU_REG_1P0A_CLR_RSVD1_MASK 0xFF000000u 995 #define PMU_REG_1P0A_CLR_RSVD1_SHIFT 24 996 #define PMU_REG_1P0A_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK) 997 /* REG_1P0A_TOG Bit Fields */ 998 #define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK 0x1u 999 #define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT 0 1000 #define PMU_REG_1P0A_TOG_ENABLE_BO_MASK 0x2u 1001 #define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT 1 1002 #define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK 0x4u 1003 #define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT 2 1004 #define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK 0x8u 1005 #define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT 3 1006 #define PMU_REG_1P0A_TOG_BO_OFFSET_MASK 0x70u 1007 #define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT 4 1008 #define PMU_REG_1P0A_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK) 1009 #define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK 0x80u 1010 #define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT 7 1011 #define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK 0x1F00u 1012 #define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT 8 1013 #define PMU_REG_1P0A_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK) 1014 #define PMU_REG_1P0A_TOG_RSVD0_MASK 0xE000u 1015 #define PMU_REG_1P0A_TOG_RSVD0_SHIFT 13 1016 #define PMU_REG_1P0A_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK) 1017 #define PMU_REG_1P0A_TOG_BO_MASK 0x10000u 1018 #define PMU_REG_1P0A_TOG_BO_SHIFT 16 1019 #define PMU_REG_1P0A_TOG_OK_MASK 0x20000u 1020 #define PMU_REG_1P0A_TOG_OK_SHIFT 17 1021 #define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u 1022 #define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18 1023 #define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u 1024 #define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19 1025 #define PMU_REG_1P0A_TOG_REG_TEST_MASK 0xF00000u 1026 #define PMU_REG_1P0A_TOG_REG_TEST_SHIFT 20 1027 #define PMU_REG_1P0A_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK) 1028 #define PMU_REG_1P0A_TOG_RSVD1_MASK 0xFF000000u 1029 #define PMU_REG_1P0A_TOG_RSVD1_SHIFT 24 1030 #define PMU_REG_1P0A_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK) 1031 /* REG_1P0D Bit Fields */ 1032 #define PMU_REG_1P0D_ENABLE_LINREG_MASK 0x1u 1033 #define PMU_REG_1P0D_ENABLE_LINREG_SHIFT 0 1034 #define PMU_REG_1P0D_ENABLE_BO_MASK 0x2u 1035 #define PMU_REG_1P0D_ENABLE_BO_SHIFT 1 1036 #define PMU_REG_1P0D_ENABLE_ILIMIT_MASK 0x4u 1037 #define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT 2 1038 #define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK 0x8u 1039 #define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT 3 1040 #define PMU_REG_1P0D_BO_OFFSET_MASK 0x70u 1041 #define PMU_REG_1P0D_BO_OFFSET_SHIFT 4 1042 #define PMU_REG_1P0D_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK) 1043 #define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK 0x80u 1044 #define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT 7 1045 #define PMU_REG_1P0D_OUTPUT_TRG_MASK 0x1F00u 1046 #define PMU_REG_1P0D_OUTPUT_TRG_SHIFT 8 1047 #define PMU_REG_1P0D_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK) 1048 #define PMU_REG_1P0D_RSVD0_MASK 0xE000u 1049 #define PMU_REG_1P0D_RSVD0_SHIFT 13 1050 #define PMU_REG_1P0D_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK) 1051 #define PMU_REG_1P0D_BO_MASK 0x10000u 1052 #define PMU_REG_1P0D_BO_SHIFT 16 1053 #define PMU_REG_1P0D_OK_MASK 0x20000u 1054 #define PMU_REG_1P0D_OK_SHIFT 17 1055 #define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK 0x40000u 1056 #define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT 18 1057 #define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK 0x80000u 1058 #define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT 19 1059 #define PMU_REG_1P0D_REG_TEST_MASK 0xF00000u 1060 #define PMU_REG_1P0D_REG_TEST_SHIFT 20 1061 #define PMU_REG_1P0D_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK) 1062 #define PMU_REG_1P0D_RSVD1_MASK 0x7F000000u 1063 #define PMU_REG_1P0D_RSVD1_SHIFT 24 1064 #define PMU_REG_1P0D_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK) 1065 #define PMU_REG_1P0D_OVERRIDE_MASK 0x80000000u 1066 #define PMU_REG_1P0D_OVERRIDE_SHIFT 31 1067 /* REG_1P0D_SET Bit Fields */ 1068 #define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK 0x1u 1069 #define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT 0 1070 #define PMU_REG_1P0D_SET_ENABLE_BO_MASK 0x2u 1071 #define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT 1 1072 #define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK 0x4u 1073 #define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT 2 1074 #define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK 0x8u 1075 #define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT 3 1076 #define PMU_REG_1P0D_SET_BO_OFFSET_MASK 0x70u 1077 #define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT 4 1078 #define PMU_REG_1P0D_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK) 1079 #define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK 0x80u 1080 #define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT 7 1081 #define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK 0x1F00u 1082 #define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT 8 1083 #define PMU_REG_1P0D_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK) 1084 #define PMU_REG_1P0D_SET_RSVD0_MASK 0xE000u 1085 #define PMU_REG_1P0D_SET_RSVD0_SHIFT 13 1086 #define PMU_REG_1P0D_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK) 1087 #define PMU_REG_1P0D_SET_BO_MASK 0x10000u 1088 #define PMU_REG_1P0D_SET_BO_SHIFT 16 1089 #define PMU_REG_1P0D_SET_OK_MASK 0x20000u 1090 #define PMU_REG_1P0D_SET_OK_SHIFT 17 1091 #define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u 1092 #define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18 1093 #define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u 1094 #define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19 1095 #define PMU_REG_1P0D_SET_REG_TEST_MASK 0xF00000u 1096 #define PMU_REG_1P0D_SET_REG_TEST_SHIFT 20 1097 #define PMU_REG_1P0D_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK) 1098 #define PMU_REG_1P0D_SET_RSVD1_MASK 0x7F000000u 1099 #define PMU_REG_1P0D_SET_RSVD1_SHIFT 24 1100 #define PMU_REG_1P0D_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK) 1101 #define PMU_REG_1P0D_SET_OVERRIDE_MASK 0x80000000u 1102 #define PMU_REG_1P0D_SET_OVERRIDE_SHIFT 31 1103 /* REG_1P0D_CLR Bit Fields */ 1104 #define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK 0x1u 1105 #define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT 0 1106 #define PMU_REG_1P0D_CLR_ENABLE_BO_MASK 0x2u 1107 #define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT 1 1108 #define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK 0x4u 1109 #define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT 2 1110 #define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK 0x8u 1111 #define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT 3 1112 #define PMU_REG_1P0D_CLR_BO_OFFSET_MASK 0x70u 1113 #define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT 4 1114 #define PMU_REG_1P0D_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK) 1115 #define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK 0x80u 1116 #define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT 7 1117 #define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK 0x1F00u 1118 #define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT 8 1119 #define PMU_REG_1P0D_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK) 1120 #define PMU_REG_1P0D_CLR_RSVD0_MASK 0xE000u 1121 #define PMU_REG_1P0D_CLR_RSVD0_SHIFT 13 1122 #define PMU_REG_1P0D_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK) 1123 #define PMU_REG_1P0D_CLR_BO_MASK 0x10000u 1124 #define PMU_REG_1P0D_CLR_BO_SHIFT 16 1125 #define PMU_REG_1P0D_CLR_OK_MASK 0x20000u 1126 #define PMU_REG_1P0D_CLR_OK_SHIFT 17 1127 #define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u 1128 #define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18 1129 #define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u 1130 #define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19 1131 #define PMU_REG_1P0D_CLR_REG_TEST_MASK 0xF00000u 1132 #define PMU_REG_1P0D_CLR_REG_TEST_SHIFT 20 1133 #define PMU_REG_1P0D_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK) 1134 #define PMU_REG_1P0D_CLR_RSVD1_MASK 0x7F000000u 1135 #define PMU_REG_1P0D_CLR_RSVD1_SHIFT 24 1136 #define PMU_REG_1P0D_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK) 1137 #define PMU_REG_1P0D_CLR_OVERRIDE_MASK 0x80000000u 1138 #define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT 31 1139 /* REG_1P0D_TOG Bit Fields */ 1140 #define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK 0x1u 1141 #define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT 0 1142 #define PMU_REG_1P0D_TOG_ENABLE_BO_MASK 0x2u 1143 #define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT 1 1144 #define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK 0x4u 1145 #define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT 2 1146 #define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK 0x8u 1147 #define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT 3 1148 #define PMU_REG_1P0D_TOG_BO_OFFSET_MASK 0x70u 1149 #define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT 4 1150 #define PMU_REG_1P0D_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK) 1151 #define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK 0x80u 1152 #define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT 7 1153 #define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK 0x1F00u 1154 #define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT 8 1155 #define PMU_REG_1P0D_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK) 1156 #define PMU_REG_1P0D_TOG_RSVD0_MASK 0xE000u 1157 #define PMU_REG_1P0D_TOG_RSVD0_SHIFT 13 1158 #define PMU_REG_1P0D_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK) 1159 #define PMU_REG_1P0D_TOG_BO_MASK 0x10000u 1160 #define PMU_REG_1P0D_TOG_BO_SHIFT 16 1161 #define PMU_REG_1P0D_TOG_OK_MASK 0x20000u 1162 #define PMU_REG_1P0D_TOG_OK_SHIFT 17 1163 #define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u 1164 #define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18 1165 #define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u 1166 #define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19 1167 #define PMU_REG_1P0D_TOG_REG_TEST_MASK 0xF00000u 1168 #define PMU_REG_1P0D_TOG_REG_TEST_SHIFT 20 1169 #define PMU_REG_1P0D_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK) 1170 #define PMU_REG_1P0D_TOG_RSVD1_MASK 0x7F000000u 1171 #define PMU_REG_1P0D_TOG_RSVD1_SHIFT 24 1172 #define PMU_REG_1P0D_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK) 1173 #define PMU_REG_1P0D_TOG_OVERRIDE_MASK 0x80000000u 1174 #define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT 31 1175 /* REG_HSIC_1P2 Bit Fields */ 1176 #define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK 0x1u 1177 #define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT 0 1178 #define PMU_REG_HSIC_1P2_ENABLE_BO_MASK 0x2u 1179 #define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT 1 1180 #define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK 0x4u 1181 #define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT 2 1182 #define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK 0x8u 1183 #define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT 3 1184 #define PMU_REG_HSIC_1P2_BO_OFFSET_MASK 0x70u 1185 #define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT 4 1186 #define PMU_REG_HSIC_1P2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK) 1187 #define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK 0x80u 1188 #define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT 7 1189 #define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK 0x1F00u 1190 #define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT 8 1191 #define PMU_REG_HSIC_1P2_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK) 1192 #define PMU_REG_HSIC_1P2_RSVD0_MASK 0xE000u 1193 #define PMU_REG_HSIC_1P2_RSVD0_SHIFT 13 1194 #define PMU_REG_HSIC_1P2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK) 1195 #define PMU_REG_HSIC_1P2_BO_MASK 0x10000u 1196 #define PMU_REG_HSIC_1P2_BO_SHIFT 16 1197 #define PMU_REG_HSIC_1P2_OK_MASK 0x20000u 1198 #define PMU_REG_HSIC_1P2_OK_SHIFT 17 1199 #define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u 1200 #define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18 1201 #define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u 1202 #define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19 1203 #define PMU_REG_HSIC_1P2_REG_TEST_MASK 0xF00000u 1204 #define PMU_REG_HSIC_1P2_REG_TEST_SHIFT 20 1205 #define PMU_REG_HSIC_1P2_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK) 1206 #define PMU_REG_HSIC_1P2_RSVD1_MASK 0x7F000000u 1207 #define PMU_REG_HSIC_1P2_RSVD1_SHIFT 24 1208 #define PMU_REG_HSIC_1P2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK) 1209 #define PMU_REG_HSIC_1P2_OVERRIDE_MASK 0x80000000u 1210 #define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT 31 1211 /* REG_HSIC_1P2_SET Bit Fields */ 1212 #define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK 0x1u 1213 #define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0 1214 #define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK 0x2u 1215 #define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT 1 1216 #define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK 0x4u 1217 #define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2 1218 #define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u 1219 #define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3 1220 #define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK 0x70u 1221 #define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT 4 1222 #define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK) 1223 #define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u 1224 #define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7 1225 #define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK 0x1F00u 1226 #define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT 8 1227 #define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK) 1228 #define PMU_REG_HSIC_1P2_SET_RSVD0_MASK 0xE000u 1229 #define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT 13 1230 #define PMU_REG_HSIC_1P2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK) 1231 #define PMU_REG_HSIC_1P2_SET_BO_MASK 0x10000u 1232 #define PMU_REG_HSIC_1P2_SET_BO_SHIFT 16 1233 #define PMU_REG_HSIC_1P2_SET_OK_MASK 0x20000u 1234 #define PMU_REG_HSIC_1P2_SET_OK_SHIFT 17 1235 #define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u 1236 #define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18 1237 #define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u 1238 #define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19 1239 #define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK 0xF00000u 1240 #define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT 20 1241 #define PMU_REG_HSIC_1P2_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK) 1242 #define PMU_REG_HSIC_1P2_SET_RSVD1_MASK 0x7F000000u 1243 #define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT 24 1244 #define PMU_REG_HSIC_1P2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK) 1245 #define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK 0x80000000u 1246 #define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT 31 1247 /* REG_HSIC_1P2_CLR Bit Fields */ 1248 #define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK 0x1u 1249 #define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0 1250 #define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK 0x2u 1251 #define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT 1 1252 #define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK 0x4u 1253 #define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2 1254 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u 1255 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3 1256 #define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK 0x70u 1257 #define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT 4 1258 #define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK) 1259 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u 1260 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7 1261 #define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK 0x1F00u 1262 #define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT 8 1263 #define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK) 1264 #define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK 0xE000u 1265 #define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT 13 1266 #define PMU_REG_HSIC_1P2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK) 1267 #define PMU_REG_HSIC_1P2_CLR_BO_MASK 0x10000u 1268 #define PMU_REG_HSIC_1P2_CLR_BO_SHIFT 16 1269 #define PMU_REG_HSIC_1P2_CLR_OK_MASK 0x20000u 1270 #define PMU_REG_HSIC_1P2_CLR_OK_SHIFT 17 1271 #define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u 1272 #define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18 1273 #define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u 1274 #define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19 1275 #define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK 0xF00000u 1276 #define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT 20 1277 #define PMU_REG_HSIC_1P2_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK) 1278 #define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK 0x7F000000u 1279 #define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT 24 1280 #define PMU_REG_HSIC_1P2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK) 1281 #define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK 0x80000000u 1282 #define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT 31 1283 /* REG_HSIC_1P2_TOG Bit Fields */ 1284 #define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK 0x1u 1285 #define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0 1286 #define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK 0x2u 1287 #define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT 1 1288 #define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK 0x4u 1289 #define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2 1290 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u 1291 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3 1292 #define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK 0x70u 1293 #define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT 4 1294 #define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK) 1295 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u 1296 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7 1297 #define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK 0x1F00u 1298 #define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT 8 1299 #define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK) 1300 #define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK 0xE000u 1301 #define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT 13 1302 #define PMU_REG_HSIC_1P2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK) 1303 #define PMU_REG_HSIC_1P2_TOG_BO_MASK 0x10000u 1304 #define PMU_REG_HSIC_1P2_TOG_BO_SHIFT 16 1305 #define PMU_REG_HSIC_1P2_TOG_OK_MASK 0x20000u 1306 #define PMU_REG_HSIC_1P2_TOG_OK_SHIFT 17 1307 #define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u 1308 #define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18 1309 #define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u 1310 #define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19 1311 #define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK 0xF00000u 1312 #define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT 20 1313 #define PMU_REG_HSIC_1P2_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK) 1314 #define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK 0x7F000000u 1315 #define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT 24 1316 #define PMU_REG_HSIC_1P2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK) 1317 #define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK 0x80000000u 1318 #define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT 31 1319 /* REG_LPSR_1P0 Bit Fields */ 1320 #define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK 0x1u 1321 #define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT 0 1322 #define PMU_REG_LPSR_1P0_ENABLE_BO_MASK 0x2u 1323 #define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT 1 1324 #define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK 0x4u 1325 #define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT 2 1326 #define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK 0x8u 1327 #define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT 3 1328 #define PMU_REG_LPSR_1P0_BO_OFFSET_MASK 0x70u 1329 #define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT 4 1330 #define PMU_REG_LPSR_1P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK) 1331 #define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK 0x80u 1332 #define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT 7 1333 #define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK 0x1F00u 1334 #define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT 8 1335 #define PMU_REG_LPSR_1P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK) 1336 #define PMU_REG_LPSR_1P0_RSVD0_MASK 0xE000u 1337 #define PMU_REG_LPSR_1P0_RSVD0_SHIFT 13 1338 #define PMU_REG_LPSR_1P0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK) 1339 #define PMU_REG_LPSR_1P0_BO_MASK 0x10000u 1340 #define PMU_REG_LPSR_1P0_BO_SHIFT 16 1341 #define PMU_REG_LPSR_1P0_OK_MASK 0x20000u 1342 #define PMU_REG_LPSR_1P0_OK_SHIFT 17 1343 #define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u 1344 #define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18 1345 #define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u 1346 #define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19 1347 #define PMU_REG_LPSR_1P0_REG_TEST_MASK 0xF00000u 1348 #define PMU_REG_LPSR_1P0_REG_TEST_SHIFT 20 1349 #define PMU_REG_LPSR_1P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK) 1350 #define PMU_REG_LPSR_1P0_RSVD1_MASK 0xFF000000u 1351 #define PMU_REG_LPSR_1P0_RSVD1_SHIFT 24 1352 #define PMU_REG_LPSR_1P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK) 1353 /* REG_LPSR_1P0_SET Bit Fields */ 1354 #define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK 0x1u 1355 #define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0 1356 #define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK 0x2u 1357 #define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT 1 1358 #define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK 0x4u 1359 #define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2 1360 #define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u 1361 #define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3 1362 #define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK 0x70u 1363 #define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT 4 1364 #define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK) 1365 #define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u 1366 #define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7 1367 #define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK 0x1F00u 1368 #define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT 8 1369 #define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK) 1370 #define PMU_REG_LPSR_1P0_SET_RSVD0_MASK 0xE000u 1371 #define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT 13 1372 #define PMU_REG_LPSR_1P0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK) 1373 #define PMU_REG_LPSR_1P0_SET_BO_MASK 0x10000u 1374 #define PMU_REG_LPSR_1P0_SET_BO_SHIFT 16 1375 #define PMU_REG_LPSR_1P0_SET_OK_MASK 0x20000u 1376 #define PMU_REG_LPSR_1P0_SET_OK_SHIFT 17 1377 #define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u 1378 #define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18 1379 #define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u 1380 #define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19 1381 #define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK 0xF00000u 1382 #define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT 20 1383 #define PMU_REG_LPSR_1P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK) 1384 #define PMU_REG_LPSR_1P0_SET_RSVD1_MASK 0xFF000000u 1385 #define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT 24 1386 #define PMU_REG_LPSR_1P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK) 1387 /* REG_LPSR_1P0_CLR Bit Fields */ 1388 #define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK 0x1u 1389 #define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0 1390 #define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK 0x2u 1391 #define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT 1 1392 #define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK 0x4u 1393 #define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2 1394 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u 1395 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3 1396 #define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK 0x70u 1397 #define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT 4 1398 #define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK) 1399 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u 1400 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7 1401 #define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK 0x1F00u 1402 #define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT 8 1403 #define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK) 1404 #define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK 0xE000u 1405 #define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT 13 1406 #define PMU_REG_LPSR_1P0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK) 1407 #define PMU_REG_LPSR_1P0_CLR_BO_MASK 0x10000u 1408 #define PMU_REG_LPSR_1P0_CLR_BO_SHIFT 16 1409 #define PMU_REG_LPSR_1P0_CLR_OK_MASK 0x20000u 1410 #define PMU_REG_LPSR_1P0_CLR_OK_SHIFT 17 1411 #define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u 1412 #define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18 1413 #define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u 1414 #define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19 1415 #define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK 0xF00000u 1416 #define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT 20 1417 #define PMU_REG_LPSR_1P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK) 1418 #define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK 0xFF000000u 1419 #define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT 24 1420 #define PMU_REG_LPSR_1P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK) 1421 /* REG_LPSR_1P0_TOG Bit Fields */ 1422 #define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK 0x1u 1423 #define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0 1424 #define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK 0x2u 1425 #define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT 1 1426 #define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK 0x4u 1427 #define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2 1428 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u 1429 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3 1430 #define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK 0x70u 1431 #define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT 4 1432 #define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK) 1433 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u 1434 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7 1435 #define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK 0x1F00u 1436 #define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT 8 1437 #define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK) 1438 #define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK 0xE000u 1439 #define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT 13 1440 #define PMU_REG_LPSR_1P0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK) 1441 #define PMU_REG_LPSR_1P0_TOG_BO_MASK 0x10000u 1442 #define PMU_REG_LPSR_1P0_TOG_BO_SHIFT 16 1443 #define PMU_REG_LPSR_1P0_TOG_OK_MASK 0x20000u 1444 #define PMU_REG_LPSR_1P0_TOG_OK_SHIFT 17 1445 #define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u 1446 #define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18 1447 #define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u 1448 #define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19 1449 #define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK 0xF00000u 1450 #define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT 20 1451 #define PMU_REG_LPSR_1P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK) 1452 #define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u 1453 #define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24 1454 #define PMU_REG_LPSR_1P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK) 1455 /* REG_3P0 Bit Fields */ 1456 #define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u 1457 #define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0 1458 #define PMU_REG_3P0_ENABLE_BO_MASK 0x2u 1459 #define PMU_REG_3P0_ENABLE_BO_SHIFT 1 1460 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u 1461 #define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2 1462 #define PMU_REG_3P0_RSVD0_MASK 0x8u 1463 #define PMU_REG_3P0_RSVD0_SHIFT 3 1464 #define PMU_REG_3P0_BO_OFFSET_MASK 0x70u 1465 #define PMU_REG_3P0_BO_OFFSET_SHIFT 4 1466 #define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK) 1467 #define PMU_REG_3P0_VBUS_SEL_MASK 0x80u 1468 #define PMU_REG_3P0_VBUS_SEL_SHIFT 7 1469 #define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u 1470 #define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8 1471 #define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK) 1472 #define PMU_REG_3P0_RSVD1_MASK 0xE000u 1473 #define PMU_REG_3P0_RSVD1_SHIFT 13 1474 #define PMU_REG_3P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK) 1475 #define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u 1476 #define PMU_REG_3P0_BO_VDD3P0_SHIFT 16 1477 #define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u 1478 #define PMU_REG_3P0_OK_VDD3P0_SHIFT 17 1479 #define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u 1480 #define PMU_REG_3P0_REG_TEST_SHIFT 18 1481 #define PMU_REG_3P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK) 1482 #define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u 1483 #define PMU_REG_3P0_RSVD2_SHIFT 22 1484 #define PMU_REG_3P0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK) 1485 /* REG_3P0_SET Bit Fields */ 1486 #define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u 1487 #define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0 1488 #define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u 1489 #define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1 1490 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u 1491 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2 1492 #define PMU_REG_3P0_SET_RSVD0_MASK 0x8u 1493 #define PMU_REG_3P0_SET_RSVD0_SHIFT 3 1494 #define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u 1495 #define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4 1496 #define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK) 1497 #define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u 1498 #define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7 1499 #define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u 1500 #define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8 1501 #define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK) 1502 #define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u 1503 #define PMU_REG_3P0_SET_RSVD1_SHIFT 13 1504 #define PMU_REG_3P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK) 1505 #define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u 1506 #define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16 1507 #define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u 1508 #define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17 1509 #define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u 1510 #define PMU_REG_3P0_SET_REG_TEST_SHIFT 18 1511 #define PMU_REG_3P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK) 1512 #define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u 1513 #define PMU_REG_3P0_SET_RSVD2_SHIFT 22 1514 #define PMU_REG_3P0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK) 1515 /* REG_3P0_CLR Bit Fields */ 1516 #define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u 1517 #define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0 1518 #define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u 1519 #define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1 1520 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u 1521 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2 1522 #define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u 1523 #define PMU_REG_3P0_CLR_RSVD0_SHIFT 3 1524 #define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u 1525 #define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4 1526 #define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK) 1527 #define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u 1528 #define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7 1529 #define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u 1530 #define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8 1531 #define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) 1532 #define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u 1533 #define PMU_REG_3P0_CLR_RSVD1_SHIFT 13 1534 #define PMU_REG_3P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK) 1535 #define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u 1536 #define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16 1537 #define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u 1538 #define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17 1539 #define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u 1540 #define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18 1541 #define PMU_REG_3P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK) 1542 #define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u 1543 #define PMU_REG_3P0_CLR_RSVD2_SHIFT 22 1544 #define PMU_REG_3P0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK) 1545 /* REG_3P0_TOG Bit Fields */ 1546 #define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u 1547 #define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0 1548 #define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u 1549 #define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1 1550 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u 1551 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2 1552 #define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u 1553 #define PMU_REG_3P0_TOG_RSVD0_SHIFT 3 1554 #define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u 1555 #define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4 1556 #define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK) 1557 #define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u 1558 #define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7 1559 #define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u 1560 #define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8 1561 #define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) 1562 #define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u 1563 #define PMU_REG_3P0_TOG_RSVD1_SHIFT 13 1564 #define PMU_REG_3P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK) 1565 #define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u 1566 #define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16 1567 #define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u 1568 #define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17 1569 #define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u 1570 #define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18 1571 #define PMU_REG_3P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK) 1572 #define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u 1573 #define PMU_REG_3P0_TOG_RSVD2_SHIFT 22 1574 #define PMU_REG_3P0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK) 1575 /* REF Bit Fields */ 1576 #define PMU_REF_REFTOP_PWD_MASK 0x1u 1577 #define PMU_REF_REFTOP_PWD_SHIFT 0 1578 #define PMU_REF_REFTOP_PWDVBGUP_MASK 0x2u 1579 #define PMU_REF_REFTOP_PWDVBGUP_SHIFT 1 1580 #define PMU_REF_REFTOP_LOWPOWER_MASK 0x4u 1581 #define PMU_REF_REFTOP_LOWPOWER_SHIFT 2 1582 #define PMU_REF_REFTOP_SELFBIASOFF_MASK 0x8u 1583 #define PMU_REF_REFTOP_SELFBIASOFF_SHIFT 3 1584 #define PMU_REF_REFTOP_VBGADJ_MASK 0x70u 1585 #define PMU_REF_REFTOP_VBGADJ_SHIFT 4 1586 #define PMU_REF_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK) 1587 #define PMU_REF_REFTOP_VBGUP_MASK 0x80u 1588 #define PMU_REF_REFTOP_VBGUP_SHIFT 7 1589 #define PMU_REF_REFTOP_BIAS_TST_MASK 0x300u 1590 #define PMU_REF_REFTOP_BIAS_TST_SHIFT 8 1591 #define PMU_REF_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK) 1592 #define PMU_REF_LPBG_SEL_MASK 0x400u 1593 #define PMU_REF_LPBG_SEL_SHIFT 10 1594 #define PMU_REF_LPBG_TEST_MASK 0x800u 1595 #define PMU_REF_LPBG_TEST_SHIFT 11 1596 #define PMU_REF_REFTOP_IBIAS_OFF_MASK 0x1000u 1597 #define PMU_REF_REFTOP_IBIAS_OFF_SHIFT 12 1598 #define PMU_REF_REFTOP_LINREGREF_EN_MASK 0x2000u 1599 #define PMU_REF_REFTOP_LINREGREF_EN_SHIFT 13 1600 #define PMU_REF_RSVD1_MASK 0xFFFFC000u 1601 #define PMU_REF_RSVD1_SHIFT 14 1602 #define PMU_REF_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK) 1603 /* REF_SET Bit Fields */ 1604 #define PMU_REF_SET_REFTOP_PWD_MASK 0x1u 1605 #define PMU_REF_SET_REFTOP_PWD_SHIFT 0 1606 #define PMU_REF_SET_REFTOP_PWDVBGUP_MASK 0x2u 1607 #define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT 1 1608 #define PMU_REF_SET_REFTOP_LOWPOWER_MASK 0x4u 1609 #define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT 2 1610 #define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK 0x8u 1611 #define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT 3 1612 #define PMU_REF_SET_REFTOP_VBGADJ_MASK 0x70u 1613 #define PMU_REF_SET_REFTOP_VBGADJ_SHIFT 4 1614 #define PMU_REF_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK) 1615 #define PMU_REF_SET_REFTOP_VBGUP_MASK 0x80u 1616 #define PMU_REF_SET_REFTOP_VBGUP_SHIFT 7 1617 #define PMU_REF_SET_REFTOP_BIAS_TST_MASK 0x300u 1618 #define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT 8 1619 #define PMU_REF_SET_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK) 1620 #define PMU_REF_SET_LPBG_SEL_MASK 0x400u 1621 #define PMU_REF_SET_LPBG_SEL_SHIFT 10 1622 #define PMU_REF_SET_LPBG_TEST_MASK 0x800u 1623 #define PMU_REF_SET_LPBG_TEST_SHIFT 11 1624 #define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK 0x1000u 1625 #define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT 12 1626 #define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK 0x2000u 1627 #define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT 13 1628 #define PMU_REF_SET_RSVD1_MASK 0xFFFFC000u 1629 #define PMU_REF_SET_RSVD1_SHIFT 14 1630 #define PMU_REF_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK) 1631 /* REF_CLR Bit Fields */ 1632 #define PMU_REF_CLR_REFTOP_PWD_MASK 0x1u 1633 #define PMU_REF_CLR_REFTOP_PWD_SHIFT 0 1634 #define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK 0x2u 1635 #define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT 1 1636 #define PMU_REF_CLR_REFTOP_LOWPOWER_MASK 0x4u 1637 #define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT 2 1638 #define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK 0x8u 1639 #define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT 3 1640 #define PMU_REF_CLR_REFTOP_VBGADJ_MASK 0x70u 1641 #define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT 4 1642 #define PMU_REF_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK) 1643 #define PMU_REF_CLR_REFTOP_VBGUP_MASK 0x80u 1644 #define PMU_REF_CLR_REFTOP_VBGUP_SHIFT 7 1645 #define PMU_REF_CLR_REFTOP_BIAS_TST_MASK 0x300u 1646 #define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT 8 1647 #define PMU_REF_CLR_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK) 1648 #define PMU_REF_CLR_LPBG_SEL_MASK 0x400u 1649 #define PMU_REF_CLR_LPBG_SEL_SHIFT 10 1650 #define PMU_REF_CLR_LPBG_TEST_MASK 0x800u 1651 #define PMU_REF_CLR_LPBG_TEST_SHIFT 11 1652 #define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK 0x1000u 1653 #define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT 12 1654 #define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK 0x2000u 1655 #define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT 13 1656 #define PMU_REF_CLR_RSVD1_MASK 0xFFFFC000u 1657 #define PMU_REF_CLR_RSVD1_SHIFT 14 1658 #define PMU_REF_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK) 1659 /* REF_TOG Bit Fields */ 1660 #define PMU_REF_TOG_REFTOP_PWD_MASK 0x1u 1661 #define PMU_REF_TOG_REFTOP_PWD_SHIFT 0 1662 #define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK 0x2u 1663 #define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT 1 1664 #define PMU_REF_TOG_REFTOP_LOWPOWER_MASK 0x4u 1665 #define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT 2 1666 #define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK 0x8u 1667 #define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT 3 1668 #define PMU_REF_TOG_REFTOP_VBGADJ_MASK 0x70u 1669 #define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT 4 1670 #define PMU_REF_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK) 1671 #define PMU_REF_TOG_REFTOP_VBGUP_MASK 0x80u 1672 #define PMU_REF_TOG_REFTOP_VBGUP_SHIFT 7 1673 #define PMU_REF_TOG_REFTOP_BIAS_TST_MASK 0x300u 1674 #define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT 8 1675 #define PMU_REF_TOG_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK) 1676 #define PMU_REF_TOG_LPBG_SEL_MASK 0x400u 1677 #define PMU_REF_TOG_LPBG_SEL_SHIFT 10 1678 #define PMU_REF_TOG_LPBG_TEST_MASK 0x800u 1679 #define PMU_REF_TOG_LPBG_TEST_SHIFT 11 1680 #define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK 0x1000u 1681 #define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT 12 1682 #define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK 0x2000u 1683 #define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT 13 1684 #define PMU_REF_TOG_RSVD1_MASK 0xFFFFC000u 1685 #define PMU_REF_TOG_RSVD1_SHIFT 14 1686 #define PMU_REF_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK) 1687 /* LOWPWR_CTRL Bit Fields */ 1688 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK 0x3u 1689 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT 0 1690 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK) 1691 #define PMU_LOWPWR_CTRL_RSVD0_MASK 0xFCu 1692 #define PMU_LOWPWR_CTRL_RSVD0_SHIFT 2 1693 #define PMU_LOWPWR_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK) 1694 #define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u 1695 #define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8 1696 #define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u 1697 #define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9 1698 #define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u 1699 #define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10 1700 #define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u 1701 #define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11 1702 #define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x1000u 1703 #define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 12 1704 #define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x2000u 1705 #define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 13 1706 #define PMU_LOWPWR_CTRL_CONTROL0_MASK 0xFFC000u 1707 #define PMU_LOWPWR_CTRL_CONTROL0_SHIFT 14 1708 #define PMU_LOWPWR_CTRL_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK) 1709 #define PMU_LOWPWR_CTRL_CONTROL1_MASK 0xFF000000u 1710 #define PMU_LOWPWR_CTRL_CONTROL1_SHIFT 24 1711 #define PMU_LOWPWR_CTRL_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK) 1712 /* LOWPWR_CTRL_SET Bit Fields */ 1713 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u 1714 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0 1715 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK) 1716 #define PMU_LOWPWR_CTRL_SET_RSVD0_MASK 0xFCu 1717 #define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT 2 1718 #define PMU_LOWPWR_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK) 1719 #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u 1720 #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8 1721 #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u 1722 #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9 1723 #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u 1724 #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10 1725 #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u 1726 #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11 1727 #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x1000u 1728 #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 12 1729 #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x2000u 1730 #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 13 1731 #define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK 0xFFC000u 1732 #define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT 14 1733 #define PMU_LOWPWR_CTRL_SET_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK) 1734 #define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK 0xFF000000u 1735 #define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT 24 1736 #define PMU_LOWPWR_CTRL_SET_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK) 1737 /* LOWPWR_CTRL_CLR Bit Fields */ 1738 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u 1739 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0 1740 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK) 1741 #define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK 0xFCu 1742 #define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT 2 1743 #define PMU_LOWPWR_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK) 1744 #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u 1745 #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8 1746 #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u 1747 #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9 1748 #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u 1749 #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10 1750 #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u 1751 #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11 1752 #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x1000u 1753 #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 12 1754 #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x2000u 1755 #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 13 1756 #define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK 0xFFC000u 1757 #define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT 14 1758 #define PMU_LOWPWR_CTRL_CLR_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK) 1759 #define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK 0xFF000000u 1760 #define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT 24 1761 #define PMU_LOWPWR_CTRL_CLR_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK) 1762 /* LOWPWR_CTRL_TOG Bit Fields */ 1763 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u 1764 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0 1765 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK) 1766 #define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK 0xFCu 1767 #define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT 2 1768 #define PMU_LOWPWR_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK) 1769 #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u 1770 #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8 1771 #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u 1772 #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9 1773 #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u 1774 #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10 1775 #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u 1776 #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11 1777 #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x1000u 1778 #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 12 1779 #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x2000u 1780 #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 13 1781 #define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK 0xFFC000u 1782 #define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT 14 1783 #define PMU_LOWPWR_CTRL_TOG_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK) 1784 #define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK 0xFF000000u 1785 #define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24 1786 #define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK) 1787 1788 1789 /* HW_ANADIG_TEMPSENSE0 Bit Fields */ 1790 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu 1791 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 1792 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK) 1793 #define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u 1794 #define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9 1795 #define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK) 1796 #define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u 1797 #define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18 1798 #define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK) 1799 #define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK 0xF8000000u 1800 #define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27 1801 #define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK) 1802 /* HW_ANADIG_TEMPSENSE0_SET Bit Fields */ 1803 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu 1804 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0 1805 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK) 1806 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u 1807 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9 1808 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK) 1809 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u 1810 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18 1811 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK) 1812 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u 1813 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27 1814 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK) 1815 /* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */ 1816 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu 1817 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0 1818 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK) 1819 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u 1820 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9 1821 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK) 1822 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u 1823 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18 1824 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK) 1825 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u 1826 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27 1827 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK) 1828 /* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */ 1829 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu 1830 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0 1831 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK) 1832 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u 1833 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9 1834 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK) 1835 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u 1836 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18 1837 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK) 1838 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u 1839 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27 1840 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK) 1841 /* HW_ANADIG_TEMPSENSE1 Bit Fields */ 1842 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu 1843 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0 1844 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) 1845 #define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u 1846 #define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9 1847 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u 1848 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10 1849 #define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u 1850 #define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11 1851 #define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK 0xF000u 1852 #define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12 1853 #define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK) 1854 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u 1855 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16 1856 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK) 1857 /* HW_ANADIG_TEMPSENSE1_SET Bit Fields */ 1858 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu 1859 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0 1860 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK) 1861 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u 1862 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9 1863 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u 1864 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10 1865 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u 1866 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11 1867 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u 1868 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12 1869 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK) 1870 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u 1871 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16 1872 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK) 1873 /* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */ 1874 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu 1875 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0 1876 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK) 1877 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u 1878 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9 1879 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u 1880 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10 1881 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u 1882 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11 1883 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u 1884 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12 1885 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK) 1886 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u 1887 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16 1888 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) 1889 /* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */ 1890 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu 1891 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0 1892 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK) 1893 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u 1894 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9 1895 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u 1896 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10 1897 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u 1898 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11 1899 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u 1900 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12 1901 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK) 1902 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u 1903 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16 1904 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) 1905 /* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */ 1906 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu 1907 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0 1908 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK) 1909 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u 1910 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5 1911 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK) 1912 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u 1913 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7 1914 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u 1915 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8 1916 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK) 1917 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u 1918 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17 1919 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK) 1920 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u 1921 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20 1922 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK) 1923 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u 1924 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24 1925 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK) 1926 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u 1927 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29 1928 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK) 1929 /* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */ 1930 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu 1931 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0 1932 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK) 1933 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u 1934 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5 1935 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK) 1936 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u 1937 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7 1938 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u 1939 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8 1940 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK) 1941 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u 1942 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17 1943 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK) 1944 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u 1945 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20 1946 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK) 1947 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u 1948 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24 1949 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK) 1950 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u 1951 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29 1952 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK) 1953 /* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */ 1954 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu 1955 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0 1956 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK) 1957 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u 1958 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5 1959 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK) 1960 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u 1961 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7 1962 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u 1963 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8 1964 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK) 1965 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u 1966 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17 1967 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK) 1968 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u 1969 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20 1970 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK) 1971 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u 1972 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24 1973 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK) 1974 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u 1975 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29 1976 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK) 1977 /* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */ 1978 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu 1979 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0 1980 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK) 1981 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u 1982 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5 1983 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK) 1984 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u 1985 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7 1986 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u 1987 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8 1988 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK) 1989 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u 1990 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17 1991 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK) 1992 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u 1993 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20 1994 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK) 1995 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u 1996 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24 1997 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK) 1998 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u 1999 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 2000 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK) 2001 2002 2003 #define CCM_GPR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i)) 2004 #define CCM_OBSERVE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i)) 2005 #define CCM_SCTRL(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i)) 2006 #define CCM_CCGR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i)) 2007 #define CCM_ROOT_TARGET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) 2008 2009 #define CCM_GPR_SET(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4) 2010 #define CCM_OBSERVE_SET(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) 2011 #define CCM_SCTRL_SET(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) 2012 #define CCM_CCGR_SET(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) 2013 #define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) 2014 2015 #define CCM_GPR_CLR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8) 2016 #define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) 2017 #define CCM_SCTRL_CLR(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) 2018 #define CCM_CCGR_CLR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) 2019 #define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) 2020 2021 #define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12) 2022 #define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) 2023 #define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) 2024 #define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) 2025 #define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12) 2026 2027 #define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i)) 2028 #define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i)) 2029 #define HW_CCM_SCTRL_WR(i, v) writel((v), CCM_SCTRL(i)) 2030 #define HW_CCM_CCGR_WR(i, v) writel((v), CCM_CCGR(i)) 2031 #define HW_CCM_ROOT_TARGET_WR(i, v) writel((v), CCM_ROOT_TARGET(i)) 2032 2033 #define HW_CCM_GPR_RD(i) readl(CCM_GPR(i)) 2034 #define HW_CCM_CCM_OBSERVE_RD(i) readl(CCM_OBSERVE(i)) 2035 #define HW_CCM_SCTRL_RD(i) readl(CCM_SCTRL(i)) 2036 #define HW_CCM_CCGR_RD(i) readl(CCM_CCGR(i)) 2037 #define HW_CCM_ROOT_TARGET_RD(i) readl(CCM_ROOT_TARGET(i)) 2038 2039 #define HW_CCM_GPR_SET(i, v) writel((v), CCM_GPR_SET(i)) 2040 #define HW_CCM_CCM_OBSERVE_SET(i, v) writel((v), CCM_CCM_OBSERVE_SET(i)) 2041 #define HW_CCM_SCTRL_SET(i, v) writel((v), CCM_SCTRL_SET(i)) 2042 #define HW_CCM_CCGR_SET(i, v) writel((v), CCM_CCGR_SET(i)) 2043 #define HW_CCM_ROOT_TARGET_SET(i, v) writel((v), CCM_ROOT_TARGET_SET(i)) 2044 2045 #define HW_CCM_GPR_CLR(i, v) writel((v), CCM_GPR_CLR(i)) 2046 #define HW_CCM_CCM_OBSERVE_CLR(i, v) writel((v), CCM_CCM_OBSERVE_CLR(i)) 2047 #define HW_CCM_SCTRL_CLR(i, v) writel((v), CCM_SCTRL_CLR(i)) 2048 #define HW_CCM_CCGR_CLR(i, v) writel((v), CCM_CCGR_CLR(i)) 2049 #define HW_CCM_ROOT_TARGET_CLR(i, v) writel((v), CCM_ROOT_TARGET_CLR(i)) 2050 2051 #define HW_CCM_GPR_TOGGLE(i, v) writel((v), CCM_GPR_TOGGLE(i)) 2052 #define HW_CCM_CCM_OBSERVE_TOGGLE(i, v) writel((v), CCM_CCM_OBSERVE_TOGGLE(i)) 2053 #define HW_CCM_SCTRL_TOGGLE(i, v) writel((v), CCM_SCTRL_TOGGLE(i)) 2054 #define HW_CCM_CCGR_TOGGLE(i, v) writel((v), CCM_CCGR_TOGGLE(i)) 2055 #define HW_CCM_ROOT_TARGET_TOGGLE(i, v) writel((v), CCM_ROOT_TARGET_TOGGLE(i)) 2056 2057 #define CCM_CLK_ON_MSK 0x03 2058 2059 #define CCM_ROOT_TGT_POST_DIV_SHIFT 0 2060 #define CCM_ROOT_TGT_PRE_DIV_SHIFT 15 2061 #define CCM_ROOT_TGT_MUX_SHIFT 24 2062 #define CCM_ROOT_TGT_ENABLE_SHIFT 28 2063 #define CCM_ROOT_TGT_POST_DIV_MSK 0x3F 2064 #define CCM_ROOT_TGT_PRE_DIV_MSK (0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT) 2065 #define CCM_ROOT_TGT_MUX_MSK (0x07 << CCM_ROOT_TGT_MUX_SHIFT) 2066 #define CCM_ROOT_TGT_ENABLE_MSK (0x01 << CCM_ROOT_TGT_ENABLE_SHIFT) 2067 2068 #define CCM_ROOT_TGT_POST_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_POST_DIV_SHIFT) & CCM_ROOT_TGT_POST_DIV_MSK) 2069 #define CCM_ROOT_TGT_PRE_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_PRE_DIV_SHIFT) & CCM_ROOT_TGT_PRE_DIV_MSK) 2070 #define CCM_ROOT_TGT_MUX_TO(x) ((((x) - 1) << CCM_ROOT_TGT_MUX_SHIFT) & CCM_ROOT_TGT_MUX_MSK) 2071 2072 /* 2073 * Field values definition for clock slice TARGET register 2074 */ 2075 2076 #define CLK_ROOT_ON 0x10000000 2077 #define CLK_ROOT_OFF 0x0 2078 #define CLK_ROOT_ENABLE_MASK 0x10000000 2079 #define CLK_ROOT_ENABLE_SHIFT 28 2080 2081 #define CLK_ROOT_ALT0 0x00000000 2082 #define CLK_ROOT_ALT1 0x01000000 2083 #define CLK_ROOT_ALT2 0x02000000 2084 #define CLK_ROOT_ALT3 0x03000000 2085 #define CLK_ROOT_ALT4 0x04000000 2086 #define CLK_ROOT_ALT5 0x05000000 2087 #define CLK_ROOT_ALT6 0x06000000 2088 #define CLK_ROOT_ALT7 0x07000000 2089 2090 2091 #define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007 2092 #define CLK_ROOT_POST_DIV_MASK 0x0000003f 2093 #define CLK_ROOT_POST_DIV_SHIFT 0 2094 #define CLK_ROOT_POST_DIV(n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK) 2095 2096 #define CLK_ROOT_AUTO_DIV_MASK 0x00000700 2097 #define CLK_ROOT_AUTO_DIV_SHIFT 8 2098 #define CLK_ROOT_AUTO_DIV(n) ((n << CLK_ROOT_AUTO_DIV_SHIFT) & CLK_ROOT_AUTO_DIV_MASK) 2099 2100 #define CLK_ROOT_AUTO_EN_MASK 0x00001000 2101 #define CLK_ROOT_AUTO_EN 0x00001000 2102 2103 #define CLK_ROOT_PRE_DIV_MASK 0x00070000 2104 #define CLK_ROOT_PRE_DIV_SHIFT 16 2105 #define CLK_ROOT_PRE_DIV(n) ((n << CLK_ROOT_PRE_DIV_SHIFT) & CLK_ROOT_PRE_DIV_MASK) 2106 2107 #define CLK_ROOT_MUX_MASK 0x07000000 2108 #define CLK_ROOT_MUX_SHIFT 24 2109 2110 #define CLK_ROOT_EN_MASK 0x10000000 2111 2112 #define CLK_ROOT_AUTO_ON 0x00001000 2113 #define CLK_ROOT_AUTO_OFF 0x0 2114 2115 /* ARM_A7_CLK_ROOT */ 2116 #define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2117 #define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK 0x01000000 2118 #define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x03000000 2119 #define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2120 #define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 2121 #define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 2122 #define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2123 #define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2124 2125 /* ARM_M4_CLK_ROOT */ 2126 #define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2127 #define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 2128 #define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2129 #define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 2130 #define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x02000000 2131 #define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2132 #define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2133 #define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2134 2135 /* ARM_M0_CLK_ROOT */ 2136 #define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2137 #define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 2138 #define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2139 #define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x03000000 2140 #define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x02000000 2141 #define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2142 #define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2143 #define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2144 2145 /* MAIN_AXI_CLK_ROOT */ 2146 #define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2147 #define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2148 #define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 2149 #define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 2150 #define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2151 #define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 2152 #define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2153 #define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2154 2155 /* DISP_AXI_CLK_ROOT */ 2156 #define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2157 #define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2158 #define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 2159 #define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x04000000 2160 #define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 2161 #define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 2162 #define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2163 #define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2164 2165 /* ENET_AXI_CLK_ROOT */ 2166 #define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2167 #define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2168 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 2169 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 2170 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 2171 #define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 2172 #define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2173 #define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2174 2175 /* NAND_USDHC_BUS_CLK_ROOT */ 2176 #define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2177 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2178 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x03000000 2179 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 2180 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x04000000 2181 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 2182 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2183 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 2184 2185 /* AHB_CLK_ROOT */ 2186 #define AHB_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2187 #define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2188 #define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 2189 #define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2190 #define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 2191 #define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2192 #define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2193 #define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 2194 2195 /* DRAM_PHYM_CLK_ROOT */ 2196 #define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 2197 #define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT 0x01000000 2198 2199 /* DRAM_CLK_ROOT */ 2200 #define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 2201 #define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT 0x01000000 2202 2203 /* DRAM_PHYM_ALT_CLK_ROOT */ 2204 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2205 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 2206 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 2207 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 2208 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2209 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2210 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2211 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 2212 2213 /* DRAM_ALT_CLK_ROOT */ 2214 #define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2215 #define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 2216 #define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 2217 #define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 2218 #define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x07000000 2219 #define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2220 #define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x04000000 2221 #define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2222 2223 /* USB_HSIC_CLK_ROOT */ 2224 #define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2225 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 2226 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x03000000 2227 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 2228 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x05000000 2229 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 2230 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2231 #define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x02000000 2232 2233 /* PCIE_CTRL_CLK_ROOT */ 2234 #define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2235 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 2236 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 2237 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x06000000 2238 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 2239 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x07000000 2240 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 2241 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x01000000 2242 2243 /* PCIE_PHY_CLK_ROOT */ 2244 #define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2245 #define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x07000000 2246 #define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 2247 #define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2248 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 2249 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 2250 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 2251 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2252 2253 /* EPDC_PIXEL_CLK_ROOT */ 2254 #define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2255 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2256 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 2257 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 2258 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 2259 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 2260 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x06000000 2261 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2262 2263 /* LCDIF_PIXEL_CLK_ROOT */ 2264 #define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2265 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2266 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2267 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 2268 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 2269 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2270 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2271 #define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3 0x03000000 2272 2273 /* MIPI_DSI_EXTSER_CLK_ROOT */ 2274 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2275 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 2276 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 2277 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 2278 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 2279 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 2280 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 2281 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2282 2283 /* MIPI_CSI_WARP_CLK_ROOT */ 2284 #define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2285 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 2286 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 2287 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 2288 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 2289 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 2290 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 2291 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2292 2293 /* MIPI_DPHY_REF_CLK_ROOT */ 2294 #define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2295 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2296 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2297 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x03000000 2298 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2299 #define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK 0x04000000 2300 #define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2301 #define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2302 2303 /* SAI1_CLK_ROOT */ 2304 #define SAI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2305 #define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2306 #define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2307 #define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2308 #define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2309 #define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2310 #define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2311 #define SAI1_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 2312 2313 /* SAI2_CLK_ROOT */ 2314 #define SAI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2315 #define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2316 #define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2317 #define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2318 #define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2319 #define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2320 #define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2321 #define SAI2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 2322 2323 /* SAI3_CLK_ROOT */ 2324 #define SAI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2325 #define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2326 #define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2327 #define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2328 #define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2329 #define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2330 #define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2331 #define SAI3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2332 2333 /* SPDIF_CLK_ROOT */ 2334 #define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2335 #define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2336 #define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2337 #define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2338 #define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2339 #define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2340 #define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2341 #define SPDIF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2342 2343 /* ENET1_REF_CLK_ROOT */ 2344 #define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2345 #define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 2346 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 2347 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2348 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 2349 #define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2350 #define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2351 #define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 2352 2353 /* ENET1_TIME_CLK_ROOT */ 2354 #define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2355 #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2356 #define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2357 #define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2358 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 2359 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 2360 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 2361 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2362 2363 /* ENET2_REF_CLK_ROOT */ 2364 #define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2365 #define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 2366 #define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 2367 #define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2368 #define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 2369 #define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2370 #define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2371 #define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 2372 2373 /* ENET2_TIME_CLK_ROOT */ 2374 #define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2375 #define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2376 #define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2377 #define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2378 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 2379 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 2380 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 2381 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2382 2383 /* ENET_PHY_REF_CLK_ROOT */ 2384 #define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2385 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 2386 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x07000000 2387 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x03000000 2388 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2389 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 2390 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2391 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2392 2393 /* EIM_CLK_ROOT */ 2394 #define EIM_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2395 #define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2396 #define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2397 #define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x04000000 2398 #define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2399 #define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x05000000 2400 #define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2401 #define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2402 2403 /* NAND_CLK_ROOT */ 2404 #define NAND_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2405 #define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2406 #define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 2407 #define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 2408 #define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 2409 #define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 2410 #define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2411 #define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2412 2413 /* QSPI_CLK_ROOT */ 2414 #define QSPI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2415 #define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2416 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2417 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 2418 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 2419 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 2420 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2421 #define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2422 2423 /* USDHC1_CLK_ROOT */ 2424 #define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2425 #define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2426 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 2427 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2428 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 2429 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 2430 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2431 #define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2432 2433 /* USDHC2_CLK_ROOT */ 2434 #define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2435 #define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2436 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 2437 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2438 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 2439 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 2440 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2441 #define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2442 2443 /* USDHC3_CLK_ROOT */ 2444 #define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2445 #define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2446 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 2447 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2448 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 2449 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 2450 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2451 #define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2452 2453 /* CAN1_CLK_ROOT */ 2454 #define CAN1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2455 #define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2456 #define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 2457 #define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2458 #define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 2459 #define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 2460 #define CAN1_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 2461 #define CAN1_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 2462 2463 /* CAN2_CLK_ROOT */ 2464 #define CAN2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2465 #define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2466 #define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 2467 #define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2468 #define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 2469 #define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 2470 #define CAN2_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 2471 #define CAN2_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2472 2473 /* I2C1_CLK_ROOT */ 2474 #define I2C1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2475 #define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2476 #define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2477 #define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 2478 #define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2479 #define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2480 #define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 2481 #define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 2482 2483 /* I2C2_CLK_ROOT */ 2484 #define I2C2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2485 #define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2486 #define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2487 #define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 2488 #define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2489 #define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2490 #define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 2491 #define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 2492 2493 /* I2C3_CLK_ROOT */ 2494 #define I2C3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2495 #define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2496 #define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2497 #define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 2498 #define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2499 #define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2500 #define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 2501 #define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 2502 2503 /* I2C4_CLK_ROOT */ 2504 #define I2C4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2505 #define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2506 #define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2507 #define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 2508 #define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2509 #define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2510 #define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 2511 #define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 2512 2513 /* UART1_CLK_ROOT */ 2514 #define UART1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2515 #define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2516 #define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2517 #define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2518 #define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2519 #define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2520 #define UART1_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2521 #define UART1_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2522 2523 /* UART2_CLK_ROOT */ 2524 #define UART2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2525 #define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2526 #define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2527 #define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2528 #define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2529 #define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2530 #define UART2_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2531 #define UART2_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 2532 2533 /* UART3_CLK_ROOT */ 2534 #define UART3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2535 #define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2536 #define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2537 #define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2538 #define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2539 #define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2540 #define UART3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2541 #define UART3_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2542 2543 /* UART4_CLK_ROOT */ 2544 #define UART4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2545 #define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2546 #define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2547 #define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2548 #define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2549 #define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2550 #define UART4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2551 #define UART4_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 2552 2553 /* UART5_CLK_ROOT */ 2554 #define UART5_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2555 #define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2556 #define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2557 #define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2558 #define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2559 #define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2560 #define UART5_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2561 #define UART5_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2562 2563 /* UART6_CLK_ROOT */ 2564 #define UART6_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2565 #define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2566 #define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2567 #define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2568 #define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2569 #define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2570 #define UART6_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2571 #define UART6_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 2572 2573 /* UART7_CLK_ROOT */ 2574 #define UART7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2575 #define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2576 #define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2577 #define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2578 #define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2579 #define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2580 #define UART7_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2581 #define UART7_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2582 2583 /* ECSPI1_CLK_ROOT */ 2584 #define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2585 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2586 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2587 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 2588 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2589 #define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2590 #define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2591 #define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2592 2593 /* ECSPI2_CLK_ROOT */ 2594 #define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2595 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2596 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2597 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 2598 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2599 #define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2600 #define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2601 #define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2602 2603 /* ECSPI3_CLK_ROOT */ 2604 #define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2605 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2606 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2607 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 2608 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2609 #define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2610 #define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2611 #define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2612 2613 /* ECSPI4_CLK_ROOT */ 2614 #define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2615 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2616 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2617 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 2618 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2619 #define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2620 #define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2621 #define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2622 2623 /* PWM1_CLK_ROOT */ 2624 #define PWM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2625 #define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2626 #define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2627 #define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2628 #define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2629 #define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2630 #define PWM1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2631 #define PWM1_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 2632 2633 /* PWM2_CLK_ROOT */ 2634 #define PWM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2635 #define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2636 #define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2637 #define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2638 #define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2639 #define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2640 #define PWM2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2641 #define PWM2_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 2642 2643 /* PWM3_CLK_ROOT */ 2644 #define PWM3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2645 #define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2646 #define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2647 #define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2648 #define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2649 #define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2650 #define PWM3_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2651 #define PWM3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2652 2653 /* PWM4_CLK_ROOT */ 2654 #define PWM4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2655 #define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2656 #define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2657 #define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2658 #define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2659 #define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2660 #define PWM4_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2661 #define PWM4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2662 2663 /* FLEXTIMER1_CLK_ROOT */ 2664 #define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2665 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2666 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2667 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2668 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2669 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2670 #define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2671 #define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 2672 2673 /* FLEXTIMER2_CLK_ROOT */ 2674 #define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2675 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2676 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2677 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2678 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2679 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2680 #define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2681 #define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 2682 2683 /* SIM1_CLK_ROOT */ 2684 #define SIM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2685 #define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2686 #define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2687 #define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2688 #define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2689 #define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2690 #define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2691 #define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 2692 2693 /* SIM2_CLK_ROOT */ 2694 #define SIM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2695 #define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2696 #define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2697 #define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2698 #define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2699 #define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2700 #define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 2701 #define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 2702 2703 /* GPT1_CLK_ROOT */ 2704 #define GPT1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2705 #define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 2706 #define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2707 #define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2708 #define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2709 #define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2710 #define GPT1_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 2711 #define GPT1_CLK_ROOT_FROM_EXT_CLK_1 0x07000000 2712 2713 /* GPT2_CLK_ROOT */ 2714 #define GPT2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2715 #define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 2716 #define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2717 #define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2718 #define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2719 #define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2720 #define GPT2_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 2721 #define GPT2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 2722 2723 /* GPT3_CLK_ROOT */ 2724 #define GPT3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2725 #define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 2726 #define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2727 #define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2728 #define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2729 #define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2730 #define GPT3_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 2731 #define GPT3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2732 2733 /* GPT4_CLK_ROOT */ 2734 #define GPT4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2735 #define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 2736 #define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2737 #define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2738 #define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2739 #define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2740 #define GPT4_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 2741 #define GPT4_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 2742 2743 /* TRACE_CLK_ROOT */ 2744 #define TRACE_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2745 #define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2746 #define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2747 #define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2748 #define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 2749 #define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 2750 #define TRACE_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 2751 #define TRACE_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2752 2753 /* WDOG_CLK_ROOT */ 2754 #define WDOG_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2755 #define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2756 #define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2757 #define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK 0x07000000 2758 #define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2759 #define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 2760 #define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 2761 #define WDOG_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2762 2763 /* CSI_MCLK_CLK_ROOT */ 2764 #define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2765 #define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2766 #define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2767 #define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2768 #define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 2769 #define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2770 #define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2771 #define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2772 2773 /* AUDIO_MCLK_CLK_ROOT */ 2774 #define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2775 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2776 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2777 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2778 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 2779 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2780 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2781 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2782 2783 /* WRCLK_CLK_ROOT */ 2784 #define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2785 #define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2786 #define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 2787 #define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2788 #define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2789 #define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x06000000 2790 #define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x01000000 2791 #define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x03000000 2792 2793 /* IPP_DO_CLKO1 */ 2794 #define IPP_DO_CLKO1_FROM_OSC_24M_CLK 0x00000000 2795 #define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK 0x06000000 2796 #define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 2797 #define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 2798 #define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK 0x03000000 2799 #define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK 0x04000000 2800 #define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 2801 #define IPP_DO_CLKO1_FROM_REF_1M_CLK 0x07000000 2802 2803 /* IPP_DO_CLKO2 */ 2804 #define IPP_DO_CLKO2_FROM_OSC_24M_CLK 0x00000000 2805 #define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2806 #define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 2807 #define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK 0x03000000 2808 #define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK 0x04000000 2809 #define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2810 #define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2811 #define IPP_DO_CLKO2_FROM_OSC_32K_CLK 0x07000000 2812 2813 #endif 2814