1 /* 2 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * Author: 5 * Peng Fan <Peng.Fan@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _ASM_ARCH_CLOCK_SLICE_H 11 #define _ASM_ARCH_CLOCK_SLICE_H 12 13 enum root_pre_div { 14 CLK_ROOT_PRE_DIV1 = 0, 15 CLK_ROOT_PRE_DIV2, 16 CLK_ROOT_PRE_DIV3, 17 CLK_ROOT_PRE_DIV4, 18 CLK_ROOT_PRE_DIV5, 19 CLK_ROOT_PRE_DIV6, 20 CLK_ROOT_PRE_DIV7, 21 CLK_ROOT_PRE_DIV8, 22 }; 23 24 enum root_post_div { 25 CLK_ROOT_POST_DIV1 = 0, 26 CLK_ROOT_POST_DIV2, 27 CLK_ROOT_POST_DIV3, 28 CLK_ROOT_POST_DIV4, 29 CLK_ROOT_POST_DIV5, 30 CLK_ROOT_POST_DIV6, 31 CLK_ROOT_POST_DIV7, 32 CLK_ROOT_POST_DIV8, 33 CLK_ROOT_POST_DIV9, 34 CLK_ROOT_POST_DIV10, 35 CLK_ROOT_POST_DIV11, 36 CLK_ROOT_POST_DIV12, 37 CLK_ROOT_POST_DIV13, 38 CLK_ROOT_POST_DIV14, 39 CLK_ROOT_POST_DIV15, 40 CLK_ROOT_POST_DIV16, 41 CLK_ROOT_POST_DIV17, 42 CLK_ROOT_POST_DIV18, 43 CLK_ROOT_POST_DIV19, 44 CLK_ROOT_POST_DIV20, 45 CLK_ROOT_POST_DIV21, 46 CLK_ROOT_POST_DIV22, 47 CLK_ROOT_POST_DIV23, 48 CLK_ROOT_POST_DIV24, 49 CLK_ROOT_POST_DIV25, 50 CLK_ROOT_POST_DIV26, 51 CLK_ROOT_POST_DIV27, 52 CLK_ROOT_POST_DIV28, 53 CLK_ROOT_POST_DIV29, 54 CLK_ROOT_POST_DIV30, 55 CLK_ROOT_POST_DIV31, 56 CLK_ROOT_POST_DIV32, 57 CLK_ROOT_POST_DIV33, 58 CLK_ROOT_POST_DIV34, 59 CLK_ROOT_POST_DIV35, 60 CLK_ROOT_POST_DIV36, 61 CLK_ROOT_POST_DIV37, 62 CLK_ROOT_POST_DIV38, 63 CLK_ROOT_POST_DIV39, 64 CLK_ROOT_POST_DIV40, 65 CLK_ROOT_POST_DIV41, 66 CLK_ROOT_POST_DIV42, 67 CLK_ROOT_POST_DIV43, 68 CLK_ROOT_POST_DIV44, 69 CLK_ROOT_POST_DIV45, 70 CLK_ROOT_POST_DIV46, 71 CLK_ROOT_POST_DIV47, 72 CLK_ROOT_POST_DIV48, 73 CLK_ROOT_POST_DIV49, 74 CLK_ROOT_POST_DIV50, 75 CLK_ROOT_POST_DIV51, 76 CLK_ROOT_POST_DIV52, 77 CLK_ROOT_POST_DIV53, 78 CLK_ROOT_POST_DIV54, 79 CLK_ROOT_POST_DIV55, 80 CLK_ROOT_POST_DIV56, 81 CLK_ROOT_POST_DIV57, 82 CLK_ROOT_POST_DIV58, 83 CLK_ROOT_POST_DIV59, 84 CLK_ROOT_POST_DIV60, 85 CLK_ROOT_POST_DIV61, 86 CLK_ROOT_POST_DIV62, 87 CLK_ROOT_POST_DIV63, 88 CLK_ROOT_POST_DIV64, 89 }; 90 91 enum root_auto_div { 92 CLK_ROOT_AUTO_DIV1 = 0, 93 CLK_ROOT_AUTO_DIV2, 94 CLK_ROOT_AUTO_DIV4, 95 CLK_ROOT_AUTO_DIV8, 96 CLK_ROOT_AUTO_DIV16, 97 }; 98 99 int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src); 100 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); 101 int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div); 102 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); 103 int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div); 104 int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div); 105 int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div, 106 int auto_en); 107 int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div, 108 int *auto_en); 109 int clock_get_target_val(enum clk_root_index clock_id, u32 *val); 110 int clock_set_target_val(enum clk_root_index clock_id, u32 val); 111 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, 112 enum root_post_div post_div, enum clk_root_src clock_src); 113 int clock_root_enabled(enum clk_root_index clock_id); 114 115 int clock_enable(enum clk_ccgr_index index, bool enable); 116 #endif 117