1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 */ 4 5 /* 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #ifndef __MXC_HDMI_H__ 22 #define __MXC_HDMI_H__ 23 24 /* 25 * Hdmi controller registers 26 */ 27 28 /* Identification Registers */ 29 #define HDMI_DESIGN_ID 0x0000 30 #define HDMI_REVISION_ID 0x0001 31 #define HDMI_PRODUCT_ID0 0x0002 32 #define HDMI_PRODUCT_ID1 0x0003 33 #define HDMI_CONFIG0_ID 0x0004 34 #define HDMI_CONFIG1_ID 0x0005 35 #define HDMI_CONFIG2_ID 0x0006 36 #define HDMI_CONFIG3_ID 0x0007 37 38 /* Interrupt Registers */ 39 #define HDMI_IH_FC_STAT0 0x0100 40 #define HDMI_IH_FC_STAT1 0x0101 41 #define HDMI_IH_FC_STAT2 0x0102 42 #define HDMI_IH_AS_STAT0 0x0103 43 #define HDMI_IH_PHY_STAT0 0x0104 44 #define HDMI_IH_I2CM_STAT0 0x0105 45 #define HDMI_IH_CEC_STAT0 0x0106 46 #define HDMI_IH_VP_STAT0 0x0107 47 #define HDMI_IH_I2CMPHY_STAT0 0x0108 48 #define HDMI_IH_AHBDMAAUD_STAT0 0x0109 49 50 #define HDMI_IH_MUTE_FC_STAT0 0x0180 51 #define HDMI_IH_MUTE_FC_STAT1 0x0181 52 #define HDMI_IH_MUTE_FC_STAT2 0x0182 53 #define HDMI_IH_MUTE_AS_STAT0 0x0183 54 #define HDMI_IH_MUTE_PHY_STAT0 0x0184 55 #define HDMI_IH_MUTE_I2CM_STAT0 0x0185 56 #define HDMI_IH_MUTE_CEC_STAT0 0x0186 57 #define HDMI_IH_MUTE_VP_STAT0 0x0187 58 #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 59 #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 60 #define HDMI_IH_MUTE 0x01FF 61 62 /* Video Sample Registers */ 63 #define HDMI_TX_INVID0 0x0200 64 #define HDMI_TX_INSTUFFING 0x0201 65 #define HDMI_TX_GYDATA0 0x0202 66 #define HDMI_TX_GYDATA1 0x0203 67 #define HDMI_TX_RCRDATA0 0x0204 68 #define HDMI_TX_RCRDATA1 0x0205 69 #define HDMI_TX_BCBDATA0 0x0206 70 #define HDMI_TX_BCBDATA1 0x0207 71 72 /* Video Packetizer Registers */ 73 #define HDMI_VP_STATUS 0x0800 74 #define HDMI_VP_PR_CD 0x0801 75 #define HDMI_VP_STUFF 0x0802 76 #define HDMI_VP_REMAP 0x0803 77 #define HDMI_VP_CONF 0x0804 78 #define HDMI_VP_STAT 0x0805 79 #define HDMI_VP_INT 0x0806 80 #define HDMI_VP_MASK 0x0807 81 #define HDMI_VP_POL 0x0808 82 83 /* Frame Composer Registers */ 84 #define HDMI_FC_INVIDCONF 0x1000 85 #define HDMI_FC_INHACTV0 0x1001 86 #define HDMI_FC_INHACTV1 0x1002 87 #define HDMI_FC_INHBLANK0 0x1003 88 #define HDMI_FC_INHBLANK1 0x1004 89 #define HDMI_FC_INVACTV0 0x1005 90 #define HDMI_FC_INVACTV1 0x1006 91 #define HDMI_FC_INVBLANK 0x1007 92 #define HDMI_FC_HSYNCINDELAY0 0x1008 93 #define HDMI_FC_HSYNCINDELAY1 0x1009 94 #define HDMI_FC_HSYNCINWIDTH0 0x100A 95 #define HDMI_FC_HSYNCINWIDTH1 0x100B 96 #define HDMI_FC_VSYNCINDELAY 0x100C 97 #define HDMI_FC_VSYNCINWIDTH 0x100D 98 #define HDMI_FC_INFREQ0 0x100E 99 #define HDMI_FC_INFREQ1 0x100F 100 #define HDMI_FC_INFREQ2 0x1010 101 #define HDMI_FC_CTRLDUR 0x1011 102 #define HDMI_FC_EXCTRLDUR 0x1012 103 #define HDMI_FC_EXCTRLSPAC 0x1013 104 #define HDMI_FC_CH0PREAM 0x1014 105 #define HDMI_FC_CH1PREAM 0x1015 106 #define HDMI_FC_CH2PREAM 0x1016 107 #define HDMI_FC_AVICONF3 0x1017 108 #define HDMI_FC_GCP 0x1018 109 #define HDMI_FC_AVICONF0 0x1019 110 #define HDMI_FC_AVICONF1 0x101A 111 #define HDMI_FC_AVICONF2 0x101B 112 #define HDMI_FC_AVIVID 0x101C 113 #define HDMI_FC_AVIETB0 0x101D 114 #define HDMI_FC_AVIETB1 0x101E 115 #define HDMI_FC_AVISBB0 0x101F 116 #define HDMI_FC_AVISBB1 0x1020 117 #define HDMI_FC_AVIELB0 0x1021 118 #define HDMI_FC_AVIELB1 0x1022 119 #define HDMI_FC_AVISRB0 0x1023 120 #define HDMI_FC_AVISRB1 0x1024 121 #define HDMI_FC_AUDICONF0 0x1025 122 #define HDMI_FC_AUDICONF1 0x1026 123 #define HDMI_FC_AUDICONF2 0x1027 124 #define HDMI_FC_AUDICONF3 0x1028 125 #define HDMI_FC_VSDIEEEID0 0x1029 126 #define HDMI_FC_VSDSIZE 0x102A 127 #define HDMI_FC_VSDIEEEID1 0x1030 128 #define HDMI_FC_VSDIEEEID2 0x1031 129 #define HDMI_FC_VSDPAYLOAD0 0x1032 130 #define HDMI_FC_VSDPAYLOAD1 0x1033 131 #define HDMI_FC_VSDPAYLOAD2 0x1034 132 #define HDMI_FC_VSDPAYLOAD3 0x1035 133 #define HDMI_FC_VSDPAYLOAD4 0x1036 134 #define HDMI_FC_VSDPAYLOAD5 0x1037 135 #define HDMI_FC_VSDPAYLOAD6 0x1038 136 #define HDMI_FC_VSDPAYLOAD7 0x1039 137 #define HDMI_FC_VSDPAYLOAD8 0x103A 138 #define HDMI_FC_VSDPAYLOAD9 0x103B 139 #define HDMI_FC_VSDPAYLOAD10 0x103C 140 #define HDMI_FC_VSDPAYLOAD11 0x103D 141 #define HDMI_FC_VSDPAYLOAD12 0x103E 142 #define HDMI_FC_VSDPAYLOAD13 0x103F 143 #define HDMI_FC_VSDPAYLOAD14 0x1040 144 #define HDMI_FC_VSDPAYLOAD15 0x1041 145 #define HDMI_FC_VSDPAYLOAD16 0x1042 146 #define HDMI_FC_VSDPAYLOAD17 0x1043 147 #define HDMI_FC_VSDPAYLOAD18 0x1044 148 #define HDMI_FC_VSDPAYLOAD19 0x1045 149 #define HDMI_FC_VSDPAYLOAD20 0x1046 150 #define HDMI_FC_VSDPAYLOAD21 0x1047 151 #define HDMI_FC_VSDPAYLOAD22 0x1048 152 #define HDMI_FC_VSDPAYLOAD23 0x1049 153 #define HDMI_FC_SPDVENDORNAME0 0x104A 154 #define HDMI_FC_SPDVENDORNAME1 0x104B 155 #define HDMI_FC_SPDVENDORNAME2 0x104C 156 #define HDMI_FC_SPDVENDORNAME3 0x104D 157 #define HDMI_FC_SPDVENDORNAME4 0x104E 158 #define HDMI_FC_SPDVENDORNAME5 0x104F 159 #define HDMI_FC_SPDVENDORNAME6 0x1050 160 #define HDMI_FC_SPDVENDORNAME7 0x1051 161 #define HDMI_FC_SDPPRODUCTNAME0 0x1052 162 #define HDMI_FC_SDPPRODUCTNAME1 0x1053 163 #define HDMI_FC_SDPPRODUCTNAME2 0x1054 164 #define HDMI_FC_SDPPRODUCTNAME3 0x1055 165 #define HDMI_FC_SDPPRODUCTNAME4 0x1056 166 #define HDMI_FC_SDPPRODUCTNAME5 0x1057 167 #define HDMI_FC_SDPPRODUCTNAME6 0x1058 168 #define HDMI_FC_SDPPRODUCTNAME7 0x1059 169 #define HDMI_FC_SDPPRODUCTNAME8 0x105A 170 #define HDMI_FC_SDPPRODUCTNAME9 0x105B 171 #define HDMI_FC_SDPPRODUCTNAME10 0x105C 172 #define HDMI_FC_SDPPRODUCTNAME11 0x105D 173 #define HDMI_FC_SDPPRODUCTNAME12 0x105E 174 #define HDMI_FC_SDPPRODUCTNAME13 0x105F 175 #define HDMI_FC_SDPPRODUCTNAME14 0x1060 176 #define HDMI_FC_SPDPRODUCTNAME15 0x1061 177 #define HDMI_FC_SPDDEVICEINF 0x1062 178 #define HDMI_FC_AUDSCONF 0x1063 179 #define HDMI_FC_AUDSSTAT 0x1064 180 #define HDMI_FC_DATACH0FILL 0x1070 181 #define HDMI_FC_DATACH1FILL 0x1071 182 #define HDMI_FC_DATACH2FILL 0x1072 183 #define HDMI_FC_CTRLQHIGH 0x1073 184 #define HDMI_FC_CTRLQLOW 0x1074 185 #define HDMI_FC_ACP0 0x1075 186 #define HDMI_FC_ACP28 0x1076 187 #define HDMI_FC_ACP27 0x1077 188 #define HDMI_FC_ACP26 0x1078 189 #define HDMI_FC_ACP25 0x1079 190 #define HDMI_FC_ACP24 0x107A 191 #define HDMI_FC_ACP23 0x107B 192 #define HDMI_FC_ACP22 0x107C 193 #define HDMI_FC_ACP21 0x107D 194 #define HDMI_FC_ACP20 0x107E 195 #define HDMI_FC_ACP19 0x107F 196 #define HDMI_FC_ACP18 0x1080 197 #define HDMI_FC_ACP17 0x1081 198 #define HDMI_FC_ACP16 0x1082 199 #define HDMI_FC_ACP15 0x1083 200 #define HDMI_FC_ACP14 0x1084 201 #define HDMI_FC_ACP13 0x1085 202 #define HDMI_FC_ACP12 0x1086 203 #define HDMI_FC_ACP11 0x1087 204 #define HDMI_FC_ACP10 0x1088 205 #define HDMI_FC_ACP9 0x1089 206 #define HDMI_FC_ACP8 0x108A 207 #define HDMI_FC_ACP7 0x108B 208 #define HDMI_FC_ACP6 0x108C 209 #define HDMI_FC_ACP5 0x108D 210 #define HDMI_FC_ACP4 0x108E 211 #define HDMI_FC_ACP3 0x108F 212 #define HDMI_FC_ACP2 0x1090 213 #define HDMI_FC_ACP1 0x1091 214 #define HDMI_FC_ISCR1_0 0x1092 215 #define HDMI_FC_ISCR1_16 0x1093 216 #define HDMI_FC_ISCR1_15 0x1094 217 #define HDMI_FC_ISCR1_14 0x1095 218 #define HDMI_FC_ISCR1_13 0x1096 219 #define HDMI_FC_ISCR1_12 0x1097 220 #define HDMI_FC_ISCR1_11 0x1098 221 #define HDMI_FC_ISCR1_10 0x1099 222 #define HDMI_FC_ISCR1_9 0x109A 223 #define HDMI_FC_ISCR1_8 0x109B 224 #define HDMI_FC_ISCR1_7 0x109C 225 #define HDMI_FC_ISCR1_6 0x109D 226 #define HDMI_FC_ISCR1_5 0x109E 227 #define HDMI_FC_ISCR1_4 0x109F 228 #define HDMI_FC_ISCR1_3 0x10A0 229 #define HDMI_FC_ISCR1_2 0x10A1 230 #define HDMI_FC_ISCR1_1 0x10A2 231 #define HDMI_FC_ISCR2_15 0x10A3 232 #define HDMI_FC_ISCR2_14 0x10A4 233 #define HDMI_FC_ISCR2_13 0x10A5 234 #define HDMI_FC_ISCR2_12 0x10A6 235 #define HDMI_FC_ISCR2_11 0x10A7 236 #define HDMI_FC_ISCR2_10 0x10A8 237 #define HDMI_FC_ISCR2_9 0x10A9 238 #define HDMI_FC_ISCR2_8 0x10AA 239 #define HDMI_FC_ISCR2_7 0x10AB 240 #define HDMI_FC_ISCR2_6 0x10AC 241 #define HDMI_FC_ISCR2_5 0x10AD 242 #define HDMI_FC_ISCR2_4 0x10AE 243 #define HDMI_FC_ISCR2_3 0x10AF 244 #define HDMI_FC_ISCR2_2 0x10B0 245 #define HDMI_FC_ISCR2_1 0x10B1 246 #define HDMI_FC_ISCR2_0 0x10B2 247 #define HDMI_FC_DATAUTO0 0x10B3 248 #define HDMI_FC_DATAUTO1 0x10B4 249 #define HDMI_FC_DATAUTO2 0x10B5 250 #define HDMI_FC_DATMAN 0x10B6 251 #define HDMI_FC_DATAUTO3 0x10B7 252 #define HDMI_FC_RDRB0 0x10B8 253 #define HDMI_FC_RDRB1 0x10B9 254 #define HDMI_FC_RDRB2 0x10BA 255 #define HDMI_FC_RDRB3 0x10BB 256 #define HDMI_FC_RDRB4 0x10BC 257 #define HDMI_FC_RDRB5 0x10BD 258 #define HDMI_FC_RDRB6 0x10BE 259 #define HDMI_FC_RDRB7 0x10BF 260 #define HDMI_FC_STAT0 0x10D0 261 #define HDMI_FC_INT0 0x10D1 262 #define HDMI_FC_MASK0 0x10D2 263 #define HDMI_FC_POL0 0x10D3 264 #define HDMI_FC_STAT1 0x10D4 265 #define HDMI_FC_INT1 0x10D5 266 #define HDMI_FC_MASK1 0x10D6 267 #define HDMI_FC_POL1 0x10D7 268 #define HDMI_FC_STAT2 0x10D8 269 #define HDMI_FC_INT2 0x10D9 270 #define HDMI_FC_MASK2 0x10DA 271 #define HDMI_FC_POL2 0x10DB 272 #define HDMI_FC_PRCONF 0x10E0 273 274 #define HDMI_FC_GMD_STAT 0x1100 275 #define HDMI_FC_GMD_EN 0x1101 276 #define HDMI_FC_GMD_UP 0x1102 277 #define HDMI_FC_GMD_CONF 0x1103 278 #define HDMI_FC_GMD_HB 0x1104 279 #define HDMI_FC_GMD_PB0 0x1105 280 #define HDMI_FC_GMD_PB1 0x1106 281 #define HDMI_FC_GMD_PB2 0x1107 282 #define HDMI_FC_GMD_PB3 0x1108 283 #define HDMI_FC_GMD_PB4 0x1109 284 #define HDMI_FC_GMD_PB5 0x110A 285 #define HDMI_FC_GMD_PB6 0x110B 286 #define HDMI_FC_GMD_PB7 0x110C 287 #define HDMI_FC_GMD_PB8 0x110D 288 #define HDMI_FC_GMD_PB9 0x110E 289 #define HDMI_FC_GMD_PB10 0x110F 290 #define HDMI_FC_GMD_PB11 0x1110 291 #define HDMI_FC_GMD_PB12 0x1111 292 #define HDMI_FC_GMD_PB13 0x1112 293 #define HDMI_FC_GMD_PB14 0x1113 294 #define HDMI_FC_GMD_PB15 0x1114 295 #define HDMI_FC_GMD_PB16 0x1115 296 #define HDMI_FC_GMD_PB17 0x1116 297 #define HDMI_FC_GMD_PB18 0x1117 298 #define HDMI_FC_GMD_PB19 0x1118 299 #define HDMI_FC_GMD_PB20 0x1119 300 #define HDMI_FC_GMD_PB21 0x111A 301 #define HDMI_FC_GMD_PB22 0x111B 302 #define HDMI_FC_GMD_PB23 0x111C 303 #define HDMI_FC_GMD_PB24 0x111D 304 #define HDMI_FC_GMD_PB25 0x111E 305 #define HDMI_FC_GMD_PB26 0x111F 306 #define HDMI_FC_GMD_PB27 0x1120 307 308 #define HDMI_FC_DBGFORCE 0x1200 309 #define HDMI_FC_DBGAUD0CH0 0x1201 310 #define HDMI_FC_DBGAUD1CH0 0x1202 311 #define HDMI_FC_DBGAUD2CH0 0x1203 312 #define HDMI_FC_DBGAUD0CH1 0x1204 313 #define HDMI_FC_DBGAUD1CH1 0x1205 314 #define HDMI_FC_DBGAUD2CH1 0x1206 315 #define HDMI_FC_DBGAUD0CH2 0x1207 316 #define HDMI_FC_DBGAUD1CH2 0x1208 317 #define HDMI_FC_DBGAUD2CH2 0x1209 318 #define HDMI_FC_DBGAUD0CH3 0x120A 319 #define HDMI_FC_DBGAUD1CH3 0x120B 320 #define HDMI_FC_DBGAUD2CH3 0x120C 321 #define HDMI_FC_DBGAUD0CH4 0x120D 322 #define HDMI_FC_DBGAUD1CH4 0x120E 323 #define HDMI_FC_DBGAUD2CH4 0x120F 324 #define HDMI_FC_DBGAUD0CH5 0x1210 325 #define HDMI_FC_DBGAUD1CH5 0x1211 326 #define HDMI_FC_DBGAUD2CH5 0x1212 327 #define HDMI_FC_DBGAUD0CH6 0x1213 328 #define HDMI_FC_DBGAUD1CH6 0x1214 329 #define HDMI_FC_DBGAUD2CH6 0x1215 330 #define HDMI_FC_DBGAUD0CH7 0x1216 331 #define HDMI_FC_DBGAUD1CH7 0x1217 332 #define HDMI_FC_DBGAUD2CH7 0x1218 333 #define HDMI_FC_DBGTMDS0 0x1219 334 #define HDMI_FC_DBGTMDS1 0x121A 335 #define HDMI_FC_DBGTMDS2 0x121B 336 337 /* HDMI Source PHY Registers */ 338 #define HDMI_PHY_CONF0 0x3000 339 #define HDMI_PHY_TST0 0x3001 340 #define HDMI_PHY_TST1 0x3002 341 #define HDMI_PHY_TST2 0x3003 342 #define HDMI_PHY_STAT0 0x3004 343 #define HDMI_PHY_INT0 0x3005 344 #define HDMI_PHY_MASK0 0x3006 345 #define HDMI_PHY_POL0 0x3007 346 347 /* HDMI Master PHY Registers */ 348 #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 349 #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 350 #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 351 #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 352 #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 353 #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 354 #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 355 #define HDMI_PHY_I2CM_INT_ADDR 0x3027 356 #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 357 #define HDMI_PHY_I2CM_DIV_ADDR 0x3029 358 #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a 359 #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b 360 #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c 361 #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d 362 #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e 363 #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f 364 #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 365 #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 366 #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 367 368 /* Audio Sampler Registers */ 369 #define HDMI_AUD_CONF0 0x3100 370 #define HDMI_AUD_CONF1 0x3101 371 #define HDMI_AUD_INT 0x3102 372 #define HDMI_AUD_CONF2 0x3103 373 #define HDMI_AUD_N1 0x3200 374 #define HDMI_AUD_N2 0x3201 375 #define HDMI_AUD_N3 0x3202 376 #define HDMI_AUD_CTS1 0x3203 377 #define HDMI_AUD_CTS2 0x3204 378 #define HDMI_AUD_CTS3 0x3205 379 #define HDMI_AUD_INPUTCLKFS 0x3206 380 #define HDMI_AUD_SPDIFINT 0x3302 381 #define HDMI_AUD_CONF0_HBR 0x3400 382 #define HDMI_AUD_HBR_STATUS 0x3401 383 #define HDMI_AUD_HBR_INT 0x3402 384 #define HDMI_AUD_HBR_POL 0x3403 385 #define HDMI_AUD_HBR_MASK 0x3404 386 387 /* Generic Parallel Audio Interface Registers */ 388 /* Not used as GPAUD interface is not enabled in hw */ 389 #define HDMI_GP_CONF0 0x3500 390 #define HDMI_GP_CONF1 0x3501 391 #define HDMI_GP_CONF2 0x3502 392 #define HDMI_GP_STAT 0x3503 393 #define HDMI_GP_INT 0x3504 394 #define HDMI_GP_MASK 0x3505 395 #define HDMI_GP_POL 0x3506 396 397 /* Audio DMA Registers */ 398 #define HDMI_AHB_DMA_CONF0 0x3600 399 #define HDMI_AHB_DMA_START 0x3601 400 #define HDMI_AHB_DMA_STOP 0x3602 401 #define HDMI_AHB_DMA_THRSLD 0x3603 402 #define HDMI_AHB_DMA_STRADDR0 0x3604 403 #define HDMI_AHB_DMA_STRADDR1 0x3605 404 #define HDMI_AHB_DMA_STRADDR2 0x3606 405 #define HDMI_AHB_DMA_STRADDR3 0x3607 406 #define HDMI_AHB_DMA_STPADDR0 0x3608 407 #define HDMI_AHB_DMA_STPADDR1 0x3609 408 #define HDMI_AHB_DMA_STPADDR2 0x360a 409 #define HDMI_AHB_DMA_STPADDR3 0x360b 410 #define HDMI_AHB_DMA_BSTADDR0 0x360c 411 #define HDMI_AHB_DMA_BSTADDR1 0x360d 412 #define HDMI_AHB_DMA_BSTADDR2 0x360e 413 #define HDMI_AHB_DMA_BSTADDR3 0x360f 414 #define HDMI_AHB_DMA_MBLENGTH0 0x3610 415 #define HDMI_AHB_DMA_MBLENGTH1 0x3611 416 #define HDMI_AHB_DMA_STAT 0x3612 417 #define HDMI_AHB_DMA_INT 0x3613 418 #define HDMI_AHB_DMA_MASK 0x3614 419 #define HDMI_AHB_DMA_POL 0x3615 420 #define HDMI_AHB_DMA_CONF1 0x3616 421 #define HDMI_AHB_DMA_BUFFSTAT 0x3617 422 #define HDMI_AHB_DMA_BUFFINT 0x3618 423 #define HDMI_AHB_DMA_BUFFMASK 0x3619 424 #define HDMI_AHB_DMA_BUFFPOL 0x361a 425 426 /* Main Controller Registers */ 427 #define HDMI_MC_SFRDIV 0x4000 428 #define HDMI_MC_CLKDIS 0x4001 429 #define HDMI_MC_SWRSTZ 0x4002 430 #define HDMI_MC_OPCTRL 0x4003 431 #define HDMI_MC_FLOWCTRL 0x4004 432 #define HDMI_MC_PHYRSTZ 0x4005 433 #define HDMI_MC_LOCKONCLOCK 0x4006 434 #define HDMI_MC_HEACPHY_RST 0x4007 435 436 /* Color Space Converter Registers */ 437 #define HDMI_CSC_CFG 0x4100 438 #define HDMI_CSC_SCALE 0x4101 439 #define HDMI_CSC_COEF_A1_MSB 0x4102 440 #define HDMI_CSC_COEF_A1_LSB 0x4103 441 #define HDMI_CSC_COEF_A2_MSB 0x4104 442 #define HDMI_CSC_COEF_A2_LSB 0x4105 443 #define HDMI_CSC_COEF_A3_MSB 0x4106 444 #define HDMI_CSC_COEF_A3_LSB 0x4107 445 #define HDMI_CSC_COEF_A4_MSB 0x4108 446 #define HDMI_CSC_COEF_A4_LSB 0x4109 447 #define HDMI_CSC_COEF_B1_MSB 0x410A 448 #define HDMI_CSC_COEF_B1_LSB 0x410B 449 #define HDMI_CSC_COEF_B2_MSB 0x410C 450 #define HDMI_CSC_COEF_B2_LSB 0x410D 451 #define HDMI_CSC_COEF_B3_MSB 0x410E 452 #define HDMI_CSC_COEF_B3_LSB 0x410F 453 #define HDMI_CSC_COEF_B4_MSB 0x4110 454 #define HDMI_CSC_COEF_B4_LSB 0x4111 455 #define HDMI_CSC_COEF_C1_MSB 0x4112 456 #define HDMI_CSC_COEF_C1_LSB 0x4113 457 #define HDMI_CSC_COEF_C2_MSB 0x4114 458 #define HDMI_CSC_COEF_C2_LSB 0x4115 459 #define HDMI_CSC_COEF_C3_MSB 0x4116 460 #define HDMI_CSC_COEF_C3_LSB 0x4117 461 #define HDMI_CSC_COEF_C4_MSB 0x4118 462 #define HDMI_CSC_COEF_C4_LSB 0x4119 463 464 /* HDCP Encryption Engine Registers */ 465 #define HDMI_A_HDCPCFG0 0x5000 466 #define HDMI_A_HDCPCFG1 0x5001 467 #define HDMI_A_HDCPOBS0 0x5002 468 #define HDMI_A_HDCPOBS1 0x5003 469 #define HDMI_A_HDCPOBS2 0x5004 470 #define HDMI_A_HDCPOBS3 0x5005 471 #define HDMI_A_APIINTCLR 0x5006 472 #define HDMI_A_APIINTSTAT 0x5007 473 #define HDMI_A_APIINTMSK 0x5008 474 #define HDMI_A_VIDPOLCFG 0x5009 475 #define HDMI_A_OESSWCFG 0x500A 476 #define HDMI_A_TIMER1SETUP0 0x500B 477 #define HDMI_A_TIMER1SETUP1 0x500C 478 #define HDMI_A_TIMER2SETUP0 0x500D 479 #define HDMI_A_TIMER2SETUP1 0x500E 480 #define HDMI_A_100MSCFG 0x500F 481 #define HDMI_A_2SCFG0 0x5010 482 #define HDMI_A_2SCFG1 0x5011 483 #define HDMI_A_5SCFG0 0x5012 484 #define HDMI_A_5SCFG1 0x5013 485 #define HDMI_A_SRMVERLSB 0x5014 486 #define HDMI_A_SRMVERMSB 0x5015 487 #define HDMI_A_SRMCTRL 0x5016 488 #define HDMI_A_SFRSETUP 0x5017 489 #define HDMI_A_I2CHSETUP 0x5018 490 #define HDMI_A_INTSETUP 0x5019 491 #define HDMI_A_PRESETUP 0x501A 492 #define HDMI_A_SRM_BASE 0x5020 493 494 /* CEC Engine Registers */ 495 #define HDMI_CEC_CTRL 0x7D00 496 #define HDMI_CEC_STAT 0x7D01 497 #define HDMI_CEC_MASK 0x7D02 498 #define HDMI_CEC_POLARITY 0x7D03 499 #define HDMI_CEC_INT 0x7D04 500 #define HDMI_CEC_ADDR_L 0x7D05 501 #define HDMI_CEC_ADDR_H 0x7D06 502 #define HDMI_CEC_TX_CNT 0x7D07 503 #define HDMI_CEC_RX_CNT 0x7D08 504 #define HDMI_CEC_TX_DATA0 0x7D10 505 #define HDMI_CEC_TX_DATA1 0x7D11 506 #define HDMI_CEC_TX_DATA2 0x7D12 507 #define HDMI_CEC_TX_DATA3 0x7D13 508 #define HDMI_CEC_TX_DATA4 0x7D14 509 #define HDMI_CEC_TX_DATA5 0x7D15 510 #define HDMI_CEC_TX_DATA6 0x7D16 511 #define HDMI_CEC_TX_DATA7 0x7D17 512 #define HDMI_CEC_TX_DATA8 0x7D18 513 #define HDMI_CEC_TX_DATA9 0x7D19 514 #define HDMI_CEC_TX_DATA10 0x7D1a 515 #define HDMI_CEC_TX_DATA11 0x7D1b 516 #define HDMI_CEC_TX_DATA12 0x7D1c 517 #define HDMI_CEC_TX_DATA13 0x7D1d 518 #define HDMI_CEC_TX_DATA14 0x7D1e 519 #define HDMI_CEC_TX_DATA15 0x7D1f 520 #define HDMI_CEC_RX_DATA0 0x7D20 521 #define HDMI_CEC_RX_DATA1 0x7D21 522 #define HDMI_CEC_RX_DATA2 0x7D22 523 #define HDMI_CEC_RX_DATA3 0x7D23 524 #define HDMI_CEC_RX_DATA4 0x7D24 525 #define HDMI_CEC_RX_DATA5 0x7D25 526 #define HDMI_CEC_RX_DATA6 0x7D26 527 #define HDMI_CEC_RX_DATA7 0x7D27 528 #define HDMI_CEC_RX_DATA8 0x7D28 529 #define HDMI_CEC_RX_DATA9 0x7D29 530 #define HDMI_CEC_RX_DATA10 0x7D2a 531 #define HDMI_CEC_RX_DATA11 0x7D2b 532 #define HDMI_CEC_RX_DATA12 0x7D2c 533 #define HDMI_CEC_RX_DATA13 0x7D2d 534 #define HDMI_CEC_RX_DATA14 0x7D2e 535 #define HDMI_CEC_RX_DATA15 0x7D2f 536 #define HDMI_CEC_LOCK 0x7D30 537 #define HDMI_CEC_WKUPCTRL 0x7D31 538 539 /* I2C Master Registers (E-DDC) */ 540 #define HDMI_I2CM_SLAVE 0x7E00 541 #define HDMI_I2CMESS 0x7E01 542 #define HDMI_I2CM_DATAO 0x7E02 543 #define HDMI_I2CM_DATAI 0x7E03 544 #define HDMI_I2CM_OPERATION 0x7E04 545 #define HDMI_I2CM_INT 0x7E05 546 #define HDMI_I2CM_CTLINT 0x7E06 547 #define HDMI_I2CM_DIV 0x7E07 548 #define HDMI_I2CM_SEGADDR 0x7E08 549 #define HDMI_I2CM_SOFTRSTZ 0x7E09 550 #define HDMI_I2CM_SEGPTR 0x7E0A 551 #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B 552 #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C 553 #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D 554 #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E 555 #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F 556 #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 557 #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 558 #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 559 560 /* Random Number Generator Registers (RNG) */ 561 #define HDMI_RNG_BASE 0x8000 562 563 564 /* 565 * Register field definitions 566 */ 567 enum { 568 /* IH_FC_INT2 field values */ 569 HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, 570 HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, 571 HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, 572 573 /* IH_FC_STAT2 field values */ 574 HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03, 575 HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, 576 HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, 577 578 /* IH_PHY_STAT0 field values */ 579 HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20, 580 HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10, 581 HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8, 582 HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4, 583 HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2, 584 HDMI_IH_PHY_STAT0_HPD = 0x1, 585 586 /* IH_MUTE_I2CMPHY_STAT0 field values */ 587 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2, 588 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1, 589 590 /* IH_AHBDMAAUD_STAT0 field values */ 591 HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20, 592 HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10, 593 HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08, 594 HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04, 595 HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02, 596 HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, 597 598 /* IH_MUTE_FC_STAT2 field values */ 599 HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03, 600 HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, 601 HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, 602 603 /* IH_MUTE_AHBDMAAUD_STAT0 field values */ 604 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20, 605 HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10, 606 HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08, 607 HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04, 608 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02, 609 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, 610 611 /* IH_MUTE field values */ 612 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, 613 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, 614 615 /* TX_INVID0 field values */ 616 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80, 617 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80, 618 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, 619 HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F, 620 HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, 621 622 /* TX_INSTUFFING field values */ 623 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4, 624 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, 625 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0, 626 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2, 627 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, 628 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0, 629 HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1, 630 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, 631 HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0, 632 633 /* VP_PR_CD field values */ 634 HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0, 635 HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, 636 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F, 637 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, 638 639 /* VP_STUFF field values */ 640 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, 641 HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, 642 HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10, 643 HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4, 644 HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8, 645 HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3, 646 HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, 647 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, 648 HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0, 649 HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, 650 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, 651 HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0, 652 HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, 653 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, 654 HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0, 655 656 /* VP_CONF field values */ 657 HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, 658 HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, 659 HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00, 660 HDMI_VP_CONF_PP_EN_ENMASK = 0x20, 661 HDMI_VP_CONF_PP_EN_ENABLE = 0x20, 662 HDMI_VP_CONF_PP_EN_DISABLE = 0x00, 663 HDMI_VP_CONF_PR_EN_MASK = 0x10, 664 HDMI_VP_CONF_PR_EN_ENABLE = 0x10, 665 HDMI_VP_CONF_PR_EN_DISABLE = 0x00, 666 HDMI_VP_CONF_YCC422_EN_MASK = 0x8, 667 HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8, 668 HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, 669 HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, 670 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, 671 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0, 672 HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, 673 HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, 674 HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1, 675 HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0, 676 677 /* VP_REMAP field values */ 678 HDMI_VP_REMAP_MASK = 0x3, 679 HDMI_VP_REMAP_YCC422_24bit = 0x2, 680 HDMI_VP_REMAP_YCC422_20bit = 0x1, 681 HDMI_VP_REMAP_YCC422_16bit = 0x0, 682 683 /* FC_INVIDCONF field values */ 684 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, 685 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, 686 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, 687 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, 688 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, 689 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 690 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, 691 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, 692 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 693 HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, 694 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, 695 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, 696 HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, 697 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, 698 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, 699 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, 700 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, 701 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, 702 HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, 703 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, 704 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, 705 706 /* FC_AUDICONF0 field values */ 707 HDMI_FC_AUDICONF0_CC_OFFSET = 4, 708 HDMI_FC_AUDICONF0_CC_MASK = 0x70, 709 HDMI_FC_AUDICONF0_CT_OFFSET = 0, 710 HDMI_FC_AUDICONF0_CT_MASK = 0xF, 711 712 /* FC_AUDICONF1 field values */ 713 HDMI_FC_AUDICONF1_SS_OFFSET = 3, 714 HDMI_FC_AUDICONF1_SS_MASK = 0x18, 715 HDMI_FC_AUDICONF1_SF_OFFSET = 0, 716 HDMI_FC_AUDICONF1_SF_MASK = 0x7, 717 718 /* FC_AUDICONF3 field values */ 719 HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5, 720 HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60, 721 HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4, 722 HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10, 723 HDMI_FC_AUDICONF3_LSV_OFFSET = 0, 724 HDMI_FC_AUDICONF3_LSV_MASK = 0xF, 725 726 /* FC_AUDSCHNLS0 field values */ 727 HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4, 728 HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30, 729 HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0, 730 HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01, 731 732 /* FC_AUDSCHNLS3-6 field values */ 733 HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0, 734 HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f, 735 HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4, 736 HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0, 737 HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0, 738 HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f, 739 HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4, 740 HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0, 741 742 HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0, 743 HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f, 744 HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4, 745 HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0, 746 HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0, 747 HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f, 748 HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4, 749 HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0, 750 751 /* HDMI_FC_AUDSCHNLS7 field values */ 752 HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, 753 HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, 754 755 /* HDMI_FC_AUDSCHNLS8 field values */ 756 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, 757 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4, 758 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, 759 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, 760 761 /* FC_AUDSCONF field values */ 762 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, 763 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4, 764 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1, 765 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0, 766 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1, 767 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0, 768 769 /* FC_STAT2 field values */ 770 HDMI_FC_STAT2_OVERFLOW_MASK = 0x03, 771 HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, 772 HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, 773 774 /* FC_INT2 field values */ 775 HDMI_FC_INT2_OVERFLOW_MASK = 0x03, 776 HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, 777 HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, 778 779 /* FC_MASK2 field values */ 780 HDMI_FC_MASK2_OVERFLOW_MASK = 0x03, 781 HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02, 782 HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01, 783 784 /* FC_PRCONF field values */ 785 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0, 786 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4, 787 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F, 788 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0, 789 790 /* FC_AVICONF0-FC_AVICONF3 field values */ 791 HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, 792 HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, 793 HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, 794 HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, 795 HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, 796 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, 797 HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, 798 HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C, 799 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, 800 HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, 801 HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, 802 HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C, 803 HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, 804 HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, 805 HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, 806 HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, 807 808 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F, 809 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, 810 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, 811 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A, 812 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B, 813 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, 814 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, 815 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, 816 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, 817 HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0, 818 HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, 819 HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, 820 HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, 821 HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0, 822 823 HDMI_FC_AVICONF2_SCALING_MASK = 0x03, 824 HDMI_FC_AVICONF2_SCALING_NONE = 0x00, 825 HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, 826 HDMI_FC_AVICONF2_SCALING_VERT = 0x02, 827 HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03, 828 HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C, 829 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, 830 HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, 831 HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, 832 HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, 833 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, 834 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, 835 HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, 836 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, 837 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, 838 HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, 839 HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, 840 HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, 841 842 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, 843 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, 844 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, 845 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, 846 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, 847 HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C, 848 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, 849 HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, 850 851 /* FC_DBGFORCE field values */ 852 HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, 853 HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, 854 855 /* PHY_CONF0 field values */ 856 HDMI_PHY_CONF0_PDZ_MASK = 0x80, 857 HDMI_PHY_CONF0_PDZ_OFFSET = 7, 858 HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, 859 HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, 860 HDMI_PHY_CONF0_SPARECTRL = 0x20, 861 HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, 862 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, 863 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, 864 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, 865 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4, 866 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2, 867 HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, 868 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, 869 HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, 870 HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, 871 872 /* PHY_TST0 field values */ 873 HDMI_PHY_TST0_TSTCLR_MASK = 0x20, 874 HDMI_PHY_TST0_TSTCLR_OFFSET = 5, 875 HDMI_PHY_TST0_TSTEN_MASK = 0x10, 876 HDMI_PHY_TST0_TSTEN_OFFSET = 4, 877 HDMI_PHY_TST0_TSTCLK_MASK = 0x1, 878 HDMI_PHY_TST0_TSTCLK_OFFSET = 0, 879 880 /* PHY_STAT0 field values */ 881 HDMI_PHY_RX_SENSE3 = 0x80, 882 HDMI_PHY_RX_SENSE2 = 0x40, 883 HDMI_PHY_RX_SENSE1 = 0x20, 884 HDMI_PHY_RX_SENSE0 = 0x10, 885 HDMI_PHY_HPD = 0x02, 886 HDMI_PHY_TX_PHY_LOCK = 0x01, 887 888 /* PHY_I2CM_SLAVE_ADDR field values */ 889 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, 890 HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, 891 892 /* PHY_I2CM_OPERATION_ADDR field values */ 893 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, 894 HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1, 895 896 /* HDMI_PHY_I2CM_INT_ADDR */ 897 HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, 898 HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04, 899 900 /* HDMI_PHY_I2CM_CTLINT_ADDR */ 901 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, 902 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40, 903 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, 904 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04, 905 906 /* AUD_CTS3 field values */ 907 HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, 908 HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, 909 HDMI_AUD_CTS3_N_SHIFT_1 = 0, 910 HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, 911 HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, 912 HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, 913 HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, 914 HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, 915 /* note that the CTS3 MANUAL bit has been removed 916 from our part. Can't set it, will read as 0. */ 917 HDMI_AUD_CTS3_CTS_MANUAL = 0x10, 918 HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, 919 920 /* AHB_DMA_CONF0 field values */ 921 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7, 922 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80, 923 HDMI_AHB_DMA_CONF0_HBR = 0x10, 924 HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3, 925 HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08, 926 HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1, 927 HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06, 928 HDMI_AHB_DMA_CONF0_INCR4 = 0x0, 929 HDMI_AHB_DMA_CONF0_INCR8 = 0x2, 930 HDMI_AHB_DMA_CONF0_INCR16 = 0x4, 931 HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1, 932 933 /* HDMI_AHB_DMA_START field values */ 934 HDMI_AHB_DMA_START_START_OFFSET = 0, 935 HDMI_AHB_DMA_START_START_MASK = 0x01, 936 937 /* HDMI_AHB_DMA_STOP field values */ 938 HDMI_AHB_DMA_STOP_STOP_OFFSET = 0, 939 HDMI_AHB_DMA_STOP_STOP_MASK = 0x01, 940 941 /* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */ 942 HDMI_AHB_DMA_DONE = 0x80, 943 HDMI_AHB_DMA_RETRY_SPLIT = 0x40, 944 HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20, 945 HDMI_AHB_DMA_ERROR = 0x10, 946 HDMI_AHB_DMA_FIFO_THREMPTY = 0x04, 947 HDMI_AHB_DMA_FIFO_FULL = 0x02, 948 HDMI_AHB_DMA_FIFO_EMPTY = 0x01, 949 950 /* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */ 951 HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02, 952 HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01, 953 954 /* MC_CLKDIS field values */ 955 HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, 956 HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, 957 HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, 958 HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, 959 HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, 960 HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, 961 HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, 962 963 /* MC_SWRSTZ field values */ 964 HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, 965 966 /* MC_FLOWCTRL field values */ 967 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1, 968 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, 969 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, 970 971 /* MC_PHYRSTZ field values */ 972 HDMI_MC_PHYRSTZ_ASSERT = 0x0, 973 HDMI_MC_PHYRSTZ_DEASSERT = 0x1, 974 975 /* MC_HEACPHY_RST field values */ 976 HDMI_MC_HEACPHY_RST_ASSERT = 0x1, 977 HDMI_MC_HEACPHY_RST_DEASSERT = 0x0, 978 979 /* CSC_CFG field values */ 980 HDMI_CSC_CFG_INTMODE_MASK = 0x30, 981 HDMI_CSC_CFG_INTMODE_OFFSET = 4, 982 HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, 983 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, 984 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, 985 HDMI_CSC_CFG_DECMODE_MASK = 0x3, 986 HDMI_CSC_CFG_DECMODE_OFFSET = 0, 987 HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, 988 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, 989 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, 990 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, 991 992 /* CSC_SCALE field values */ 993 HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, 994 HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, 995 HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, 996 HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, 997 HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, 998 HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, 999 1000 /* A_HDCPCFG0 field values */ 1001 HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80, 1002 HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80, 1003 HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00, 1004 HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40, 1005 HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40, 1006 HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00, 1007 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20, 1008 HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20, 1009 HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00, 1010 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10, 1011 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10, 1012 HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00, 1013 HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8, 1014 HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8, 1015 HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0, 1016 HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4, 1017 HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4, 1018 HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0, 1019 HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2, 1020 HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2, 1021 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0, 1022 HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1, 1023 HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1, 1024 HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0, 1025 1026 /* A_HDCPCFG1 field values */ 1027 HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8, 1028 HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8, 1029 HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0, 1030 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4, 1031 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4, 1032 HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0, 1033 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2, 1034 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2, 1035 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0, 1036 HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1, 1037 HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0, 1038 1039 /* A_VIDPOLCFG field values */ 1040 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60, 1041 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5, 1042 HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10, 1043 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10, 1044 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0, 1045 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8, 1046 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8, 1047 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0, 1048 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2, 1049 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2, 1050 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0, 1051 }; 1052 1053 #endif /* __MXC_HDMI_H__ */ 1054