1 /*
2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ASM_ARCH_MX6UL_DDR_H__
8 #define __ASM_ARCH_MX6UL_DDR_H__
9 
10 #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
11 #error "wrong CPU"
12 #endif
13 
14 #define MX6_IOM_DRAM_DQM0	0x020e0244
15 #define MX6_IOM_DRAM_DQM1	0x020e0248
16 
17 #define MX6_IOM_DRAM_RAS	0x020e024c
18 #define MX6_IOM_DRAM_CAS	0x020e0250
19 #define MX6_IOM_DRAM_CS0	0x020e0254
20 #define MX6_IOM_DRAM_CS1	0x020e0258
21 #define MX6_IOM_DRAM_SDWE_B	0x020e025c
22 #define MX6_IOM_DRAM_SDODT0	0x020e0260
23 #define MX6_IOM_DRAM_SDODT1	0x020e0264
24 #define MX6_IOM_DRAM_SDBA0	0x020e0268
25 #define MX6_IOM_DRAM_SDBA1	0x020e026c
26 #define MX6_IOM_DRAM_SDBA2	0x020e0270
27 #define MX6_IOM_DRAM_SDCKE0	0x020e0274
28 #define MX6_IOM_DRAM_SDCKE1	0x020e0278
29 #define MX6_IOM_DRAM_SDCLK_0	0x020e027c
30 #define MX6_IOM_DRAM_SDQS0	0x020e0280
31 #define MX6_IOM_DRAM_SDQS1	0x020e0284
32 #define MX6_IOM_DRAM_RESET	0x020e0288
33 
34 #define MX6_IOM_GRP_ADDDS	0x020e0490
35 #define MX6_IOM_DDRMODE_CTL	0x020e0494
36 #define MX6_IOM_GRP_B0DS	0x020e0498
37 #define MX6_IOM_GRP_DDRPK	0x020e049c
38 #define MX6_IOM_GRP_CTLDS	0x020e04a0
39 #define MX6_IOM_GRP_B1DS	0x020e04a4
40 #define MX6_IOM_GRP_DDRHYS	0x020e04a8
41 #define MX6_IOM_GRP_DDRPKE	0x020e04ac
42 #define MX6_IOM_GRP_DDRMODE	0x020e04b0
43 #define MX6_IOM_GRP_DDR_TYPE	0x020e04b4
44 
45 #endif	/*__ASM_ARCH_MX6SX_DDR_H__ */
46