1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_MX6SL_DDR_H__ 8 #define __ASM_ARCH_MX6SL_DDR_H__ 9 10 #ifndef CONFIG_MX6SL 11 #error "wrong CPU" 12 #endif 13 14 #define MX6_IOM_DRAM_CAS_B 0x020e0300 15 #define MX6_IOM_DRAM_CS0_B 0x020e0304 16 #define MX6_IOM_DRAM_CS1_B 0x020e0308 17 18 #define MX6_IOM_DRAM_DQM0 0x020e030c 19 #define MX6_IOM_DRAM_DQM1 0x020e0310 20 #define MX6_IOM_DRAM_DQM2 0x020e0314 21 #define MX6_IOM_DRAM_DQM3 0x020e0318 22 23 #define MX6_IOM_DRAM_RAS_B 0x020e031c 24 #define MX6_IOM_DRAM_RESET 0x020e0320 25 26 #define MX6_IOM_DRAM_SDBA0 0x020e0324 27 #define MX6_IOM_DRAM_SDBA1 0x020e0328 28 #define MX6_IOM_DRAM_SDBA2 0x020e032c 29 30 #define MX6_IOM_DRAM_SDCKE0 0x020e0330 31 #define MX6_IOM_DRAM_SDCKE1 0x020e0334 32 33 #define MX6_IOM_DRAM_SDCLK0_P 0x020e0338 34 35 #define MX6_IOM_DRAM_ODT0 0x020e033c 36 #define MX6_IOM_DRAM_ODT1 0x020e0340 37 38 #define MX6_IOM_DRAM_SDQS0_P 0x020e0344 39 #define MX6_IOM_DRAM_SDQS1_P 0x020e0348 40 #define MX6_IOM_DRAM_SDQS2_P 0x020e034c 41 #define MX6_IOM_DRAM_SDQS3_P 0x020e0350 42 43 #define MX6_IOM_DRAM_SDWE_B 0x020e0354 44 45 #endif /*__ASM_ARCH_MX6SL_DDR_H__ */ 46