1 /* 2 * Copyright (C) 2013 Boundary Devices Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __ASM_ARCH_MX6Q_DDR_H__ 7 #define __ASM_ARCH_MX6Q_DDR_H__ 8 9 #ifndef CONFIG_MX6Q 10 #error "wrong CPU" 11 #endif 12 13 #define MX6_IOM_DRAM_DQM0 0x020e05ac 14 #define MX6_IOM_DRAM_DQM1 0x020e05b4 15 #define MX6_IOM_DRAM_DQM2 0x020e0528 16 #define MX6_IOM_DRAM_DQM3 0x020e0520 17 #define MX6_IOM_DRAM_DQM4 0x020e0514 18 #define MX6_IOM_DRAM_DQM5 0x020e0510 19 #define MX6_IOM_DRAM_DQM6 0x020e05bc 20 #define MX6_IOM_DRAM_DQM7 0x020e05c4 21 22 #define MX6_IOM_DRAM_CAS 0x020e056c 23 #define MX6_IOM_DRAM_RAS 0x020e0578 24 #define MX6_IOM_DRAM_RESET 0x020e057c 25 #define MX6_IOM_DRAM_SDCLK_0 0x020e0588 26 #define MX6_IOM_DRAM_SDCLK_1 0x020e0594 27 #define MX6_IOM_DRAM_SDBA2 0x020e058c 28 #define MX6_IOM_DRAM_SDCKE0 0x020e0590 29 #define MX6_IOM_DRAM_SDCKE1 0x020e0598 30 #define MX6_IOM_DRAM_SDODT0 0x020e059c 31 #define MX6_IOM_DRAM_SDODT1 0x020e05a0 32 33 #define MX6_IOM_DRAM_SDQS0 0x020e05a8 34 #define MX6_IOM_DRAM_SDQS1 0x020e05b0 35 #define MX6_IOM_DRAM_SDQS2 0x020e0524 36 #define MX6_IOM_DRAM_SDQS3 0x020e051c 37 #define MX6_IOM_DRAM_SDQS4 0x020e0518 38 #define MX6_IOM_DRAM_SDQS5 0x020e050c 39 #define MX6_IOM_DRAM_SDQS6 0x020e05b8 40 #define MX6_IOM_DRAM_SDQS7 0x020e05c0 41 42 #define MX6_IOM_GRP_B0DS 0x020e0784 43 #define MX6_IOM_GRP_B1DS 0x020e0788 44 #define MX6_IOM_GRP_B2DS 0x020e0794 45 #define MX6_IOM_GRP_B3DS 0x020e079c 46 #define MX6_IOM_GRP_B4DS 0x020e07a0 47 #define MX6_IOM_GRP_B5DS 0x020e07a4 48 #define MX6_IOM_GRP_B6DS 0x020e07a8 49 #define MX6_IOM_GRP_B7DS 0x020e0748 50 #define MX6_IOM_GRP_ADDDS 0x020e074c 51 #define MX6_IOM_DDRMODE_CTL 0x020e0750 52 #define MX6_IOM_GRP_DDRPKE 0x020e0758 53 #define MX6_IOM_GRP_DDRMODE 0x020e0774 54 #define MX6_IOM_GRP_CTLDS 0x020e078c 55 #define MX6_IOM_GRP_DDR_TYPE 0x020e0798 56 57 #endif /*__ASM_ARCH_MX6Q_DDR_H__ */ 58