1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 */
5
6#include <config.h>
7
8#ifdef CONFIG_ROM_UNIFIED_SECTIONS
9#define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
10#define ROM_VERSION_OFFSET               	0x80
11#else
12#define ROM_API_TABLE_BASE_ADDR_LEGACY		0xC0
13#define ROM_VERSION_OFFSET               	0x48
14#endif
15#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15	0xC4
16#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12	0xC4
17#define ROM_API_HWCNFG_SETUP_OFFSET		0x08
18#define ROM_VERSION_TO10			0x10
19#define ROM_VERSION_TO12			0x12
20#define ROM_VERSION_TO15			0x15
21
22plugin_start:
23
24	push    {r0-r4, lr}
25
26	imx6_ddr_setting
27	imx6_clock_gating
28	imx6_qos_setting
29
30/*
31 * The following is to fill in those arguments for this ROM function
32 * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
33 * This function is used to copy data from the storage media into DDR.
34 * start - Initial (possibly partial) image load address on entry.
35 *         Final image load address on exit.
36 * bytes - Initial (possibly partial) image size on entry.
37 *         Final image size on exit.
38 * boot_data - Initial @ref ivt Boot Data load address.
39 */
40	adr r0, boot_data2
41	adr r1, image_len2
42	adr r2, boot_data2
43
44#ifdef CONFIG_NOR_BOOT
45#ifdef CONFIG_MX6SX
46	ldr r3, =ROM_VERSION_OFFSET
47	ldr r4, [r3]
48	cmp r4, #ROM_VERSION_TO10
49	bgt before_calling_rom___pu_irom_hwcnfg_setup
50	ldr r3, =0x00900b00
51	ldr r4, =0x50000000
52	str r4, [r3, #0x5c]
53#else
54	ldr r3, =0x00900800
55	ldr r4, =0x08000000
56	str r4, [r3, #0xc0]
57#endif
58#endif
59
60/*
61 * check the _pu_irom_api_table for the address
62 */
63before_calling_rom___pu_irom_hwcnfg_setup:
64	ldr r3, =ROM_VERSION_OFFSET
65	ldr r4, [r3]
66#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL)
67	ldr r3, =ROM_VERSION_TO12
68	cmp r4, r3
69	ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12
70	ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
71#elif defined(CONFIG_MX6Q)
72	ldr r3, =ROM_VERSION_TO15
73	cmp r4, r3
74	ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15
75	ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
76#else
77	ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
78#endif
79	ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
80	blx r4
81after_calling_rom___pu_irom_hwcnfg_setup:
82
83/*
84 * ROM_API_HWCNFG_SETUP function enables MMU & Caches.
85 * Thus disable MMU & Caches.
86 */
87
88	mrc     p15, 0, r0, c1, c0, 0   /* read CP15 register 1 into r0*/
89	ands    r0, r0, #0x1            /* check if MMU is enabled */
90	beq     mmu_disable_notreq      /* exit if MMU is already disabled */
91
92	/* Disable caches, MMU */
93	mrc     p15, 0, r0, c1, c0, 0	/* read CP15 register 1 into r0 */
94	bic     r0, r0, #(1 << 2)	/* disable D Cache */
95	bic     r0, r0, #0x1		/* clear bit 0 ; MMU off */
96
97	bic     r0, r0, #(0x1 << 11)	/* disable Z, branch prediction */
98	bic     r0, r0, #(0x1 << 1)	/* disable A, Strict alignment */
99					/* check enabled. */
100	mcr     p15, 0, r0, c1, c0, 0	/* write CP15 register 1 */
101	mov     r0, r0
102	mov     r0, r0
103	mov     r0, r0
104	mov     r0, r0
105
106mmu_disable_notreq:
107    NOP
108
109/* To return to ROM from plugin, we need to fill in these argument.
110 * Here is what need to do:
111 * Need to construct the paramters for this function before return to ROM:
112 * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
113 */
114	pop {r0-r4, lr}
115	push {r5}
116	ldr r5, boot_data2
117	str r5, [r0]
118	ldr r5, image_len2
119	str r5, [r1]
120	ldr r5, second_ivt_offset
121	str r5, [r2]
122	mov r0, #1
123	pop {r5}
124
125	/* return back to ROM code */
126	bx lr
127
128/* make the following data right in the end of the output*/
129.ltorg
130
131#if (defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT))
132#define FLASH_OFFSET 0x1000
133#else
134#define FLASH_OFFSET 0x400
135#endif
136
137/*
138 * second_ivt_offset is the offset from the "second_ivt_header" to
139 * "image_copy_start", which involves FLASH_OFFSET, plus the first
140 * ivt_header, the plugin code size itself recorded by "ivt2_header"
141 */
142
143second_ivt_offset:      .long (ivt2_header + 0x2C + FLASH_OFFSET)
144
145/*
146 * The following is the second IVT header plus the second boot data
147 */
148ivt2_header:            .long 0x0
149app2_code_jump_v:       .long 0x0
150reserv3:                .long 0x0
151dcd2_ptr:               .long 0x0
152boot_data2_ptr:         .long 0x0
153self_ptr2:              .long 0x0
154app_code_csf2:          .long 0x0
155reserv4:                .long 0x0
156boot_data2:             .long 0x0
157image_len2:             .long 0x0
158plugin2:                .long 0x0
159