1/*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#include <config.h>
8
9#ifdef CONFIG_ROM_UNIFIED_SECTIONS
10#define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
11#define ROM_VERSION_OFFSET               	0x80
12#else
13#define ROM_API_TABLE_BASE_ADDR_LEGACY		0xC0
14#define ROM_VERSION_OFFSET               	0x48
15#endif
16#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15	0xC4
17#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12	0xC4
18#define ROM_API_HWCNFG_SETUP_OFFSET		0x08
19#define ROM_VERSION_TO10			0x10
20#define ROM_VERSION_TO12			0x12
21#define ROM_VERSION_TO15			0x15
22
23plugin_start:
24
25	push    {r0-r4, lr}
26
27	imx6_ddr_setting
28	imx6_clock_gating
29	imx6_qos_setting
30
31/*
32 * The following is to fill in those arguments for this ROM function
33 * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
34 * This function is used to copy data from the storage media into DDR.
35 * start - Initial (possibly partial) image load address on entry.
36 *         Final image load address on exit.
37 * bytes - Initial (possibly partial) image size on entry.
38 *         Final image size on exit.
39 * boot_data - Initial @ref ivt Boot Data load address.
40 */
41	adr r0, boot_data2
42	adr r1, image_len2
43	adr r2, boot_data2
44
45#ifdef CONFIG_NOR_BOOT
46#ifdef CONFIG_MX6SX
47	ldr r3, =ROM_VERSION_OFFSET
48	ldr r4, [r3]
49	cmp r4, #ROM_VERSION_TO10
50	bgt before_calling_rom___pu_irom_hwcnfg_setup
51	ldr r3, =0x00900b00
52	ldr r4, =0x50000000
53	str r4, [r3, #0x5c]
54#else
55	ldr r3, =0x00900800
56	ldr r4, =0x08000000
57	str r4, [r3, #0xc0]
58#endif
59#endif
60
61/*
62 * check the _pu_irom_api_table for the address
63 */
64before_calling_rom___pu_irom_hwcnfg_setup:
65	ldr r3, =ROM_VERSION_OFFSET
66	ldr r4, [r3]
67#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL)
68	ldr r3, =ROM_VERSION_TO12
69	cmp r4, r3
70	ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12
71	ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
72#elif defined(CONFIG_MX6Q)
73	ldr r3, =ROM_VERSION_TO15
74	cmp r4, r3
75	ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15
76	ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
77#else
78	ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
79#endif
80	ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
81	blx r4
82after_calling_rom___pu_irom_hwcnfg_setup:
83
84/*
85 * ROM_API_HWCNFG_SETUP function enables MMU & Caches.
86 * Thus disable MMU & Caches.
87 */
88
89	mrc     p15, 0, r0, c1, c0, 0   /* read CP15 register 1 into r0*/
90	ands    r0, r0, #0x1            /* check if MMU is enabled */
91	beq     mmu_disable_notreq      /* exit if MMU is already disabled */
92
93	/* Disable caches, MMU */
94	mrc     p15, 0, r0, c1, c0, 0	/* read CP15 register 1 into r0 */
95	bic     r0, r0, #(1 << 2)	/* disable D Cache */
96	bic     r0, r0, #0x1		/* clear bit 0 ; MMU off */
97
98	bic     r0, r0, #(0x1 << 11)	/* disable Z, branch prediction */
99	bic     r0, r0, #(0x1 << 1)	/* disable A, Strict alignment */
100					/* check enabled. */
101	mcr     p15, 0, r0, c1, c0, 0	/* write CP15 register 1 */
102	mov     r0, r0
103	mov     r0, r0
104	mov     r0, r0
105	mov     r0, r0
106
107mmu_disable_notreq:
108    NOP
109
110/* To return to ROM from plugin, we need to fill in these argument.
111 * Here is what need to do:
112 * Need to construct the paramters for this function before return to ROM:
113 * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
114 */
115	pop {r0-r4, lr}
116	push {r5}
117	ldr r5, boot_data2
118	str r5, [r0]
119	ldr r5, image_len2
120	str r5, [r1]
121	ldr r5, second_ivt_offset
122	str r5, [r2]
123	mov r0, #1
124	pop {r5}
125
126	/* return back to ROM code */
127	bx lr
128
129/* make the following data right in the end of the output*/
130.ltorg
131
132#if (defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT))
133#define FLASH_OFFSET 0x1000
134#else
135#define FLASH_OFFSET 0x400
136#endif
137
138/*
139 * second_ivt_offset is the offset from the "second_ivt_header" to
140 * "image_copy_start", which involves FLASH_OFFSET, plus the first
141 * ivt_header, the plugin code size itself recorded by "ivt2_header"
142 */
143
144second_ivt_offset:      .long (ivt2_header + 0x2C + FLASH_OFFSET)
145
146/*
147 * The following is the second IVT header plus the second boot data
148 */
149ivt2_header:            .long 0x0
150app2_code_jump_v:       .long 0x0
151reserv3:                .long 0x0
152dcd2_ptr:               .long 0x0
153boot_data2_ptr:         .long 0x0
154self_ptr2:              .long 0x0
155app_code_csf2:          .long 0x0
156reserv4:                .long 0x0
157boot_data2:             .long 0x0
158image_len2:             .long 0x0
159plugin2:                .long 0x0
160