1 /*
2  * Copyright (C) 2013 Boundary Devices Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 #ifndef __ASM_ARCH_MX6_DDR_H__
7 #define __ASM_ARCH_MX6_DDR_H__
8 
9 #ifndef CONFIG_SPL_BUILD
10 #ifdef CONFIG_MX6Q
11 #include "mx6q-ddr.h"
12 #else
13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
14 #include "mx6dl-ddr.h"
15 #else
16 #ifdef CONFIG_MX6SX
17 #include "mx6sx-ddr.h"
18 #else
19 #ifdef CONFIG_MX6UL
20 #include "mx6ul-ddr.h"
21 #else
22 #ifdef CONFIG_MX6SL
23 #include "mx6sl-ddr.h"
24 #else
25 #error "Please select cpu"
26 #endif	/* CONFIG_MX6SL */
27 #endif	/* CONFIG_MX6UL */
28 #endif	/* CONFIG_MX6SX */
29 #endif	/* CONFIG_MX6DL or CONFIG_MX6S */
30 #endif	/* CONFIG_MX6Q */
31 #else
32 
33 enum {
34 	DDR_TYPE_DDR3,
35 	DDR_TYPE_LPDDR2,
36 };
37 
38 /* MMDC P0/P1 Registers */
39 struct mmdc_p_regs {
40 	u32 mdctl;
41 	u32 mdpdc;
42 	u32 mdotc;
43 	u32 mdcfg0;
44 	u32 mdcfg1;
45 	u32 mdcfg2;
46 	u32 mdmisc;
47 	u32 mdscr;
48 	u32 mdref;
49 	u32 res1[2];
50 	u32 mdrwd;
51 	u32 mdor;
52 	u32 mdmrr;
53 	u32 mdcfg3lp;
54 	u32 mdmr4;
55 	u32 mdasp;
56 	u32 res2[239];
57 	u32 maarcr;
58 	u32 mapsr;
59 	u32 maexidr0;
60 	u32 maexidr1;
61 	u32 madpcr0;
62 	u32 madpcr1;
63 	u32 madpsr0;
64 	u32 madpsr1;
65 	u32 madpsr2;
66 	u32 madpsr3;
67 	u32 madpsr4;
68 	u32 madpsr5;
69 	u32 masbs0;
70 	u32 masbs1;
71 	u32 res3[2];
72 	u32 magenp;
73 	u32 res4[239];
74 	u32 mpzqhwctrl;
75 	u32 mpzqswctrl;
76 	u32 mpwlgcr;
77 	u32 mpwldectrl0;
78 	u32 mpwldectrl1;
79 	u32 mpwldlst;
80 	u32 mpodtctrl;
81 	u32 mprddqby0dl;
82 	u32 mprddqby1dl;
83 	u32 mprddqby2dl;
84 	u32 mprddqby3dl;
85 	u32 mpwrdqby0dl;
86 	u32 mpwrdqby1dl;
87 	u32 mpwrdqby2dl;
88 	u32 mpwrdqby3dl;
89 	u32 mpdgctrl0;
90 	u32 mpdgctrl1;
91 	u32 mpdgdlst0;
92 	u32 mprddlctl;
93 	u32 mprddlst;
94 	u32 mpwrdlctl;
95 	u32 mpwrdlst;
96 	u32 mpsdctrl;
97 	u32 mpzqlp2ctl;
98 	u32 mprddlhwctl;
99 	u32 mpwrdlhwctl;
100 	u32 mprddlhwst0;
101 	u32 mprddlhwst1;
102 	u32 mpwrdlhwst0;
103 	u32 mpwrdlhwst1;
104 	u32 mpwlhwerr;
105 	u32 mpdghwst0;
106 	u32 mpdghwst1;
107 	u32 mpdghwst2;
108 	u32 mpdghwst3;
109 	u32 mppdcmpr1;
110 	u32 mppdcmpr2;
111 	u32 mpswdar0;
112 	u32 mpswdrdr0;
113 	u32 mpswdrdr1;
114 	u32 mpswdrdr2;
115 	u32 mpswdrdr3;
116 	u32 mpswdrdr4;
117 	u32 mpswdrdr5;
118 	u32 mpswdrdr6;
119 	u32 mpswdrdr7;
120 	u32 mpmur0;
121 	u32 mpwrcadl;
122 	u32 mpdccr;
123 };
124 
125 #define MX6SL_IOM_DDR_BASE     0x020e0300
126 struct mx6sl_iomux_ddr_regs {
127 	u32 dram_cas;
128 	u32 dram_cs0_b;
129 	u32 dram_cs1_b;
130 	u32 dram_dqm0;
131 	u32 dram_dqm1;
132 	u32 dram_dqm2;
133 	u32 dram_dqm3;
134 	u32 dram_ras;
135 	u32 dram_reset;
136 	u32 dram_sdba0;
137 	u32 dram_sdba1;
138 	u32 dram_sdba2;
139 	u32 dram_sdcke0;
140 	u32 dram_sdcke1;
141 	u32 dram_sdclk_0;
142 	u32 dram_odt0;
143 	u32 dram_odt1;
144 	u32 dram_sdqs0;
145 	u32 dram_sdqs1;
146 	u32 dram_sdqs2;
147 	u32 dram_sdqs3;
148 	u32 dram_sdwe_b;
149 };
150 
151 #define MX6SL_IOM_GRP_BASE     0x020e0500
152 struct mx6sl_iomux_grp_regs {
153 	u32 res1[43];
154 	u32 grp_addds;
155 	u32 grp_ddrmode_ctl;
156 	u32 grp_ddrpke;
157 	u32 grp_ddrpk;
158 	u32 grp_ddrhys;
159 	u32 grp_ddrmode;
160 	u32 grp_b0ds;
161 	u32 grp_ctlds;
162 	u32 grp_b1ds;
163 	u32 grp_ddr_type;
164 	u32 grp_b2ds;
165 	u32 grp_b3ds;
166 };
167 
168 #define MX6UL_IOM_DDR_BASE	0x020e0200
169 struct mx6ul_iomux_ddr_regs {
170 	u32 res1[17];
171 	u32 dram_dqm0;
172 	u32 dram_dqm1;
173 	u32 dram_ras;
174 	u32 dram_cas;
175 	u32 dram_cs0;
176 	u32 dram_cs1;
177 	u32 dram_sdwe_b;
178 	u32 dram_odt0;
179 	u32 dram_odt1;
180 	u32 dram_sdba0;
181 	u32 dram_sdba1;
182 	u32 dram_sdba2;
183 	u32 dram_sdcke0;
184 	u32 dram_sdcke1;
185 	u32 dram_sdclk_0;
186 	u32 dram_sdqs0;
187 	u32 dram_sdqs1;
188 	u32 dram_reset;
189 };
190 
191 #define MX6UL_IOM_GRP_BASE	0x020e0400
192 struct mx6ul_iomux_grp_regs {
193 	u32 res1[36];
194 	u32 grp_addds;
195 	u32 grp_ddrmode_ctl;
196 	u32 grp_b0ds;
197 	u32 grp_ddrpk;
198 	u32 grp_ctlds;
199 	u32 grp_b1ds;
200 	u32 grp_ddrhys;
201 	u32 grp_ddrpke;
202 	u32 grp_ddrmode;
203 	u32 grp_ddr_type;
204 };
205 
206 #define MX6SX_IOM_DDR_BASE	0x020e0200
207 struct mx6sx_iomux_ddr_regs {
208 	u32 res1[59];
209 	u32 dram_dqm0;
210 	u32 dram_dqm1;
211 	u32 dram_dqm2;
212 	u32 dram_dqm3;
213 	u32 dram_ras;
214 	u32 dram_cas;
215 	u32 res2[2];
216 	u32 dram_sdwe_b;
217 	u32 dram_odt0;
218 	u32 dram_odt1;
219 	u32 dram_sdba0;
220 	u32 dram_sdba1;
221 	u32 dram_sdba2;
222 	u32 dram_sdcke0;
223 	u32 dram_sdcke1;
224 	u32 dram_sdclk_0;
225 	u32 dram_sdqs0;
226 	u32 dram_sdqs1;
227 	u32 dram_sdqs2;
228 	u32 dram_sdqs3;
229 	u32 dram_reset;
230 };
231 
232 #define MX6SX_IOM_GRP_BASE	0x020e0500
233 struct mx6sx_iomux_grp_regs {
234 	u32 res1[61];
235 	u32 grp_addds;
236 	u32 grp_ddrmode_ctl;
237 	u32 grp_ddrpke;
238 	u32 grp_ddrpk;
239 	u32 grp_ddrhys;
240 	u32 grp_ddrmode;
241 	u32 grp_b0ds;
242 	u32 grp_b1ds;
243 	u32 grp_ctlds;
244 	u32 grp_ddr_type;
245 	u32 grp_b2ds;
246 	u32 grp_b3ds;
247 };
248 
249 /*
250  * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
251  */
252 #define MX6DQ_IOM_DDR_BASE      0x020e0500
253 struct mx6dq_iomux_ddr_regs {
254 	u32 res1[3];
255 	u32 dram_sdqs5;
256 	u32 dram_dqm5;
257 	u32 dram_dqm4;
258 	u32 dram_sdqs4;
259 	u32 dram_sdqs3;
260 	u32 dram_dqm3;
261 	u32 dram_sdqs2;
262 	u32 dram_dqm2;
263 	u32 res2[16];
264 	u32 dram_cas;
265 	u32 res3[2];
266 	u32 dram_ras;
267 	u32 dram_reset;
268 	u32 res4[2];
269 	u32 dram_sdclk_0;
270 	u32 dram_sdba2;
271 	u32 dram_sdcke0;
272 	u32 dram_sdclk_1;
273 	u32 dram_sdcke1;
274 	u32 dram_sdodt0;
275 	u32 dram_sdodt1;
276 	u32 res5;
277 	u32 dram_sdqs0;
278 	u32 dram_dqm0;
279 	u32 dram_sdqs1;
280 	u32 dram_dqm1;
281 	u32 dram_sdqs6;
282 	u32 dram_dqm6;
283 	u32 dram_sdqs7;
284 	u32 dram_dqm7;
285 };
286 
287 #define MX6DQ_IOM_GRP_BASE      0x020e0700
288 struct mx6dq_iomux_grp_regs {
289 	u32 res1[18];
290 	u32 grp_b7ds;
291 	u32 grp_addds;
292 	u32 grp_ddrmode_ctl;
293 	u32 res2;
294 	u32 grp_ddrpke;
295 	u32 res3[6];
296 	u32 grp_ddrmode;
297 	u32 res4[3];
298 	u32 grp_b0ds;
299 	u32 grp_b1ds;
300 	u32 grp_ctlds;
301 	u32 res5;
302 	u32 grp_b2ds;
303 	u32 grp_ddr_type;
304 	u32 grp_b3ds;
305 	u32 grp_b4ds;
306 	u32 grp_b5ds;
307 	u32 grp_b6ds;
308 };
309 
310 #define MX6SDL_IOM_DDR_BASE     0x020e0400
311 struct mx6sdl_iomux_ddr_regs {
312 	u32 res1[25];
313 	u32 dram_cas;
314 	u32 res2[2];
315 	u32 dram_dqm0;
316 	u32 dram_dqm1;
317 	u32 dram_dqm2;
318 	u32 dram_dqm3;
319 	u32 dram_dqm4;
320 	u32 dram_dqm5;
321 	u32 dram_dqm6;
322 	u32 dram_dqm7;
323 	u32 dram_ras;
324 	u32 dram_reset;
325 	u32 res3[2];
326 	u32 dram_sdba2;
327 	u32 dram_sdcke0;
328 	u32 dram_sdcke1;
329 	u32 dram_sdclk_0;
330 	u32 dram_sdclk_1;
331 	u32 dram_sdodt0;
332 	u32 dram_sdodt1;
333 	u32 dram_sdqs0;
334 	u32 dram_sdqs1;
335 	u32 dram_sdqs2;
336 	u32 dram_sdqs3;
337 	u32 dram_sdqs4;
338 	u32 dram_sdqs5;
339 	u32 dram_sdqs6;
340 	u32 dram_sdqs7;
341 };
342 
343 #define MX6SDL_IOM_GRP_BASE     0x020e0700
344 struct mx6sdl_iomux_grp_regs {
345 	u32 res1[18];
346 	u32 grp_b7ds;
347 	u32 grp_addds;
348 	u32 grp_ddrmode_ctl;
349 	u32 grp_ddrpke;
350 	u32 res2[2];
351 	u32 grp_ddrmode;
352 	u32 grp_b0ds;
353 	u32 res3;
354 	u32 grp_ctlds;
355 	u32 grp_b1ds;
356 	u32 grp_ddr_type;
357 	u32 grp_b2ds;
358 	u32 grp_b3ds;
359 	u32 grp_b4ds;
360 	u32 grp_b5ds;
361 	u32 res4;
362 	u32 grp_b6ds;
363 };
364 
365 /* Device Information: Varies per DDR3 part number and speed grade */
366 struct mx6_ddr3_cfg {
367 	u16 mem_speed;	/* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
368 	u8 density;	/* chip density (Gb) (1,2,4,8) */
369 	u8 width;	/* bus width (bits) (4,8,16) */
370 	u8 banks;	/* number of banks */
371 	u8 rowaddr;	/* row address bits (11-16)*/
372 	u8 coladdr;	/* col address bits (9-12) */
373 	u8 pagesz;	/* page size (K) (1-2) */
374 	u16 trcd;	/* tRCD=tRP=CL (ns*100) */
375 	u16 trcmin;	/* tRC min (ns*100) */
376 	u16 trasmin;	/* tRAS min (ns*100) */
377 	u8 SRT;		/* self-refresh temperature: 0=normal, 1=extended */
378 };
379 
380 /* Device Information: Varies per LPDDR2 part number and speed grade */
381 struct mx6_lpddr2_cfg {
382 	u16 mem_speed;	/* ie 800 for LPDDR2-800 */
383 	u8 density;	/* chip density (Gb) (1,2,4,8) */
384 	u8 width;	/* bus width (bits) (4,8,16) */
385 	u8 banks;	/* number of banks */
386 	u8 rowaddr;	/* row address bits (11-16)*/
387 	u8 coladdr;	/* col address bits (9-12) */
388 	u16 trcd_lp;
389 	u16 trppb_lp;
390 	u16 trpab_lp;
391 	u16 trcmin;	/* tRC min (ns*100) */
392 	u16 trasmin;	/* tRAS min (ns*100) */
393 };
394 
395 /* System Information: Varies per board design, layout, and term choices */
396 struct mx6_ddr_sysinfo {
397 	u8 dsize;	/* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
398 	u8 cs_density;	/* density per chip select (Gb) */
399 	u8 ncs;		/* number chip selects used (1|2) */
400 	char cs1_mirror;/* enable address mirror (0|1) */
401 	char bi_on;	/* Bank interleaving enable */
402 	u8 rtt_nom;	/* Rtt_Nom (DDR3_RTT_*) */
403 	u8 rtt_wr;	/* Rtt_Wr (DDR3_RTT_*) */
404 	u8 ralat;	/* Read Additional Latency (0-7) */
405 	u8 walat;	/* Write Additional Latency (0-3) */
406 	u8 mif3_mode;	/* Command prediction working mode */
407 	u8 rst_to_cke;	/* Time from SDE enable to CKE rise */
408 	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
409 	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
410 	u8 ddr_type;	/* DDR type: DDR3(0) or LPDDR2(1) */
411 	u8 refsel;	/* REF_SEL field of register MDREF */
412 	u8 refr;	/* REFR field of register MDREF */
413 };
414 
415 /*
416  * Board specific calibration:
417  *   This includes write leveling calibration values as well as DQS gating
418  *   and read/write delays. These values are board/layout/device specific.
419  *   Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
420  *   (DOC-96412) to determine these values over a range of boards and
421  *   temperatures.
422  */
423 struct mx6_mmdc_calibration {
424 	/* write leveling calibration */
425 	u32 p0_mpwldectrl0;
426 	u32 p0_mpwldectrl1;
427 	u32 p1_mpwldectrl0;
428 	u32 p1_mpwldectrl1;
429 	/* read DQS gating */
430 	u32 p0_mpdgctrl0;
431 	u32 p0_mpdgctrl1;
432 	u32 p1_mpdgctrl0;
433 	u32 p1_mpdgctrl1;
434 	/* read delay */
435 	u32 p0_mprddlctl;
436 	u32 p1_mprddlctl;
437 	/* write delay */
438 	u32 p0_mpwrdlctl;
439 	u32 p1_mpwrdlctl;
440 	/* lpddr2 zq hw calibration */
441 	u32 mpzqlp2ctl;
442 };
443 
444 /* configure iomux (pinctl/padctl) */
445 void mx6dq_dram_iocfg(unsigned width,
446 		      const struct mx6dq_iomux_ddr_regs *,
447 		      const struct mx6dq_iomux_grp_regs *);
448 void mx6sdl_dram_iocfg(unsigned width,
449 		       const struct mx6sdl_iomux_ddr_regs *,
450 		       const struct mx6sdl_iomux_grp_regs *);
451 void mx6sx_dram_iocfg(unsigned width,
452 		      const struct mx6sx_iomux_ddr_regs *,
453 		      const struct mx6sx_iomux_grp_regs *);
454 void mx6ul_dram_iocfg(unsigned width,
455 		      const struct mx6ul_iomux_ddr_regs *,
456 		      const struct mx6ul_iomux_grp_regs *);
457 void mx6sl_dram_iocfg(unsigned width,
458 		      const struct mx6sl_iomux_ddr_regs *,
459 		      const struct mx6sl_iomux_grp_regs *);
460 
461 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
462 int mmdc_do_write_level_calibration(void);
463 int mmdc_do_dqs_calibration(void);
464 #endif
465 
466 /* configure mx6 mmdc registers */
467 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
468 		  const struct mx6_mmdc_calibration *,
469 		  const void *);
470 
471 #endif /* CONFIG_SPL_BUILD */
472 
473 #define MX6_MMDC_P0_MDCTL	0x021b0000
474 #define MX6_MMDC_P0_MDPDC	0x021b0004
475 #define MX6_MMDC_P0_MDOTC	0x021b0008
476 #define MX6_MMDC_P0_MDCFG0	0x021b000c
477 #define MX6_MMDC_P0_MDCFG1	0x021b0010
478 #define MX6_MMDC_P0_MDCFG2	0x021b0014
479 #define MX6_MMDC_P0_MDMISC	0x021b0018
480 #define MX6_MMDC_P0_MDSCR	0x021b001c
481 #define MX6_MMDC_P0_MDREF	0x021b0020
482 #define MX6_MMDC_P0_MDRWD	0x021b002c
483 #define MX6_MMDC_P0_MDOR	0x021b0030
484 #define MX6_MMDC_P0_MDASP	0x021b0040
485 #define MX6_MMDC_P0_MAPSR	0x021b0404
486 #define MX6_MMDC_P0_MPZQHWCTRL	0x021b0800
487 #define MX6_MMDC_P0_MPWLDECTRL0	0x021b080c
488 #define MX6_MMDC_P0_MPWLDECTRL1	0x021b0810
489 #define MX6_MMDC_P0_MPODTCTRL	0x021b0818
490 #define MX6_MMDC_P0_MPRDDQBY0DL	0x021b081c
491 #define MX6_MMDC_P0_MPRDDQBY1DL	0x021b0820
492 #define MX6_MMDC_P0_MPRDDQBY2DL	0x021b0824
493 #define MX6_MMDC_P0_MPRDDQBY3DL	0x021b0828
494 #define MX6_MMDC_P0_MPDGCTRL0	0x021b083c
495 #define MX6_MMDC_P0_MPDGCTRL1	0x021b0840
496 #define MX6_MMDC_P0_MPRDDLCTL	0x021b0848
497 #define MX6_MMDC_P0_MPWRDLCTL	0x021b0850
498 #define MX6_MMDC_P0_MPMUR0	0x021b08b8
499 
500 #define MX6_MMDC_P1_MDCTL	0x021b4000
501 #define MX6_MMDC_P1_MDPDC	0x021b4004
502 #define MX6_MMDC_P1_MDOTC	0x021b4008
503 #define MX6_MMDC_P1_MDCFG0	0x021b400c
504 #define MX6_MMDC_P1_MDCFG1	0x021b4010
505 #define MX6_MMDC_P1_MDCFG2	0x021b4014
506 #define MX6_MMDC_P1_MDMISC	0x021b4018
507 #define MX6_MMDC_P1_MDSCR	0x021b401c
508 #define MX6_MMDC_P1_MDREF	0x021b4020
509 #define MX6_MMDC_P1_MDRWD	0x021b402c
510 #define MX6_MMDC_P1_MDOR	0x021b4030
511 #define MX6_MMDC_P1_MDASP	0x021b4040
512 #define MX6_MMDC_P1_MAPSR	0x021b4404
513 #define MX6_MMDC_P1_MPZQHWCTRL	0x021b4800
514 #define MX6_MMDC_P1_MPWLDECTRL0	0x021b480c
515 #define MX6_MMDC_P1_MPWLDECTRL1	0x021b4810
516 #define MX6_MMDC_P1_MPODTCTRL	0x021b4818
517 #define MX6_MMDC_P1_MPRDDQBY0DL	0x021b481c
518 #define MX6_MMDC_P1_MPRDDQBY1DL	0x021b4820
519 #define MX6_MMDC_P1_MPRDDQBY2DL	0x021b4824
520 #define MX6_MMDC_P1_MPRDDQBY3DL	0x021b4828
521 #define MX6_MMDC_P1_MPDGCTRL0	0x021b483c
522 #define MX6_MMDC_P1_MPDGCTRL1	0x021b4840
523 #define MX6_MMDC_P1_MPRDDLCTL	0x021b4848
524 #define MX6_MMDC_P1_MPWRDLCTL	0x021b4850
525 #define MX6_MMDC_P1_MPMUR0	0x021b48b8
526 
527 #endif	/*__ASM_ARCH_MX6_DDR_H__ */
528