1 /* 2 * Copyright (C) 2013 Boundary Devices Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __ASM_ARCH_MX6_DDR_H__ 7 #define __ASM_ARCH_MX6_DDR_H__ 8 9 #ifndef CONFIG_SPL_BUILD 10 #ifdef CONFIG_MX6Q 11 #include "mx6q-ddr.h" 12 #else 13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) 14 #include "mx6dl-ddr.h" 15 #else 16 #ifdef CONFIG_MX6SX 17 #include "mx6sx-ddr.h" 18 #else 19 #ifdef CONFIG_MX6UL 20 #include "mx6ul-ddr.h" 21 #else 22 #error "Please select cpu" 23 #endif /* CONFIG_MX6UL */ 24 #endif /* CONFIG_MX6SX */ 25 #endif /* CONFIG_MX6DL or CONFIG_MX6S */ 26 #endif /* CONFIG_MX6Q */ 27 #else 28 29 /* MMDC P0/P1 Registers */ 30 struct mmdc_p_regs { 31 u32 mdctl; 32 u32 mdpdc; 33 u32 mdotc; 34 u32 mdcfg0; 35 u32 mdcfg1; 36 u32 mdcfg2; 37 u32 mdmisc; 38 u32 mdscr; 39 u32 mdref; 40 u32 res1[2]; 41 u32 mdrwd; 42 u32 mdor; 43 u32 res2[3]; 44 u32 mdasp; 45 u32 res3[240]; 46 u32 mapsr; 47 u32 res4[254]; 48 u32 mpzqhwctrl; 49 u32 res5[2]; 50 u32 mpwldectrl0; 51 u32 mpwldectrl1; 52 u32 res6; 53 u32 mpodtctrl; 54 u32 mprddqby0dl; 55 u32 mprddqby1dl; 56 u32 mprddqby2dl; 57 u32 mprddqby3dl; 58 u32 res7[4]; 59 u32 mpdgctrl0; 60 u32 mpdgctrl1; 61 u32 res8; 62 u32 mprddlctl; 63 u32 res9; 64 u32 mpwrdlctl; 65 u32 res10[25]; 66 u32 mpmur0; 67 }; 68 69 #define MX6UL_IOM_DDR_BASE 0x020e0200 70 struct mx6ul_iomux_ddr_regs { 71 u32 res1[17]; 72 u32 dram_dqm0; 73 u32 dram_dqm1; 74 u32 dram_ras; 75 u32 dram_cas; 76 u32 dram_cs0; 77 u32 dram_cs1; 78 u32 dram_sdwe_b; 79 u32 dram_odt0; 80 u32 dram_odt1; 81 u32 dram_sdba0; 82 u32 dram_sdba1; 83 u32 dram_sdba2; 84 u32 dram_sdcke0; 85 u32 dram_sdcke1; 86 u32 dram_sdclk_0; 87 u32 dram_sdqs0; 88 u32 dram_sdqs1; 89 u32 dram_reset; 90 }; 91 92 #define MX6UL_IOM_GRP_BASE 0x020e0400 93 struct mx6ul_iomux_grp_regs { 94 u32 res1[36]; 95 u32 grp_addds; 96 u32 grp_ddrmode_ctl; 97 u32 grp_b0ds; 98 u32 grp_ddrpk; 99 u32 grp_ctlds; 100 u32 grp_b1ds; 101 u32 grp_ddrhys; 102 u32 grp_ddrpke; 103 u32 grp_ddrmode; 104 u32 grp_ddr_type; 105 }; 106 107 #define MX6SX_IOM_DDR_BASE 0x020e0200 108 struct mx6sx_iomux_ddr_regs { 109 u32 res1[59]; 110 u32 dram_dqm0; 111 u32 dram_dqm1; 112 u32 dram_dqm2; 113 u32 dram_dqm3; 114 u32 dram_ras; 115 u32 dram_cas; 116 u32 res2[2]; 117 u32 dram_sdwe_b; 118 u32 dram_odt0; 119 u32 dram_odt1; 120 u32 dram_sdba0; 121 u32 dram_sdba1; 122 u32 dram_sdba2; 123 u32 dram_sdcke0; 124 u32 dram_sdcke1; 125 u32 dram_sdclk_0; 126 u32 dram_sdqs0; 127 u32 dram_sdqs1; 128 u32 dram_sdqs2; 129 u32 dram_sdqs3; 130 u32 dram_reset; 131 }; 132 133 #define MX6SX_IOM_GRP_BASE 0x020e0500 134 struct mx6sx_iomux_grp_regs { 135 u32 res1[61]; 136 u32 grp_addds; 137 u32 grp_ddrmode_ctl; 138 u32 grp_ddrpke; 139 u32 grp_ddrpk; 140 u32 grp_ddrhys; 141 u32 grp_ddrmode; 142 u32 grp_b0ds; 143 u32 grp_b1ds; 144 u32 grp_ctlds; 145 u32 grp_ddr_type; 146 u32 grp_b2ds; 147 u32 grp_b3ds; 148 }; 149 150 /* 151 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL) 152 */ 153 #define MX6DQ_IOM_DDR_BASE 0x020e0500 154 struct mx6dq_iomux_ddr_regs { 155 u32 res1[3]; 156 u32 dram_sdqs5; 157 u32 dram_dqm5; 158 u32 dram_dqm4; 159 u32 dram_sdqs4; 160 u32 dram_sdqs3; 161 u32 dram_dqm3; 162 u32 dram_sdqs2; 163 u32 dram_dqm2; 164 u32 res2[16]; 165 u32 dram_cas; 166 u32 res3[2]; 167 u32 dram_ras; 168 u32 dram_reset; 169 u32 res4[2]; 170 u32 dram_sdclk_0; 171 u32 dram_sdba2; 172 u32 dram_sdcke0; 173 u32 dram_sdclk_1; 174 u32 dram_sdcke1; 175 u32 dram_sdodt0; 176 u32 dram_sdodt1; 177 u32 res5; 178 u32 dram_sdqs0; 179 u32 dram_dqm0; 180 u32 dram_sdqs1; 181 u32 dram_dqm1; 182 u32 dram_sdqs6; 183 u32 dram_dqm6; 184 u32 dram_sdqs7; 185 u32 dram_dqm7; 186 }; 187 188 #define MX6DQ_IOM_GRP_BASE 0x020e0700 189 struct mx6dq_iomux_grp_regs { 190 u32 res1[18]; 191 u32 grp_b7ds; 192 u32 grp_addds; 193 u32 grp_ddrmode_ctl; 194 u32 res2; 195 u32 grp_ddrpke; 196 u32 res3[6]; 197 u32 grp_ddrmode; 198 u32 res4[3]; 199 u32 grp_b0ds; 200 u32 grp_b1ds; 201 u32 grp_ctlds; 202 u32 res5; 203 u32 grp_b2ds; 204 u32 grp_ddr_type; 205 u32 grp_b3ds; 206 u32 grp_b4ds; 207 u32 grp_b5ds; 208 u32 grp_b6ds; 209 }; 210 211 #define MX6SDL_IOM_DDR_BASE 0x020e0400 212 struct mx6sdl_iomux_ddr_regs { 213 u32 res1[25]; 214 u32 dram_cas; 215 u32 res2[2]; 216 u32 dram_dqm0; 217 u32 dram_dqm1; 218 u32 dram_dqm2; 219 u32 dram_dqm3; 220 u32 dram_dqm4; 221 u32 dram_dqm5; 222 u32 dram_dqm6; 223 u32 dram_dqm7; 224 u32 dram_ras; 225 u32 dram_reset; 226 u32 res3[2]; 227 u32 dram_sdba2; 228 u32 dram_sdcke0; 229 u32 dram_sdcke1; 230 u32 dram_sdclk_0; 231 u32 dram_sdclk_1; 232 u32 dram_sdodt0; 233 u32 dram_sdodt1; 234 u32 dram_sdqs0; 235 u32 dram_sdqs1; 236 u32 dram_sdqs2; 237 u32 dram_sdqs3; 238 u32 dram_sdqs4; 239 u32 dram_sdqs5; 240 u32 dram_sdqs6; 241 u32 dram_sdqs7; 242 }; 243 244 #define MX6SDL_IOM_GRP_BASE 0x020e0700 245 struct mx6sdl_iomux_grp_regs { 246 u32 res1[18]; 247 u32 grp_b7ds; 248 u32 grp_addds; 249 u32 grp_ddrmode_ctl; 250 u32 grp_ddrpke; 251 u32 res2[2]; 252 u32 grp_ddrmode; 253 u32 grp_b0ds; 254 u32 res3; 255 u32 grp_ctlds; 256 u32 grp_b1ds; 257 u32 grp_ddr_type; 258 u32 grp_b2ds; 259 u32 grp_b3ds; 260 u32 grp_b4ds; 261 u32 grp_b5ds; 262 u32 res4; 263 u32 grp_b6ds; 264 }; 265 266 /* Device Information: Varies per DDR3 part number and speed grade */ 267 struct mx6_ddr3_cfg { 268 u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */ 269 u8 density; /* chip density (Gb) (1,2,4,8) */ 270 u8 width; /* bus width (bits) (4,8,16) */ 271 u8 banks; /* number of banks */ 272 u8 rowaddr; /* row address bits (11-16)*/ 273 u8 coladdr; /* col address bits (9-12) */ 274 u8 pagesz; /* page size (K) (1-2) */ 275 u16 trcd; /* tRCD=tRP=CL (ns*100) */ 276 u16 trcmin; /* tRC min (ns*100) */ 277 u16 trasmin; /* tRAS min (ns*100) */ 278 u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */ 279 }; 280 281 /* System Information: Varies per board design, layout, and term choices */ 282 struct mx6_ddr_sysinfo { 283 u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */ 284 u8 cs_density; /* density per chip select (Gb) */ 285 u8 ncs; /* number chip selects used (1|2) */ 286 char cs1_mirror;/* enable address mirror (0|1) */ 287 char bi_on; /* Bank interleaving enable */ 288 u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */ 289 u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */ 290 u8 ralat; /* Read Additional Latency (0-7) */ 291 u8 walat; /* Write Additional Latency (0-3) */ 292 u8 mif3_mode; /* Command prediction working mode */ 293 u8 rst_to_cke; /* Time from SDE enable to CKE rise */ 294 u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ 295 u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ 296 }; 297 298 /* 299 * Board specific calibration: 300 * This includes write leveling calibration values as well as DQS gating 301 * and read/write delays. These values are board/layout/device specific. 302 * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2 303 * (DOC-96412) to determine these values over a range of boards and 304 * temperatures. 305 */ 306 struct mx6_mmdc_calibration { 307 /* write leveling calibration */ 308 u32 p0_mpwldectrl0; 309 u32 p0_mpwldectrl1; 310 u32 p1_mpwldectrl0; 311 u32 p1_mpwldectrl1; 312 /* read DQS gating */ 313 u32 p0_mpdgctrl0; 314 u32 p0_mpdgctrl1; 315 u32 p1_mpdgctrl0; 316 u32 p1_mpdgctrl1; 317 /* read delay */ 318 u32 p0_mprddlctl; 319 u32 p1_mprddlctl; 320 /* write delay */ 321 u32 p0_mpwrdlctl; 322 u32 p1_mpwrdlctl; 323 }; 324 325 /* configure iomux (pinctl/padctl) */ 326 void mx6dq_dram_iocfg(unsigned width, 327 const struct mx6dq_iomux_ddr_regs *, 328 const struct mx6dq_iomux_grp_regs *); 329 void mx6sdl_dram_iocfg(unsigned width, 330 const struct mx6sdl_iomux_ddr_regs *, 331 const struct mx6sdl_iomux_grp_regs *); 332 void mx6sx_dram_iocfg(unsigned width, 333 const struct mx6sx_iomux_ddr_regs *, 334 const struct mx6sx_iomux_grp_regs *); 335 void mx6ul_dram_iocfg(unsigned width, 336 const struct mx6ul_iomux_ddr_regs *, 337 const struct mx6ul_iomux_grp_regs *); 338 339 /* configure mx6 mmdc registers */ 340 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, 341 const struct mx6_mmdc_calibration *, 342 const struct mx6_ddr3_cfg *); 343 344 #endif /* CONFIG_SPL_BUILD */ 345 346 #define MX6_MMDC_P0_MDCTL 0x021b0000 347 #define MX6_MMDC_P0_MDPDC 0x021b0004 348 #define MX6_MMDC_P0_MDOTC 0x021b0008 349 #define MX6_MMDC_P0_MDCFG0 0x021b000c 350 #define MX6_MMDC_P0_MDCFG1 0x021b0010 351 #define MX6_MMDC_P0_MDCFG2 0x021b0014 352 #define MX6_MMDC_P0_MDMISC 0x021b0018 353 #define MX6_MMDC_P0_MDSCR 0x021b001c 354 #define MX6_MMDC_P0_MDREF 0x021b0020 355 #define MX6_MMDC_P0_MDRWD 0x021b002c 356 #define MX6_MMDC_P0_MDOR 0x021b0030 357 #define MX6_MMDC_P0_MDASP 0x021b0040 358 #define MX6_MMDC_P0_MAPSR 0x021b0404 359 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800 360 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c 361 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810 362 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818 363 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c 364 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820 365 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824 366 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828 367 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c 368 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840 369 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848 370 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850 371 #define MX6_MMDC_P0_MPMUR0 0x021b08b8 372 373 #define MX6_MMDC_P1_MDCTL 0x021b4000 374 #define MX6_MMDC_P1_MDPDC 0x021b4004 375 #define MX6_MMDC_P1_MDOTC 0x021b4008 376 #define MX6_MMDC_P1_MDCFG0 0x021b400c 377 #define MX6_MMDC_P1_MDCFG1 0x021b4010 378 #define MX6_MMDC_P1_MDCFG2 0x021b4014 379 #define MX6_MMDC_P1_MDMISC 0x021b4018 380 #define MX6_MMDC_P1_MDSCR 0x021b401c 381 #define MX6_MMDC_P1_MDREF 0x021b4020 382 #define MX6_MMDC_P1_MDRWD 0x021b402c 383 #define MX6_MMDC_P1_MDOR 0x021b4030 384 #define MX6_MMDC_P1_MDASP 0x021b4040 385 #define MX6_MMDC_P1_MAPSR 0x021b4404 386 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800 387 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c 388 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810 389 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818 390 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c 391 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820 392 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824 393 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828 394 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c 395 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840 396 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848 397 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850 398 #define MX6_MMDC_P1_MPMUR0 0x021b48b8 399 400 #endif /*__ASM_ARCH_MX6_DDR_H__ */ 401