1 /*
2  * Copyright (C) 2013 Boundary Devices Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 #ifndef __ASM_ARCH_MX6_DDR_H__
7 #define __ASM_ARCH_MX6_DDR_H__
8 
9 #ifndef CONFIG_SPL_BUILD
10 #ifdef CONFIG_MX6Q
11 #include "mx6q-ddr.h"
12 #else
13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
14 #include "mx6dl-ddr.h"
15 #else
16 #ifdef CONFIG_MX6SX
17 #include "mx6sx-ddr.h"
18 #else
19 #error "Please select cpu"
20 #endif	/* CONFIG_MX6SX */
21 #endif	/* CONFIG_MX6DL or CONFIG_MX6S */
22 #endif	/* CONFIG_MX6Q */
23 #else
24 
25 /* MMDC P0/P1 Registers */
26 struct mmdc_p_regs {
27 	u32 mdctl;
28 	u32 mdpdc;
29 	u32 mdotc;
30 	u32 mdcfg0;
31 	u32 mdcfg1;
32 	u32 mdcfg2;
33 	u32 mdmisc;
34 	u32 mdscr;
35 	u32 mdref;
36 	u32 res1[2];
37 	u32 mdrwd;
38 	u32 mdor;
39 	u32 res2[3];
40 	u32 mdasp;
41 	u32 res3[240];
42 	u32 mapsr;
43 	u32 res4[254];
44 	u32 mpzqhwctrl;
45 	u32 res5[2];
46 	u32 mpwldectrl0;
47 	u32 mpwldectrl1;
48 	u32 res6;
49 	u32 mpodtctrl;
50 	u32 mprddqby0dl;
51 	u32 mprddqby1dl;
52 	u32 mprddqby2dl;
53 	u32 mprddqby3dl;
54 	u32 res7[4];
55 	u32 mpdgctrl0;
56 	u32 mpdgctrl1;
57 	u32 res8;
58 	u32 mprddlctl;
59 	u32 res9;
60 	u32 mpwrdlctl;
61 	u32 res10[25];
62 	u32 mpmur0;
63 };
64 
65 #define MX6SX_IOM_DDR_BASE	0x020e0200
66 struct mx6sx_iomux_ddr_regs {
67 	u32 res1[59];
68 	u32 dram_dqm0;
69 	u32 dram_dqm1;
70 	u32 dram_dqm2;
71 	u32 dram_dqm3;
72 	u32 dram_ras;
73 	u32 dram_cas;
74 	u32 res2[2];
75 	u32 dram_sdwe_b;
76 	u32 dram_odt0;
77 	u32 dram_odt1;
78 	u32 dram_sdba0;
79 	u32 dram_sdba1;
80 	u32 dram_sdba2;
81 	u32 dram_sdcke0;
82 	u32 dram_sdcke1;
83 	u32 dram_sdclk_0;
84 	u32 dram_sdqs0;
85 	u32 dram_sdqs1;
86 	u32 dram_sdqs2;
87 	u32 dram_sdqs3;
88 	u32 dram_reset;
89 };
90 
91 #define MX6SX_IOM_GRP_BASE	0x020e0500
92 struct mx6sx_iomux_grp_regs {
93 	u32 res1[61];
94 	u32 grp_addds;
95 	u32 grp_ddrmode_ctl;
96 	u32 grp_ddrpke;
97 	u32 grp_ddrpk;
98 	u32 grp_ddrhys;
99 	u32 grp_ddrmode;
100 	u32 grp_b0ds;
101 	u32 grp_b1ds;
102 	u32 grp_ctlds;
103 	u32 grp_ddr_type;
104 	u32 grp_b2ds;
105 	u32 grp_b3ds;
106 };
107 
108 /*
109  * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
110  */
111 #define MX6DQ_IOM_DDR_BASE      0x020e0500
112 struct mx6dq_iomux_ddr_regs {
113 	u32 res1[3];
114 	u32 dram_sdqs5;
115 	u32 dram_dqm5;
116 	u32 dram_dqm4;
117 	u32 dram_sdqs4;
118 	u32 dram_sdqs3;
119 	u32 dram_dqm3;
120 	u32 dram_sdqs2;
121 	u32 dram_dqm2;
122 	u32 res2[16];
123 	u32 dram_cas;
124 	u32 res3[2];
125 	u32 dram_ras;
126 	u32 dram_reset;
127 	u32 res4[2];
128 	u32 dram_sdclk_0;
129 	u32 dram_sdba2;
130 	u32 dram_sdcke0;
131 	u32 dram_sdclk_1;
132 	u32 dram_sdcke1;
133 	u32 dram_sdodt0;
134 	u32 dram_sdodt1;
135 	u32 res5;
136 	u32 dram_sdqs0;
137 	u32 dram_dqm0;
138 	u32 dram_sdqs1;
139 	u32 dram_dqm1;
140 	u32 dram_sdqs6;
141 	u32 dram_dqm6;
142 	u32 dram_sdqs7;
143 	u32 dram_dqm7;
144 };
145 
146 #define MX6DQ_IOM_GRP_BASE      0x020e0700
147 struct mx6dq_iomux_grp_regs {
148 	u32 res1[18];
149 	u32 grp_b7ds;
150 	u32 grp_addds;
151 	u32 grp_ddrmode_ctl;
152 	u32 res2;
153 	u32 grp_ddrpke;
154 	u32 res3[6];
155 	u32 grp_ddrmode;
156 	u32 res4[3];
157 	u32 grp_b0ds;
158 	u32 grp_b1ds;
159 	u32 grp_ctlds;
160 	u32 res5;
161 	u32 grp_b2ds;
162 	u32 grp_ddr_type;
163 	u32 grp_b3ds;
164 	u32 grp_b4ds;
165 	u32 grp_b5ds;
166 	u32 grp_b6ds;
167 };
168 
169 #define MX6SDL_IOM_DDR_BASE     0x020e0400
170 struct mx6sdl_iomux_ddr_regs {
171 	u32 res1[25];
172 	u32 dram_cas;
173 	u32 res2[2];
174 	u32 dram_dqm0;
175 	u32 dram_dqm1;
176 	u32 dram_dqm2;
177 	u32 dram_dqm3;
178 	u32 dram_dqm4;
179 	u32 dram_dqm5;
180 	u32 dram_dqm6;
181 	u32 dram_dqm7;
182 	u32 dram_ras;
183 	u32 dram_reset;
184 	u32 res3[2];
185 	u32 dram_sdba2;
186 	u32 dram_sdcke0;
187 	u32 dram_sdcke1;
188 	u32 dram_sdclk_0;
189 	u32 dram_sdclk_1;
190 	u32 dram_sdodt0;
191 	u32 dram_sdodt1;
192 	u32 dram_sdqs0;
193 	u32 dram_sdqs1;
194 	u32 dram_sdqs2;
195 	u32 dram_sdqs3;
196 	u32 dram_sdqs4;
197 	u32 dram_sdqs5;
198 	u32 dram_sdqs6;
199 	u32 dram_sdqs7;
200 };
201 
202 #define MX6SDL_IOM_GRP_BASE     0x020e0700
203 struct mx6sdl_iomux_grp_regs {
204 	u32 res1[18];
205 	u32 grp_b7ds;
206 	u32 grp_addds;
207 	u32 grp_ddrmode_ctl;
208 	u32 grp_ddrpke;
209 	u32 res2[2];
210 	u32 grp_ddrmode;
211 	u32 grp_b0ds;
212 	u32 res3;
213 	u32 grp_ctlds;
214 	u32 grp_b1ds;
215 	u32 grp_ddr_type;
216 	u32 grp_b2ds;
217 	u32 grp_b3ds;
218 	u32 grp_b4ds;
219 	u32 grp_b5ds;
220 	u32 res4;
221 	u32 grp_b6ds;
222 };
223 
224 /* Device Information: Varies per DDR3 part number and speed grade */
225 struct mx6_ddr3_cfg {
226 	u16 mem_speed;	/* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
227 	u8 density;	/* chip density (Gb) (1,2,4,8) */
228 	u8 width;	/* bus width (bits) (4,8,16) */
229 	u8 banks;	/* number of banks */
230 	u8 rowaddr;	/* row address bits (11-16)*/
231 	u8 coladdr;	/* col address bits (9-12) */
232 	u8 pagesz;	/* page size (K) (1-2) */
233 	u16 trcd;	/* tRCD=tRP=CL (ns*100) */
234 	u16 trcmin;	/* tRC min (ns*100) */
235 	u16 trasmin;	/* tRAS min (ns*100) */
236 	u8 SRT;		/* self-refresh temperature: 0=normal, 1=extended */
237 };
238 
239 /* System Information: Varies per board design, layout, and term choices */
240 struct mx6_ddr_sysinfo {
241 	u8 dsize;	/* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
242 	u8 cs_density;	/* density per chip select (Gb) */
243 	u8 ncs;		/* number chip selects used (1|2) */
244 	char cs1_mirror;/* enable address mirror (0|1) */
245 	char bi_on;	/* Bank interleaving enable */
246 	u8 rtt_nom;	/* Rtt_Nom (DDR3_RTT_*) */
247 	u8 rtt_wr;	/* Rtt_Wr (DDR3_RTT_*) */
248 	u8 ralat;	/* Read Additional Latency (0-7) */
249 	u8 walat;	/* Write Additional Latency (0-3) */
250 	u8 mif3_mode;	/* Command prediction working mode */
251 	u8 rst_to_cke;	/* Time from SDE enable to CKE rise */
252 	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
253 };
254 
255 /*
256  * Board specific calibration:
257  *   This includes write leveling calibration values as well as DQS gating
258  *   and read/write delays. These values are board/layout/device specific.
259  *   Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
260  *   (DOC-96412) to determine these values over a range of boards and
261  *   temperatures.
262  */
263 struct mx6_mmdc_calibration {
264 	/* write leveling calibration */
265 	u32 p0_mpwldectrl0;
266 	u32 p0_mpwldectrl1;
267 	u32 p1_mpwldectrl0;
268 	u32 p1_mpwldectrl1;
269 	/* read DQS gating */
270 	u32 p0_mpdgctrl0;
271 	u32 p0_mpdgctrl1;
272 	u32 p1_mpdgctrl0;
273 	u32 p1_mpdgctrl1;
274 	/* read delay */
275 	u32 p0_mprddlctl;
276 	u32 p1_mprddlctl;
277 	/* write delay */
278 	u32 p0_mpwrdlctl;
279 	u32 p1_mpwrdlctl;
280 };
281 
282 /* configure iomux (pinctl/padctl) */
283 void mx6dq_dram_iocfg(unsigned width,
284 		      const struct mx6dq_iomux_ddr_regs *,
285 		      const struct mx6dq_iomux_grp_regs *);
286 void mx6sdl_dram_iocfg(unsigned width,
287 		       const struct mx6sdl_iomux_ddr_regs *,
288 		       const struct mx6sdl_iomux_grp_regs *);
289 void mx6sx_dram_iocfg(unsigned width,
290 		      const struct mx6sx_iomux_ddr_regs *,
291 		      const struct mx6sx_iomux_grp_regs *);
292 
293 /* configure mx6 mmdc registers */
294 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
295 		  const struct mx6_mmdc_calibration *,
296 		  const struct mx6_ddr3_cfg *);
297 
298 #endif /* CONFIG_SPL_BUILD */
299 
300 #define MX6_MMDC_P0_MDCTL	0x021b0000
301 #define MX6_MMDC_P0_MDPDC	0x021b0004
302 #define MX6_MMDC_P0_MDOTC	0x021b0008
303 #define MX6_MMDC_P0_MDCFG0	0x021b000c
304 #define MX6_MMDC_P0_MDCFG1	0x021b0010
305 #define MX6_MMDC_P0_MDCFG2	0x021b0014
306 #define MX6_MMDC_P0_MDMISC	0x021b0018
307 #define MX6_MMDC_P0_MDSCR	0x021b001c
308 #define MX6_MMDC_P0_MDREF	0x021b0020
309 #define MX6_MMDC_P0_MDRWD	0x021b002c
310 #define MX6_MMDC_P0_MDOR	0x021b0030
311 #define MX6_MMDC_P0_MDASP	0x021b0040
312 #define MX6_MMDC_P0_MAPSR	0x021b0404
313 #define MX6_MMDC_P0_MPZQHWCTRL	0x021b0800
314 #define MX6_MMDC_P0_MPWLDECTRL0	0x021b080c
315 #define MX6_MMDC_P0_MPWLDECTRL1	0x021b0810
316 #define MX6_MMDC_P0_MPODTCTRL	0x021b0818
317 #define MX6_MMDC_P0_MPRDDQBY0DL	0x021b081c
318 #define MX6_MMDC_P0_MPRDDQBY1DL	0x021b0820
319 #define MX6_MMDC_P0_MPRDDQBY2DL	0x021b0824
320 #define MX6_MMDC_P0_MPRDDQBY3DL	0x021b0828
321 #define MX6_MMDC_P0_MPDGCTRL0	0x021b083c
322 #define MX6_MMDC_P0_MPDGCTRL1	0x021b0840
323 #define MX6_MMDC_P0_MPRDDLCTL	0x021b0848
324 #define MX6_MMDC_P0_MPWRDLCTL	0x021b0850
325 #define MX6_MMDC_P0_MPMUR0	0x021b08b8
326 
327 #define MX6_MMDC_P1_MDCTL	0x021b4000
328 #define MX6_MMDC_P1_MDPDC	0x021b4004
329 #define MX6_MMDC_P1_MDOTC	0x021b4008
330 #define MX6_MMDC_P1_MDCFG0	0x021b400c
331 #define MX6_MMDC_P1_MDCFG1	0x021b4010
332 #define MX6_MMDC_P1_MDCFG2	0x021b4014
333 #define MX6_MMDC_P1_MDMISC	0x021b4018
334 #define MX6_MMDC_P1_MDSCR	0x021b401c
335 #define MX6_MMDC_P1_MDREF	0x021b4020
336 #define MX6_MMDC_P1_MDRWD	0x021b402c
337 #define MX6_MMDC_P1_MDOR	0x021b4030
338 #define MX6_MMDC_P1_MDASP	0x021b4040
339 #define MX6_MMDC_P1_MAPSR	0x021b4404
340 #define MX6_MMDC_P1_MPZQHWCTRL	0x021b4800
341 #define MX6_MMDC_P1_MPWLDECTRL0	0x021b480c
342 #define MX6_MMDC_P1_MPWLDECTRL1	0x021b4810
343 #define MX6_MMDC_P1_MPODTCTRL	0x021b4818
344 #define MX6_MMDC_P1_MPRDDQBY0DL	0x021b481c
345 #define MX6_MMDC_P1_MPRDDQBY1DL	0x021b4820
346 #define MX6_MMDC_P1_MPRDDQBY2DL	0x021b4824
347 #define MX6_MMDC_P1_MPRDDQBY3DL	0x021b4828
348 #define MX6_MMDC_P1_MPDGCTRL0	0x021b483c
349 #define MX6_MMDC_P1_MPDGCTRL1	0x021b4840
350 #define MX6_MMDC_P1_MPRDDLCTL	0x021b4848
351 #define MX6_MMDC_P1_MPWRDLCTL	0x021b4850
352 #define MX6_MMDC_P1_MPMUR0	0x021b48b8
353 
354 #endif	/*__ASM_ARCH_MX6_DDR_H__ */
355