1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2d1c679a4STroy Kisky 3d1c679a4STroy Kisky #ifndef __ASM_ARCH_IOMUX_H__ 4d1c679a4STroy Kisky #define __ASM_ARCH_IOMUX_H__ 5714afa64SEric Nelson 6714afa64SEric Nelson #define MX6_IOMUXC_GPR4 0x020e0010 7714afa64SEric Nelson #define MX6_IOMUXC_GPR6 0x020e0018 8714afa64SEric Nelson #define MX6_IOMUXC_GPR7 0x020e001c 9714afa64SEric Nelson 10d1c679a4STroy Kisky /* 117132869dSTroy Kisky * IOMUXC_GPR1 bit fields 127132869dSTroy Kisky */ 137132869dSTroy Kisky #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) 147132869dSTroy Kisky #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) 157132869dSTroy Kisky #define IOMUXC_GPR1_OTG_ID_MASK (1<<13) 16e9be4292SMarek Vasut #define IOMUXC_GPR1_REF_SSP_EN (1 << 16) 17e9be4292SMarek Vasut #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) 18e9be4292SMarek Vasut 19aaf87f03SFabio Estevam #define IOMUXC_GPR1_PCIE_SW_RST (1 << 29) 20aaf87f03SFabio Estevam 21e9be4292SMarek Vasut /* 221b8ad74aSFabio Estevam * IOMUXC_GPR5 bit fields 231b8ad74aSFabio Estevam */ 241b8ad74aSFabio Estevam #define IOMUXC_GPR5_PCIE_BTNRST (1 << 19) 251b8ad74aSFabio Estevam #define IOMUXC_GPR5_PCIE_PERST (1 << 18) 261b8ad74aSFabio Estevam 271b8ad74aSFabio Estevam /* 28e9be4292SMarek Vasut * IOMUXC_GPR8 bit fields 29e9be4292SMarek Vasut */ 30e9be4292SMarek Vasut #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) 31e9be4292SMarek Vasut #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 32e9be4292SMarek Vasut #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) 33e9be4292SMarek Vasut #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6 34e9be4292SMarek Vasut #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12) 35e9be4292SMarek Vasut #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 36e9be4292SMarek Vasut #define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) 37e9be4292SMarek Vasut #define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 38e9be4292SMarek Vasut #define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) 39e9be4292SMarek Vasut #define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25 40e9be4292SMarek Vasut 41e9be4292SMarek Vasut /* 42e9be4292SMarek Vasut * IOMUXC_GPR12 bit fields 43e9be4292SMarek Vasut */ 441b8ad74aSFabio Estevam #define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0) 451b8ad74aSFabio Estevam #define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0) 46e9be4292SMarek Vasut #define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) 47e9be4292SMarek Vasut #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) 48e9be4292SMarek Vasut #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) 49e9be4292SMarek Vasut #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) 50bad40e08SFabio Estevam #define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12) 51e9be4292SMarek Vasut #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) 521b8ad74aSFabio Estevam #define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30) 53e9be4292SMarek Vasut 547132869dSTroy Kisky /* 55d1c679a4STroy Kisky * IOMUXC_GPR13 bit fields 56d1c679a4STroy Kisky */ 57d1c679a4STroy Kisky #define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30) 58d1c679a4STroy Kisky #define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29) 59d1c679a4STroy Kisky #define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28) 60d1c679a4STroy Kisky #define IOMUXC_GPR13_ENET_STOP_REQ (1<<27) 61d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24) 62d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19) 63d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16 64d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) 65d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15) 66d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14) 67d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11) 68d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7) 69d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) 70d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) 71d1c679a4STroy Kisky 7231f07964SFabio Estevam #define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) 7331f07964SFabio Estevam #define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) 7431f07964SFabio Estevam #define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \ 7531f07964SFabio Estevam | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK) 7631f07964SFabio Estevam 77d145878dSFabio Estevam #define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17) 78d145878dSFabio Estevam #define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13) 79d145878dSFabio Estevam #define IOMUX_GPR1_FEC1_MASK (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \ 80d145878dSFabio Estevam | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK) 81d145878dSFabio Estevam 82d145878dSFabio Estevam #define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18) 83d145878dSFabio Estevam #define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14) 84d145878dSFabio Estevam #define IOMUX_GPR1_FEC2_MASK (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \ 85d145878dSFabio Estevam | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK) 86d145878dSFabio Estevam 8719f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) 8819f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) 8919f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) 9019f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24) 9119f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24) 9219f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24) 9319f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24) 9419f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24) 95d1c679a4STroy Kisky 9619f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19) 9719f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19) 9819f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19) 9919f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19) 10019f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19) 10119f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19) 102d1c679a4STroy Kisky 103d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15) 104d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SPEED_3G (1<<15) 105d1c679a4STroy Kisky 106d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14) 107d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14) 108d1c679a4STroy Kisky 109d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11) 110d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11) 111d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11) 112d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11) 113d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11) 114d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11) 115d1c679a4STroy Kisky 11619f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7) 11719f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7) 11819f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7) 11919f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7) 12019f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7) 12119f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7) 12219f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7) 12319f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7) 12419f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7) 12519f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7) 12619f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7) 12719f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7) 12819f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7) 12919f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7) 13019f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7) 13119f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7) 132d1c679a4STroy Kisky 13319f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2) 13419f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2) 13519f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2) 13619f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2) 13719f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2) 13819f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2) 13919f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2) 14019f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2) 14119f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2) 14219f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2) 14319f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2) 14419f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2) 14519f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2) 14619f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2) 14719f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2) 14819f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2) 14919f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2) 15019f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2) 15119f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2) 15219f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2) 15319f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2) 15419f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2) 15519f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2) 15619f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2) 15719f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2) 15819f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2) 15919f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2) 16019f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2) 16119f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2) 16219f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2) 16319f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2) 16419f59ea6SStefano Babic #define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2) 165d1c679a4STroy Kisky 166d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_1_FAST 0 167d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1 168d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_PHY_1_SLOW 2 169d1c679a4STroy Kisky 170d1c679a4STroy Kisky #define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \ 171d1c679a4STroy Kisky |IOMUXC_GPR13_SATA_PHY_7_MASK \ 172d1c679a4STroy Kisky |IOMUXC_GPR13_SATA_PHY_6_MASK \ 173d1c679a4STroy Kisky |IOMUXC_GPR13_SATA_SPEED_MASK \ 174d1c679a4STroy Kisky |IOMUXC_GPR13_SATA_PHY_5_MASK \ 175d1c679a4STroy Kisky |IOMUXC_GPR13_SATA_PHY_4_MASK \ 176d1c679a4STroy Kisky |IOMUXC_GPR13_SATA_PHY_3_MASK \ 177d1c679a4STroy Kisky |IOMUXC_GPR13_SATA_PHY_2_MASK \ 178d1c679a4STroy Kisky |IOMUXC_GPR13_SATA_PHY_1_MASK) 179ec1b2697SLukasz Majewski 180ec1b2697SLukasz Majewski /* 181ec1b2697SLukasz Majewski * Setup RGMII voltage levels on iMX6 SoC - the 182ec1b2697SLukasz Majewski * 183ec1b2697SLukasz Majewski * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - register 184ec1b2697SLukasz Majewski * 185ec1b2697SLukasz Majewski * 1P2V_IO - USB_HSIC, MIPI_HSI 186ec1b2697SLukasz Majewski * 1P5V_IO - ENET pins 187ec1b2697SLukasz Majewski */ 188ec1b2697SLukasz Majewski #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x020e0790 189ec1b2697SLukasz Majewski #define DDR_SEL_1P2V_IO (0x2 << 18) 190ec1b2697SLukasz Majewski #define DDR_SEL_1P5V_IO (0x3 << 18) 191ec1b2697SLukasz Majewski 192d1c679a4STroy Kisky #endif /* __ASM_ARCH_IOMUX_H__ */ 193