1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 17 */ 18 19 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 20 #define __ASM_ARCH_MX6_IMX_REGS_H__ 21 22 #define CONFIG_SYS_CACHELINE_SIZE 32 23 24 #define ROMCP_ARB_BASE_ADDR 0x00000000 25 #define ROMCP_ARB_END_ADDR 0x000FFFFF 26 #define CAAM_ARB_BASE_ADDR 0x00100000 27 #define CAAM_ARB_END_ADDR 0x00103FFF 28 #define APBH_DMA_ARB_BASE_ADDR 0x00110000 29 #define APBH_DMA_ARB_END_ADDR 0x00117FFF 30 #define HDMI_ARB_BASE_ADDR 0x00120000 31 #define HDMI_ARB_END_ADDR 0x00128FFF 32 #define GPU_3D_ARB_BASE_ADDR 0x00130000 33 #define GPU_3D_ARB_END_ADDR 0x00133FFF 34 #define GPU_2D_ARB_BASE_ADDR 0x00134000 35 #define GPU_2D_ARB_END_ADDR 0x00137FFF 36 #define DTCP_ARB_BASE_ADDR 0x00138000 37 #define DTCP_ARB_END_ADDR 0x0013BFFF 38 39 /* GPV - PL301 configuration ports */ 40 #define GPV2_BASE_ADDR 0x00200000 41 #define GPV3_BASE_ADDR 0x00300000 42 #define GPV4_BASE_ADDR 0x00800000 43 #define IRAM_BASE_ADDR 0x00900000 44 #define SCU_BASE_ADDR 0x00A00000 45 #define IC_INTERFACES_BASE_ADDR 0x00A00100 46 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 47 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 48 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 49 #define GPV0_BASE_ADDR 0x00B00000 50 #define GPV1_BASE_ADDR 0x00C00000 51 #define PCIE_ARB_BASE_ADDR 0x01000000 52 #define PCIE_ARB_END_ADDR 0x01FFFFFF 53 54 #define AIPS1_ARB_BASE_ADDR 0x02000000 55 #define AIPS1_ARB_END_ADDR 0x020FFFFF 56 #define AIPS2_ARB_BASE_ADDR 0x02100000 57 #define AIPS2_ARB_END_ADDR 0x021FFFFF 58 #define SATA_ARB_BASE_ADDR 0x02200000 59 #define SATA_ARB_END_ADDR 0x02203FFF 60 #define OPENVG_ARB_BASE_ADDR 0x02204000 61 #define OPENVG_ARB_END_ADDR 0x02207FFF 62 #define HSI_ARB_BASE_ADDR 0x02208000 63 #define HSI_ARB_END_ADDR 0x0220BFFF 64 #define IPU1_ARB_BASE_ADDR 0x02400000 65 #define IPU1_ARB_END_ADDR 0x027FFFFF 66 #define IPU2_ARB_BASE_ADDR 0x02800000 67 #define IPU2_ARB_END_ADDR 0x02BFFFFF 68 #define WEIM_ARB_BASE_ADDR 0x08000000 69 #define WEIM_ARB_END_ADDR 0x0FFFFFFF 70 71 #define MMDC0_ARB_BASE_ADDR 0x10000000 72 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF 73 #define MMDC1_ARB_BASE_ADDR 0x80000000 74 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 75 76 /* Defines for Blocks connected via AIPS (SkyBlue) */ 77 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 78 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 79 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 80 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 81 82 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 83 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 84 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 85 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 86 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 87 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 88 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 89 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 90 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 91 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 92 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 93 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 94 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 95 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 96 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 97 98 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 99 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 100 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 101 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 102 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 103 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 104 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 105 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 106 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 107 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 108 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 109 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 110 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 111 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 112 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 113 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 114 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 115 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 116 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 117 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 118 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 119 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 120 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 121 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 122 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 123 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 124 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 125 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 126 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 127 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 128 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 129 130 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 131 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 132 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 133 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 134 #define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 135 #define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 136 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 137 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 138 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 139 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 140 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 141 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 142 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 143 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 144 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 145 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 146 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 147 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 148 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 149 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 150 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 151 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 152 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 153 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 154 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 155 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 156 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 157 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 158 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 159 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 160 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 161 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 162 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 163 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 164 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 165 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 166 167 #define CHIP_REV_1_0 0x10 168 #define IRAM_SIZE 0x00040000 169 #define IMX_IIM_BASE OCOTP_BASE_ADDR 170 #define FEC_QUIRK_ENET_MAC 171 172 #define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31)) 173 174 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 175 #include <asm/types.h> 176 177 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 178 179 /* System Reset Controller (SRC) */ 180 struct src { 181 u32 scr; 182 u32 sbmr1; 183 u32 srsr; 184 u32 reserved1[2]; 185 u32 sisr; 186 u32 simr; 187 u32 sbmr2; 188 u32 gpr1; 189 u32 gpr2; 190 u32 gpr3; 191 u32 gpr4; 192 u32 gpr5; 193 u32 gpr6; 194 u32 gpr7; 195 u32 gpr8; 196 u32 gpr9; 197 u32 gpr10; 198 }; 199 200 /* ECSPI registers */ 201 struct cspi_regs { 202 u32 rxdata; 203 u32 txdata; 204 u32 ctrl; 205 u32 cfg; 206 u32 intr; 207 u32 dma; 208 u32 stat; 209 u32 period; 210 }; 211 212 /* 213 * CSPI register definitions 214 */ 215 #define MXC_ECSPI 216 #define MXC_CSPICTRL_EN (1 << 0) 217 #define MXC_CSPICTRL_MODE (1 << 1) 218 #define MXC_CSPICTRL_XCH (1 << 2) 219 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 220 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 221 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 222 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 223 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 224 #define MXC_CSPICTRL_MAXBITS 0xfff 225 #define MXC_CSPICTRL_TC (1 << 7) 226 #define MXC_CSPICTRL_RXOVF (1 << 6) 227 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 228 #define MAX_SPI_BYTES 32 229 230 /* Bit position inside CTRL register to be associated with SS */ 231 #define MXC_CSPICTRL_CHAN 18 232 233 /* Bit position inside CON register to be associated with SS */ 234 #define MXC_CSPICON_POL 4 235 #define MXC_CSPICON_PHA 0 236 #define MXC_CSPICON_SSPOL 12 237 #define MXC_SPI_BASE_ADDRESSES \ 238 ECSPI1_BASE_ADDR, \ 239 ECSPI2_BASE_ADDR, \ 240 ECSPI3_BASE_ADDR, \ 241 ECSPI4_BASE_ADDR, \ 242 ECSPI5_BASE_ADDR 243 244 struct iim_regs { 245 u32 ctrl; 246 u32 ctrl_set; 247 u32 ctrl_clr; 248 u32 ctrl_tog; 249 u32 timing; 250 u32 rsvd0[3]; 251 u32 data; 252 u32 rsvd1[3]; 253 u32 read_ctrl; 254 u32 rsvd2[3]; 255 u32 fuse_data; 256 u32 rsvd3[3]; 257 u32 sticky; 258 u32 rsvd4[3]; 259 u32 scs; 260 u32 scs_set; 261 u32 scs_clr; 262 u32 scs_tog; 263 u32 crc_addr; 264 u32 rsvd5[3]; 265 u32 crc_value; 266 u32 rsvd6[3]; 267 u32 version; 268 u32 rsvd7[0xdb]; 269 270 struct fuse_bank { 271 u32 fuse_regs[0x20]; 272 } bank[15]; 273 }; 274 275 struct fuse_bank4_regs { 276 u32 sjc_resp_low; 277 u32 rsvd0[3]; 278 u32 sjc_resp_high; 279 u32 rsvd1[3]; 280 u32 mac_addr_low; 281 u32 rsvd2[3]; 282 u32 mac_addr_high; 283 u32 rsvd3[0x13]; 284 }; 285 286 struct aipstz_regs { 287 u32 mprot0; 288 u32 mprot1; 289 u32 rsvd[0xe]; 290 u32 opacr0; 291 u32 opacr1; 292 u32 opacr2; 293 u32 opacr3; 294 u32 opacr4; 295 }; 296 297 struct anatop_regs { 298 u32 pll_sys; /* 0x000 */ 299 u32 pll_sys_set; /* 0x004 */ 300 u32 pll_sys_clr; /* 0x008 */ 301 u32 pll_sys_tog; /* 0x00c */ 302 u32 usb1_pll_480_ctrl; /* 0x010 */ 303 u32 usb1_pll_480_ctrl_set; /* 0x014 */ 304 u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 305 u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 306 u32 usb2_pll_480_ctrl; /* 0x020 */ 307 u32 usb2_pll_480_ctrl_set; /* 0x024 */ 308 u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 309 u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 310 u32 pll_528; /* 0x030 */ 311 u32 pll_528_set; /* 0x034 */ 312 u32 pll_528_clr; /* 0x038 */ 313 u32 pll_528_tog; /* 0x03c */ 314 u32 pll_528_ss; /* 0x040 */ 315 u32 rsvd0[3]; 316 u32 pll_528_num; /* 0x050 */ 317 u32 rsvd1[3]; 318 u32 pll_528_denom; /* 0x060 */ 319 u32 rsvd2[3]; 320 u32 pll_audio; /* 0x070 */ 321 u32 pll_audio_set; /* 0x074 */ 322 u32 pll_audio_clr; /* 0x078 */ 323 u32 pll_audio_tog; /* 0x07c */ 324 u32 pll_audio_num; /* 0x080 */ 325 u32 rsvd3[3]; 326 u32 pll_audio_denom; /* 0x090 */ 327 u32 rsvd4[3]; 328 u32 pll_video; /* 0x0a0 */ 329 u32 pll_video_set; /* 0x0a4 */ 330 u32 pll_video_clr; /* 0x0a8 */ 331 u32 pll_video_tog; /* 0x0ac */ 332 u32 pll_video_num; /* 0x0b0 */ 333 u32 rsvd5[3]; 334 u32 pll_video_denom; /* 0x0c0 */ 335 u32 rsvd6[3]; 336 u32 pll_mlb; /* 0x0d0 */ 337 u32 pll_mlb_set; /* 0x0d4 */ 338 u32 pll_mlb_clr; /* 0x0d8 */ 339 u32 pll_mlb_tog; /* 0x0dc */ 340 u32 pll_enet; /* 0x0e0 */ 341 u32 pll_enet_set; /* 0x0e4 */ 342 u32 pll_enet_clr; /* 0x0e8 */ 343 u32 pll_enet_tog; /* 0x0ec */ 344 u32 pfd_480; /* 0x0f0 */ 345 u32 pfd_480_set; /* 0x0f4 */ 346 u32 pfd_480_clr; /* 0x0f8 */ 347 u32 pfd_480_tog; /* 0x0fc */ 348 u32 pfd_528; /* 0x100 */ 349 u32 pfd_528_set; /* 0x104 */ 350 u32 pfd_528_clr; /* 0x108 */ 351 u32 pfd_528_tog; /* 0x10c */ 352 u32 reg_1p1; /* 0x110 */ 353 u32 reg_1p1_set; /* 0x114 */ 354 u32 reg_1p1_clr; /* 0x118 */ 355 u32 reg_1p1_tog; /* 0x11c */ 356 u32 reg_3p0; /* 0x120 */ 357 u32 reg_3p0_set; /* 0x124 */ 358 u32 reg_3p0_clr; /* 0x128 */ 359 u32 reg_3p0_tog; /* 0x12c */ 360 u32 reg_2p5; /* 0x130 */ 361 u32 reg_2p5_set; /* 0x134 */ 362 u32 reg_2p5_clr; /* 0x138 */ 363 u32 reg_2p5_tog; /* 0x13c */ 364 u32 reg_core; /* 0x140 */ 365 u32 reg_core_set; /* 0x144 */ 366 u32 reg_core_clr; /* 0x148 */ 367 u32 reg_core_tog; /* 0x14c */ 368 u32 ana_misc0; /* 0x150 */ 369 u32 ana_misc0_set; /* 0x154 */ 370 u32 ana_misc0_clr; /* 0x158 */ 371 u32 ana_misc0_tog; /* 0x15c */ 372 u32 ana_misc1; /* 0x160 */ 373 u32 ana_misc1_set; /* 0x164 */ 374 u32 ana_misc1_clr; /* 0x168 */ 375 u32 ana_misc1_tog; /* 0x16c */ 376 u32 ana_misc2; /* 0x170 */ 377 u32 ana_misc2_set; /* 0x174 */ 378 u32 ana_misc2_clr; /* 0x178 */ 379 u32 ana_misc2_tog; /* 0x17c */ 380 u32 tempsense0; /* 0x180 */ 381 u32 tempsense0_set; /* 0x184 */ 382 u32 tempsense0_clr; /* 0x188 */ 383 u32 tempsense0_tog; /* 0x18c */ 384 u32 tempsense1; /* 0x190 */ 385 u32 tempsense1_set; /* 0x194 */ 386 u32 tempsense1_clr; /* 0x198 */ 387 u32 tempsense1_tog; /* 0x19c */ 388 u32 usb1_vbus_detect; /* 0x1a0 */ 389 u32 usb1_vbus_detect_set; /* 0x1a4 */ 390 u32 usb1_vbus_detect_clr; /* 0x1a8 */ 391 u32 usb1_vbus_detect_tog; /* 0x1ac */ 392 u32 usb1_chrg_detect; /* 0x1b0 */ 393 u32 usb1_chrg_detect_set; /* 0x1b4 */ 394 u32 usb1_chrg_detect_clr; /* 0x1b8 */ 395 u32 usb1_chrg_detect_tog; /* 0x1bc */ 396 u32 usb1_vbus_det_stat; /* 0x1c0 */ 397 u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 398 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 399 u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 400 u32 usb1_chrg_det_stat; /* 0x1d0 */ 401 u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 402 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 403 u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 404 u32 usb1_loopback; /* 0x1e0 */ 405 u32 usb1_loopback_set; /* 0x1e4 */ 406 u32 usb1_loopback_clr; /* 0x1e8 */ 407 u32 usb1_loopback_tog; /* 0x1ec */ 408 u32 usb1_misc; /* 0x1f0 */ 409 u32 usb1_misc_set; /* 0x1f4 */ 410 u32 usb1_misc_clr; /* 0x1f8 */ 411 u32 usb1_misc_tog; /* 0x1fc */ 412 u32 usb2_vbus_detect; /* 0x200 */ 413 u32 usb2_vbus_detect_set; /* 0x204 */ 414 u32 usb2_vbus_detect_clr; /* 0x208 */ 415 u32 usb2_vbus_detect_tog; /* 0x20c */ 416 u32 usb2_chrg_detect; /* 0x210 */ 417 u32 usb2_chrg_detect_set; /* 0x214 */ 418 u32 usb2_chrg_detect_clr; /* 0x218 */ 419 u32 usb2_chrg_detect_tog; /* 0x21c */ 420 u32 usb2_vbus_det_stat; /* 0x220 */ 421 u32 usb2_vbus_det_stat_set; /* 0x224 */ 422 u32 usb2_vbus_det_stat_clr; /* 0x228 */ 423 u32 usb2_vbus_det_stat_tog; /* 0x22c */ 424 u32 usb2_chrg_det_stat; /* 0x230 */ 425 u32 usb2_chrg_det_stat_set; /* 0x234 */ 426 u32 usb2_chrg_det_stat_clr; /* 0x238 */ 427 u32 usb2_chrg_det_stat_tog; /* 0x23c */ 428 u32 usb2_loopback; /* 0x240 */ 429 u32 usb2_loopback_set; /* 0x244 */ 430 u32 usb2_loopback_clr; /* 0x248 */ 431 u32 usb2_loopback_tog; /* 0x24c */ 432 u32 usb2_misc; /* 0x250 */ 433 u32 usb2_misc_set; /* 0x254 */ 434 u32 usb2_misc_clr; /* 0x258 */ 435 u32 usb2_misc_tog; /* 0x25c */ 436 u32 digprog; /* 0x260 */ 437 }; 438 439 #endif /* __ASSEMBLER__*/ 440 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 441