1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 8 #define __ASM_ARCH_MX6_IMX_REGS_H__ 9 10 #define ARCH_MXC 11 12 #define CONFIG_SYS_CACHELINE_SIZE 32 13 14 #define ROMCP_ARB_BASE_ADDR 0x00000000 15 #define ROMCP_ARB_END_ADDR 0x000FFFFF 16 17 #ifdef CONFIG_MX6SL 18 #define GPU_2D_ARB_BASE_ADDR 0x02200000 19 #define GPU_2D_ARB_END_ADDR 0x02203FFF 20 #define OPENVG_ARB_BASE_ADDR 0x02204000 21 #define OPENVG_ARB_END_ADDR 0x02207FFF 22 #elif CONFIG_MX6SX 23 #define CAAM_ARB_BASE_ADDR 0x00100000 24 #define CAAM_ARB_END_ADDR 0x00107FFF 25 #define GPU_ARB_BASE_ADDR 0x01800000 26 #define GPU_ARB_END_ADDR 0x01803FFF 27 #define APBH_DMA_ARB_BASE_ADDR 0x01804000 28 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF 29 #define M4_BOOTROM_BASE_ADDR 0x007F8000 30 31 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 32 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 33 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 34 35 #else 36 #define CAAM_ARB_BASE_ADDR 0x00100000 37 #define CAAM_ARB_END_ADDR 0x00103FFF 38 #define APBH_DMA_ARB_BASE_ADDR 0x00110000 39 #define APBH_DMA_ARB_END_ADDR 0x00117FFF 40 #define HDMI_ARB_BASE_ADDR 0x00120000 41 #define HDMI_ARB_END_ADDR 0x00128FFF 42 #define GPU_3D_ARB_BASE_ADDR 0x00130000 43 #define GPU_3D_ARB_END_ADDR 0x00133FFF 44 #define GPU_2D_ARB_BASE_ADDR 0x00134000 45 #define GPU_2D_ARB_END_ADDR 0x00137FFF 46 #define DTCP_ARB_BASE_ADDR 0x00138000 47 #define DTCP_ARB_END_ADDR 0x0013BFFF 48 #endif /* CONFIG_MX6SL */ 49 50 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 51 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 52 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 53 54 /* GPV - PL301 configuration ports */ 55 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) 56 #define GPV2_BASE_ADDR 0x00D00000 57 #else 58 #define GPV2_BASE_ADDR 0x00200000 59 #endif 60 61 #ifdef CONFIG_MX6SX 62 #define GPV3_BASE_ADDR 0x00E00000 63 #define GPV4_BASE_ADDR 0x00F00000 64 #define GPV5_BASE_ADDR 0x01000000 65 #define GPV6_BASE_ADDR 0x01100000 66 #define PCIE_ARB_BASE_ADDR 0x08000000 67 #define PCIE_ARB_END_ADDR 0x08FFFFFF 68 69 #else 70 #define GPV3_BASE_ADDR 0x00300000 71 #define GPV4_BASE_ADDR 0x00800000 72 #define PCIE_ARB_BASE_ADDR 0x01000000 73 #define PCIE_ARB_END_ADDR 0x01FFFFFF 74 #endif 75 76 #define IRAM_BASE_ADDR 0x00900000 77 #define SCU_BASE_ADDR 0x00A00000 78 #define IC_INTERFACES_BASE_ADDR 0x00A00100 79 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 80 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 81 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 82 #define L2_PL310_BASE 0x00A02000 83 #define GPV0_BASE_ADDR 0x00B00000 84 #define GPV1_BASE_ADDR 0x00C00000 85 86 #define AIPS1_ARB_BASE_ADDR 0x02000000 87 #define AIPS1_ARB_END_ADDR 0x020FFFFF 88 #define AIPS2_ARB_BASE_ADDR 0x02100000 89 #define AIPS2_ARB_END_ADDR 0x021FFFFF 90 #ifdef CONFIG_MX6SX 91 #define AIPS3_BASE_ADDR 0x02200000 92 #define AIPS3_END_ADDR 0x022FFFFF 93 #define WEIM_ARB_BASE_ADDR 0x50000000 94 #define WEIM_ARB_END_ADDR 0x57FFFFFF 95 #define QSPI1_ARB_BASE_ADDR 0x60000000 96 #define QSPI1_ARB_END_ADDR 0x6FFFFFFF 97 #define QSPI2_ARB_BASE_ADDR 0x70000000 98 #define QSPI2_ARB_END_ADDR 0x7FFFFFFF 99 #else 100 #define SATA_ARB_BASE_ADDR 0x02200000 101 #define SATA_ARB_END_ADDR 0x02203FFF 102 #define OPENVG_ARB_BASE_ADDR 0x02204000 103 #define OPENVG_ARB_END_ADDR 0x02207FFF 104 #define HSI_ARB_BASE_ADDR 0x02208000 105 #define HSI_ARB_END_ADDR 0x0220BFFF 106 #define IPU1_ARB_BASE_ADDR 0x02400000 107 #define IPU1_ARB_END_ADDR 0x027FFFFF 108 #define IPU2_ARB_BASE_ADDR 0x02800000 109 #define IPU2_ARB_END_ADDR 0x02BFFFFF 110 #define WEIM_ARB_BASE_ADDR 0x08000000 111 #define WEIM_ARB_END_ADDR 0x0FFFFFFF 112 #endif 113 114 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) 115 #define MMDC0_ARB_BASE_ADDR 0x80000000 116 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF 117 #define MMDC1_ARB_BASE_ADDR 0xC0000000 118 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 119 #else 120 #define MMDC0_ARB_BASE_ADDR 0x10000000 121 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF 122 #define MMDC1_ARB_BASE_ADDR 0x80000000 123 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 124 #endif 125 126 #ifndef CONFIG_MX6SX 127 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR 128 #define IPU_SOC_OFFSET 0x00200000 129 #endif 130 131 /* Defines for Blocks connected via AIPS (SkyBlue) */ 132 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 133 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 134 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 135 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 136 137 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 138 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 139 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 140 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 141 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 142 #ifdef CONFIG_MX6SL 143 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 144 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) 145 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 146 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 147 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 148 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 149 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 150 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) 151 #else 152 #ifndef CONFIG_MX6SX 153 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 154 #endif 155 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 156 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 157 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 158 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 159 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 160 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 161 #endif 162 163 #ifndef CONFIG_MX6SX 164 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 165 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 166 #endif 167 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 168 169 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 170 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 171 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 172 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 173 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 174 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 175 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 176 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 177 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 178 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 179 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 180 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 181 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 182 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 183 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 184 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 185 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 186 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 187 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 188 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 189 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 190 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 191 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 192 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 193 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 194 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 195 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 196 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 197 #ifdef CONFIG_MX6SL 198 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 199 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 200 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 201 #elif CONFIG_MX6SX 202 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 203 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 204 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) 205 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 206 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 207 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) 208 #else 209 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 210 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 211 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 212 #endif 213 214 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 215 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 216 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 217 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 218 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 219 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 220 221 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 222 #ifdef CONFIG_MX6SL 223 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 224 #else 225 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 226 #endif 227 228 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 229 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 230 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 231 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 232 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 233 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 234 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 235 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 236 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 237 #ifdef CONFIG_MX6SL 238 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 239 #elif CONFIG_MX6SX 240 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 241 #else 242 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 243 #endif 244 245 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 246 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 247 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 248 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 249 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 250 #ifdef CONFIG_MX6SX 251 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 252 #else 253 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 254 #endif 255 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 256 #ifdef CONFIG_MX6SX 257 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 258 #else 259 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 260 #endif 261 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 262 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 263 #ifdef CONFIG_MX6SX 264 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 265 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 266 #define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 267 #else 268 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 269 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 270 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 271 #endif 272 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 273 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 274 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 275 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 276 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 277 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 278 279 #ifdef CONFIG_MX6SX 280 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) 281 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) 282 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) 283 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) 284 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) 285 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) 286 #define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) 287 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) 288 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) 289 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) 290 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) 291 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) 292 #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) 293 #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) 294 #define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) 295 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) 296 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) 297 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) 298 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) 299 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) 300 #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) 301 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) 302 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) 303 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) 304 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) 305 #endif 306 307 #define CHIP_REV_1_0 0x10 308 #define CHIP_REV_1_2 0x12 309 #define CHIP_REV_1_5 0x15 310 #ifndef CONFIG_MX6SX 311 #define IRAM_SIZE 0x00040000 312 #else 313 #define IRAM_SIZE 0x00020000 314 #endif 315 #define FEC_QUIRK_ENET_MAC 316 317 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 318 #include <asm/types.h> 319 320 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 321 322 #define SRC_SCR_CORE_1_RESET_OFFSET 14 323 #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET) 324 #define SRC_SCR_CORE_2_RESET_OFFSET 15 325 #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET) 326 #define SRC_SCR_CORE_3_RESET_OFFSET 16 327 #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET) 328 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22 329 #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET) 330 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23 331 #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET) 332 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24 333 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) 334 335 /* System Reset Controller (SRC) */ 336 struct src { 337 u32 scr; 338 u32 sbmr1; 339 u32 srsr; 340 u32 reserved1[2]; 341 u32 sisr; 342 u32 simr; 343 u32 sbmr2; 344 u32 gpr1; 345 u32 gpr2; 346 u32 gpr3; 347 u32 gpr4; 348 u32 gpr5; 349 u32 gpr6; 350 u32 gpr7; 351 u32 gpr8; 352 u32 gpr9; 353 u32 gpr10; 354 }; 355 356 /* GPR1 bitfields */ 357 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 358 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) 359 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 360 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) 361 362 /* GPR3 bitfields */ 363 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 364 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) 365 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 366 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) 367 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 368 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) 369 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 370 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) 371 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 372 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) 373 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 374 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) 375 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 376 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) 377 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 378 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) 379 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 380 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) 381 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 382 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) 383 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 384 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) 385 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 386 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) 387 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 388 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) 389 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 390 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) 391 392 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 393 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 394 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 395 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 396 397 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 398 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) 399 400 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 401 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) 402 403 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 404 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) 405 406 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 407 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) 408 409 410 struct iomuxc { 411 #ifdef CONFIG_MX6SX 412 u8 reserved[0x4000]; 413 #endif 414 u32 gpr[14]; 415 }; 416 417 struct gpc { 418 u32 cntr; 419 u32 pgr; 420 u32 imr1; 421 u32 imr2; 422 u32 imr3; 423 u32 imr4; 424 u32 isr1; 425 u32 isr2; 426 u32 isr3; 427 u32 isr4; 428 }; 429 430 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 431 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) 432 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 433 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) 434 435 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 436 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 437 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 438 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 439 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 440 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 441 442 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 443 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 444 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 445 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 446 447 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 448 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 449 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 450 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 451 452 #define IOMUXC_GPR2_BITMAP_SPWG 0 453 #define IOMUXC_GPR2_BITMAP_JEIDA 1 454 455 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 456 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 457 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 458 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 459 460 #define IOMUXC_GPR2_DATA_WIDTH_18 0 461 #define IOMUXC_GPR2_DATA_WIDTH_24 1 462 463 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 464 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 465 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 466 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 467 468 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 469 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 470 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 471 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 472 473 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 474 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 475 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 476 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 477 478 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 479 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) 480 481 #define IOMUXC_GPR2_MODE_DISABLED 0 482 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 483 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3 484 485 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 486 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 487 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 488 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 489 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 490 491 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 492 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 493 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 494 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 495 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 496 497 /* ECSPI registers */ 498 struct cspi_regs { 499 u32 rxdata; 500 u32 txdata; 501 u32 ctrl; 502 u32 cfg; 503 u32 intr; 504 u32 dma; 505 u32 stat; 506 u32 period; 507 }; 508 509 /* 510 * CSPI register definitions 511 */ 512 #define MXC_ECSPI 513 #define MXC_CSPICTRL_EN (1 << 0) 514 #define MXC_CSPICTRL_MODE (1 << 1) 515 #define MXC_CSPICTRL_XCH (1 << 2) 516 #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 517 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 518 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 519 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 520 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 521 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 522 #define MXC_CSPICTRL_MAXBITS 0xfff 523 #define MXC_CSPICTRL_TC (1 << 7) 524 #define MXC_CSPICTRL_RXOVF (1 << 6) 525 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 526 #define MAX_SPI_BYTES 32 527 #define SPI_MAX_NUM 4 528 529 /* Bit position inside CTRL register to be associated with SS */ 530 #define MXC_CSPICTRL_CHAN 18 531 532 /* Bit position inside CON register to be associated with SS */ 533 #define MXC_CSPICON_PHA 0 /* SCLK phase control */ 534 #define MXC_CSPICON_POL 4 /* SCLK polarity */ 535 #define MXC_CSPICON_SSPOL 12 /* SS polarity */ 536 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 537 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) 538 #define MXC_SPI_BASE_ADDRESSES \ 539 ECSPI1_BASE_ADDR, \ 540 ECSPI2_BASE_ADDR, \ 541 ECSPI3_BASE_ADDR, \ 542 ECSPI4_BASE_ADDR 543 #else 544 #define MXC_SPI_BASE_ADDRESSES \ 545 ECSPI1_BASE_ADDR, \ 546 ECSPI2_BASE_ADDR, \ 547 ECSPI3_BASE_ADDR, \ 548 ECSPI4_BASE_ADDR, \ 549 ECSPI5_BASE_ADDR 550 #endif 551 552 struct ocotp_regs { 553 u32 ctrl; 554 u32 ctrl_set; 555 u32 ctrl_clr; 556 u32 ctrl_tog; 557 u32 timing; 558 u32 rsvd0[3]; 559 u32 data; 560 u32 rsvd1[3]; 561 u32 read_ctrl; 562 u32 rsvd2[3]; 563 u32 read_fuse_data; 564 u32 rsvd3[3]; 565 u32 sw_sticky; 566 u32 rsvd4[3]; 567 u32 scs; 568 u32 scs_set; 569 u32 scs_clr; 570 u32 scs_tog; 571 u32 crc_addr; 572 u32 rsvd5[3]; 573 u32 crc_value; 574 u32 rsvd6[3]; 575 u32 version; 576 u32 rsvd7[0xdb]; 577 578 struct fuse_bank { 579 u32 fuse_regs[0x20]; 580 } bank[16]; 581 }; 582 583 struct fuse_bank0_regs { 584 u32 lock; 585 u32 rsvd0[3]; 586 u32 uid_low; 587 u32 rsvd1[3]; 588 u32 uid_high; 589 u32 rsvd2[3]; 590 u32 rsvd3[4]; 591 u32 rsvd4[4]; 592 u32 rsvd5[4]; 593 u32 cfg5; 594 u32 rsvd6[3]; 595 u32 rsvd7[4]; 596 }; 597 598 #ifdef CONFIG_MX6SX 599 struct fuse_bank4_regs { 600 u32 sjc_resp_low; 601 u32 rsvd0[3]; 602 u32 sjc_resp_high; 603 u32 rsvd1[3]; 604 u32 mac_addr_low; 605 u32 rsvd2[3]; 606 u32 mac_addr_high; 607 u32 rsvd3[3]; 608 u32 mac_addr2; 609 u32 rsvd4[7]; 610 u32 gp1; 611 u32 rsvd5[7]; 612 }; 613 #else 614 struct fuse_bank4_regs { 615 u32 sjc_resp_low; 616 u32 rsvd0[3]; 617 u32 sjc_resp_high; 618 u32 rsvd1[3]; 619 u32 mac_addr_low; 620 u32 rsvd2[3]; 621 u32 mac_addr_high; 622 u32 rsvd3[0xb]; 623 u32 gp1; 624 u32 rsvd4[3]; 625 u32 gp2; 626 u32 rsvd5[3]; 627 }; 628 #endif 629 630 struct aipstz_regs { 631 u32 mprot0; 632 u32 mprot1; 633 u32 rsvd[0xe]; 634 u32 opacr0; 635 u32 opacr1; 636 u32 opacr2; 637 u32 opacr3; 638 u32 opacr4; 639 }; 640 641 struct anatop_regs { 642 u32 pll_sys; /* 0x000 */ 643 u32 pll_sys_set; /* 0x004 */ 644 u32 pll_sys_clr; /* 0x008 */ 645 u32 pll_sys_tog; /* 0x00c */ 646 u32 usb1_pll_480_ctrl; /* 0x010 */ 647 u32 usb1_pll_480_ctrl_set; /* 0x014 */ 648 u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 649 u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 650 u32 usb2_pll_480_ctrl; /* 0x020 */ 651 u32 usb2_pll_480_ctrl_set; /* 0x024 */ 652 u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 653 u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 654 u32 pll_528; /* 0x030 */ 655 u32 pll_528_set; /* 0x034 */ 656 u32 pll_528_clr; /* 0x038 */ 657 u32 pll_528_tog; /* 0x03c */ 658 u32 pll_528_ss; /* 0x040 */ 659 u32 rsvd0[3]; 660 u32 pll_528_num; /* 0x050 */ 661 u32 rsvd1[3]; 662 u32 pll_528_denom; /* 0x060 */ 663 u32 rsvd2[3]; 664 u32 pll_audio; /* 0x070 */ 665 u32 pll_audio_set; /* 0x074 */ 666 u32 pll_audio_clr; /* 0x078 */ 667 u32 pll_audio_tog; /* 0x07c */ 668 u32 pll_audio_num; /* 0x080 */ 669 u32 rsvd3[3]; 670 u32 pll_audio_denom; /* 0x090 */ 671 u32 rsvd4[3]; 672 u32 pll_video; /* 0x0a0 */ 673 u32 pll_video_set; /* 0x0a4 */ 674 u32 pll_video_clr; /* 0x0a8 */ 675 u32 pll_video_tog; /* 0x0ac */ 676 u32 pll_video_num; /* 0x0b0 */ 677 u32 rsvd5[3]; 678 u32 pll_video_denom; /* 0x0c0 */ 679 u32 rsvd6[3]; 680 u32 pll_mlb; /* 0x0d0 */ 681 u32 pll_mlb_set; /* 0x0d4 */ 682 u32 pll_mlb_clr; /* 0x0d8 */ 683 u32 pll_mlb_tog; /* 0x0dc */ 684 u32 pll_enet; /* 0x0e0 */ 685 u32 pll_enet_set; /* 0x0e4 */ 686 u32 pll_enet_clr; /* 0x0e8 */ 687 u32 pll_enet_tog; /* 0x0ec */ 688 u32 pfd_480; /* 0x0f0 */ 689 u32 pfd_480_set; /* 0x0f4 */ 690 u32 pfd_480_clr; /* 0x0f8 */ 691 u32 pfd_480_tog; /* 0x0fc */ 692 u32 pfd_528; /* 0x100 */ 693 u32 pfd_528_set; /* 0x104 */ 694 u32 pfd_528_clr; /* 0x108 */ 695 u32 pfd_528_tog; /* 0x10c */ 696 u32 reg_1p1; /* 0x110 */ 697 u32 reg_1p1_set; /* 0x114 */ 698 u32 reg_1p1_clr; /* 0x118 */ 699 u32 reg_1p1_tog; /* 0x11c */ 700 u32 reg_3p0; /* 0x120 */ 701 u32 reg_3p0_set; /* 0x124 */ 702 u32 reg_3p0_clr; /* 0x128 */ 703 u32 reg_3p0_tog; /* 0x12c */ 704 u32 reg_2p5; /* 0x130 */ 705 u32 reg_2p5_set; /* 0x134 */ 706 u32 reg_2p5_clr; /* 0x138 */ 707 u32 reg_2p5_tog; /* 0x13c */ 708 u32 reg_core; /* 0x140 */ 709 u32 reg_core_set; /* 0x144 */ 710 u32 reg_core_clr; /* 0x148 */ 711 u32 reg_core_tog; /* 0x14c */ 712 u32 ana_misc0; /* 0x150 */ 713 u32 ana_misc0_set; /* 0x154 */ 714 u32 ana_misc0_clr; /* 0x158 */ 715 u32 ana_misc0_tog; /* 0x15c */ 716 u32 ana_misc1; /* 0x160 */ 717 u32 ana_misc1_set; /* 0x164 */ 718 u32 ana_misc1_clr; /* 0x168 */ 719 u32 ana_misc1_tog; /* 0x16c */ 720 u32 ana_misc2; /* 0x170 */ 721 u32 ana_misc2_set; /* 0x174 */ 722 u32 ana_misc2_clr; /* 0x178 */ 723 u32 ana_misc2_tog; /* 0x17c */ 724 u32 tempsense0; /* 0x180 */ 725 u32 tempsense0_set; /* 0x184 */ 726 u32 tempsense0_clr; /* 0x188 */ 727 u32 tempsense0_tog; /* 0x18c */ 728 u32 tempsense1; /* 0x190 */ 729 u32 tempsense1_set; /* 0x194 */ 730 u32 tempsense1_clr; /* 0x198 */ 731 u32 tempsense1_tog; /* 0x19c */ 732 u32 usb1_vbus_detect; /* 0x1a0 */ 733 u32 usb1_vbus_detect_set; /* 0x1a4 */ 734 u32 usb1_vbus_detect_clr; /* 0x1a8 */ 735 u32 usb1_vbus_detect_tog; /* 0x1ac */ 736 u32 usb1_chrg_detect; /* 0x1b0 */ 737 u32 usb1_chrg_detect_set; /* 0x1b4 */ 738 u32 usb1_chrg_detect_clr; /* 0x1b8 */ 739 u32 usb1_chrg_detect_tog; /* 0x1bc */ 740 u32 usb1_vbus_det_stat; /* 0x1c0 */ 741 u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 742 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 743 u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 744 u32 usb1_chrg_det_stat; /* 0x1d0 */ 745 u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 746 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 747 u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 748 u32 usb1_loopback; /* 0x1e0 */ 749 u32 usb1_loopback_set; /* 0x1e4 */ 750 u32 usb1_loopback_clr; /* 0x1e8 */ 751 u32 usb1_loopback_tog; /* 0x1ec */ 752 u32 usb1_misc; /* 0x1f0 */ 753 u32 usb1_misc_set; /* 0x1f4 */ 754 u32 usb1_misc_clr; /* 0x1f8 */ 755 u32 usb1_misc_tog; /* 0x1fc */ 756 u32 usb2_vbus_detect; /* 0x200 */ 757 u32 usb2_vbus_detect_set; /* 0x204 */ 758 u32 usb2_vbus_detect_clr; /* 0x208 */ 759 u32 usb2_vbus_detect_tog; /* 0x20c */ 760 u32 usb2_chrg_detect; /* 0x210 */ 761 u32 usb2_chrg_detect_set; /* 0x214 */ 762 u32 usb2_chrg_detect_clr; /* 0x218 */ 763 u32 usb2_chrg_detect_tog; /* 0x21c */ 764 u32 usb2_vbus_det_stat; /* 0x220 */ 765 u32 usb2_vbus_det_stat_set; /* 0x224 */ 766 u32 usb2_vbus_det_stat_clr; /* 0x228 */ 767 u32 usb2_vbus_det_stat_tog; /* 0x22c */ 768 u32 usb2_chrg_det_stat; /* 0x230 */ 769 u32 usb2_chrg_det_stat_set; /* 0x234 */ 770 u32 usb2_chrg_det_stat_clr; /* 0x238 */ 771 u32 usb2_chrg_det_stat_tog; /* 0x23c */ 772 u32 usb2_loopback; /* 0x240 */ 773 u32 usb2_loopback_set; /* 0x244 */ 774 u32 usb2_loopback_clr; /* 0x248 */ 775 u32 usb2_loopback_tog; /* 0x24c */ 776 u32 usb2_misc; /* 0x250 */ 777 u32 usb2_misc_set; /* 0x254 */ 778 u32 usb2_misc_clr; /* 0x258 */ 779 u32 usb2_misc_tog; /* 0x25c */ 780 u32 digprog; /* 0x260 */ 781 u32 reserved1[7]; 782 u32 digprog_sololite; /* 0x280 */ 783 }; 784 785 #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) 786 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) 787 #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) 788 #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) 789 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) 790 #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) 791 792 struct wdog_regs { 793 u16 wcr; /* Control */ 794 u16 wsr; /* Service */ 795 u16 wrsr; /* Reset Status */ 796 u16 wicr; /* Interrupt Control */ 797 u16 wmcr; /* Miscellaneous Control */ 798 }; 799 800 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) 801 #define PWMCR_DOZEEN (1 << 24) 802 #define PWMCR_WAITEN (1 << 23) 803 #define PWMCR_DBGEN (1 << 22) 804 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) 805 #define PWMCR_CLKSRC_IPG (1 << 16) 806 #define PWMCR_EN (1 << 0) 807 808 struct pwm_regs { 809 u32 cr; 810 u32 sr; 811 u32 ir; 812 u32 sar; 813 u32 pr; 814 u32 cnr; 815 }; 816 #endif /* __ASSEMBLER__*/ 817 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 818