1 /*
2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
9 
10 #define ARCH_MXC
11 
12 #define ROMCP_ARB_BASE_ADDR             0x00000000
13 #define ROMCP_ARB_END_ADDR              0x000FFFFF
14 
15 #ifdef CONFIG_MX6SL
16 #define GPU_2D_ARB_BASE_ADDR            0x02200000
17 #define GPU_2D_ARB_END_ADDR             0x02203FFF
18 #define OPENVG_ARB_BASE_ADDR            0x02204000
19 #define OPENVG_ARB_END_ADDR             0x02207FFF
20 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
21 #define CAAM_ARB_BASE_ADDR              0x00100000
22 #define CAAM_ARB_END_ADDR               0x00107FFF
23 #define GPU_ARB_BASE_ADDR               0x01800000
24 #define GPU_ARB_END_ADDR                0x01803FFF
25 #define APBH_DMA_ARB_BASE_ADDR          0x01804000
26 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
27 #define M4_BOOTROM_BASE_ADDR			0x007F8000
28 
29 #else
30 #define CAAM_ARB_BASE_ADDR              0x00100000
31 #define CAAM_ARB_END_ADDR               0x00103FFF
32 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
33 #define APBH_DMA_ARB_END_ADDR           0x00117FFF
34 #define HDMI_ARB_BASE_ADDR              0x00120000
35 #define HDMI_ARB_END_ADDR               0x00128FFF
36 #define GPU_3D_ARB_BASE_ADDR            0x00130000
37 #define GPU_3D_ARB_END_ADDR             0x00133FFF
38 #define GPU_2D_ARB_BASE_ADDR            0x00134000
39 #define GPU_2D_ARB_END_ADDR             0x00137FFF
40 #define DTCP_ARB_BASE_ADDR              0x00138000
41 #define DTCP_ARB_END_ADDR               0x0013BFFF
42 #endif	/* CONFIG_MX6SL */
43 
44 #define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
45 #define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
46 #define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
47 
48 /* GPV - PL301 configuration ports */
49 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
50 #define GPV2_BASE_ADDR                  0x00D00000
51 #else
52 #define GPV2_BASE_ADDR			0x00200000
53 #endif
54 
55 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
56 #define GPV3_BASE_ADDR			0x00E00000
57 #define GPV4_BASE_ADDR			0x00F00000
58 #define GPV5_BASE_ADDR			0x01000000
59 #define GPV6_BASE_ADDR			0x01100000
60 #define PCIE_ARB_BASE_ADDR              0x08000000
61 #define PCIE_ARB_END_ADDR               0x08FFFFFF
62 
63 #else
64 #define GPV3_BASE_ADDR			0x00300000
65 #define GPV4_BASE_ADDR			0x00800000
66 #define PCIE_ARB_BASE_ADDR              0x01000000
67 #define PCIE_ARB_END_ADDR               0x01FFFFFF
68 #endif
69 
70 #define IRAM_BASE_ADDR			0x00900000
71 #define SCU_BASE_ADDR                   0x00A00000
72 #define IC_INTERFACES_BASE_ADDR         0x00A00100
73 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
74 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
75 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
76 #define L2_PL310_BASE			0x00A02000
77 #define GPV0_BASE_ADDR                  0x00B00000
78 #define GPV1_BASE_ADDR                  0x00C00000
79 
80 #define AIPS1_ARB_BASE_ADDR             0x02000000
81 #define AIPS1_ARB_END_ADDR              0x020FFFFF
82 #define AIPS2_ARB_BASE_ADDR             0x02100000
83 #define AIPS2_ARB_END_ADDR              0x021FFFFF
84 /* AIPS3 only on i.MX6SX */
85 #define AIPS3_ARB_BASE_ADDR             0x02200000
86 #define AIPS3_ARB_END_ADDR              0x022FFFFF
87 #ifdef CONFIG_MX6SX
88 #define WEIM_ARB_BASE_ADDR              0x50000000
89 #define WEIM_ARB_END_ADDR               0x57FFFFFF
90 #define QSPI0_AMBA_BASE                0x60000000
91 #define QSPI0_AMBA_END                 0x6FFFFFFF
92 #define QSPI1_AMBA_BASE                0x70000000
93 #define QSPI1_AMBA_END                 0x7FFFFFFF
94 #elif defined(CONFIG_MX6UL)
95 #define WEIM_ARB_BASE_ADDR              0x50000000
96 #define WEIM_ARB_END_ADDR               0x57FFFFFF
97 #define QSPI0_AMBA_BASE                 0x60000000
98 #define QSPI0_AMBA_END                  0x6FFFFFFF
99 #else
100 #define SATA_ARB_BASE_ADDR              0x02200000
101 #define SATA_ARB_END_ADDR               0x02203FFF
102 #define OPENVG_ARB_BASE_ADDR            0x02204000
103 #define OPENVG_ARB_END_ADDR             0x02207FFF
104 #define HSI_ARB_BASE_ADDR               0x02208000
105 #define HSI_ARB_END_ADDR                0x0220BFFF
106 #define IPU1_ARB_BASE_ADDR              0x02400000
107 #define IPU1_ARB_END_ADDR               0x027FFFFF
108 #define IPU2_ARB_BASE_ADDR              0x02800000
109 #define IPU2_ARB_END_ADDR               0x02BFFFFF
110 #define WEIM_ARB_BASE_ADDR              0x08000000
111 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
112 #endif
113 
114 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
115 #define MMDC0_ARB_BASE_ADDR             0x80000000
116 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
117 #define MMDC1_ARB_BASE_ADDR             0xC0000000
118 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
119 #else
120 #define MMDC0_ARB_BASE_ADDR             0x10000000
121 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
122 #define MMDC1_ARB_BASE_ADDR             0x80000000
123 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
124 #endif
125 
126 #ifndef CONFIG_MX6SX
127 #define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
128 #define IPU_SOC_OFFSET			0x00200000
129 #endif
130 
131 /* Defines for Blocks connected via AIPS (SkyBlue) */
132 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
133 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
134 #define ATZ3_BASE_ADDR              AIPS3_ARB_BASE_ADDR
135 #define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
136 #define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
137 #define AIPS3_BASE_ADDR             AIPS3_ON_BASE_ADDR
138 
139 #define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
140 #define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
141 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
142 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
143 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
144 #ifdef CONFIG_MX6SL
145 #define UART5_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x18000)
146 #define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
147 #define UART2_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x24000)
148 #define SSI1_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x28000)
149 #define SSI2_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x2C000)
150 #define SSI3_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x30000)
151 #define UART3_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x34000)
152 #define UART4_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x38000)
153 #else
154 #ifndef CONFIG_MX6SX
155 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
156 #endif
157 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
158 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
159 #define UART8_BASE                  (ATZ1_BASE_ADDR + 0x24000)
160 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
161 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
162 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
163 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
164 #endif
165 
166 #ifndef CONFIG_MX6SX
167 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
168 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
169 #endif
170 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
171 
172 #define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
173 #define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
174 #define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
175 #define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
176 #define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
177 #define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
178 #define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
179 #define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
180 #define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
181 #define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
182 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
183 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
184 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
185 #define MX6UL_SNVS_LP_BASE_ADDR     (AIPS1_OFF_BASE_ADDR + 0x30000)
186 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
187 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
188 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
189 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
190 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
191 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
192 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
193 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
194 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
195 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
196 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
197 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
198 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
199 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
200 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
201 #ifdef CONFIG_MX6SL
202 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
203 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
204 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
205 #elif CONFIG_MX6SX
206 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
207 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
208 #define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)
209 #define SEMAPHORE1_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x74000)
210 #define SEMAPHORE2_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x78000)
211 #define RDC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
212 #else
213 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
214 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
215 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
216 #endif
217 
218 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
219 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
220 #define AIPS3_ON_BASE_ADDR          (ATZ3_BASE_ADDR + 0x7C000)
221 #define AIPS3_OFF_BASE_ADDR         (ATZ3_BASE_ADDR + 0x80000)
222 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
223 #define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
224 
225 #define CONFIG_SYS_FSL_SEC_OFFSET   0
226 #define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
227 				     CONFIG_SYS_FSL_SEC_OFFSET)
228 #define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
229 #define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
230 				     CONFIG_SYS_FSL_JR0_OFFSET)
231 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
232 
233 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
234 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
235 
236 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
237 #ifdef CONFIG_MX6SL
238 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
239 #else
240 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
241 #endif
242 
243 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
244 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
245 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
246 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
247 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
248 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
249 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
250 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
251 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
252 /* i.MX6SL */
253 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
254 #ifdef CONFIG_MX6UL
255 #define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
256 #else
257 /* i.MX6SX */
258 #define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
259 #endif
260 /* i.MX6DQ/SDL */
261 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
262 
263 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
264 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
265 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
266 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
267 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
268 #define MX6UL_LCDIF1_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x48000)
269 #define MX6ULL_LCDIF1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x48000)
270 #ifdef CONFIG_MX6SX
271 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
272 #else
273 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
274 #endif
275 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
276 #ifdef CONFIG_MX6UL
277 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
278 #define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
279 #elif defined(CONFIG_MX6SX)
280 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
281 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
282 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
283 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
284 #define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
285 #else
286 #define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
287 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
288 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
289 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
290 #endif
291 #define MX6UL_WDOG3_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x64000)
292 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
293 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
294 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
295 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
296 #define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
297 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
298 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
299 
300 #ifdef CONFIG_MX6SX
301 #define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
302 #define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
303 #define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)
304 #define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
305 #define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
306 #define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
307 #define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
308 #define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
309 #define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
310 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
311 #define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
312 #define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
313 #define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
314 #define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
315 #define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
316 #define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
317 #define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
318 #define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
319 #define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
320 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
321 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
322 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
323 #elif defined(CONFIG_MX6ULL)
324 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
325 #define DCP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x80000)
326 #define RNGB_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
327 #define UART8_IPS_BASE_ADDR         (AIPS3_ARB_BASE_ADDR + 0x88000)
328 #define EPDC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x8C000)
329 #define IOMUXC_SNVS_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x90000)
330 #define SNVS_GPR_BASE_ADDR          (AIPS3_ARB_BASE_ADDR + 0x94000)
331 #endif
332 /* Only for i.MX6SX */
333 #define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
334 #define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
335 #define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
336 
337 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
338 #define IRAM_SIZE                    0x00040000
339 #else
340 #define IRAM_SIZE                    0x00020000
341 #endif
342 #define FEC_QUIRK_ENET_MAC
343 
344 #include <asm/imx-common/regs-lcdif.h>
345 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
346 #include <asm/types.h>
347 
348 /* only for i.MX6SX/UL */
349 #define WDOG3_BASE_ADDR ((is_mx6ul() ?	\
350 			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR))
351 #define LCDIF1_BASE_ADDR ((is_mx6ul()) ?	\
352 			  MX6UL_LCDIF1_BASE_ADDR :		\
353 			  ((is_mx6ull()) ?	\
354 			  MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))
355 
356 
357 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
358 
359 #define SRC_SCR_CORE_1_RESET_OFFSET     14
360 #define SRC_SCR_CORE_1_RESET_MASK       (1<<SRC_SCR_CORE_1_RESET_OFFSET)
361 #define SRC_SCR_CORE_2_RESET_OFFSET     15
362 #define SRC_SCR_CORE_2_RESET_MASK       (1<<SRC_SCR_CORE_2_RESET_OFFSET)
363 #define SRC_SCR_CORE_3_RESET_OFFSET     16
364 #define SRC_SCR_CORE_3_RESET_MASK       (1<<SRC_SCR_CORE_3_RESET_OFFSET)
365 #define SRC_SCR_CORE_1_ENABLE_OFFSET    22
366 #define SRC_SCR_CORE_1_ENABLE_MASK      (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
367 #define SRC_SCR_CORE_2_ENABLE_OFFSET    23
368 #define SRC_SCR_CORE_2_ENABLE_MASK      (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
369 #define SRC_SCR_CORE_3_ENABLE_OFFSET    24
370 #define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
371 
372 struct rdc_regs {
373 	u32	vir;		/* Version information */
374 	u32	reserved1[8];
375 	u32	stat;		/* Status */
376 	u32	intctrl;	/* Interrupt and Control */
377 	u32	intstat;	/* Interrupt Status */
378 	u32	reserved2[116];
379 	u32	mda[32];	/* Master Domain Assignment */
380 	u32	reserved3[96];
381 	u32	pdap[104];	/* Peripheral Domain Access Permissions */
382 	u32	reserved4[88];
383 	struct {
384 		u32 mrsa;	/* Memory Region Start Address */
385 		u32 mrea;	/* Memory Region End Address */
386 		u32 mrc;	/* Memory Region Control */
387 		u32 mrvs;	/* Memory Region Violation Status */
388 	} mem_region[55];
389 };
390 
391 struct rdc_sema_regs {
392 	u8	gate[64];	/* Gate */
393 	u16	rstgt;		/* Reset Gate */
394 };
395 
396 /* WEIM registers */
397 struct weim {
398 	u32 cs0gcr1;
399 	u32 cs0gcr2;
400 	u32 cs0rcr1;
401 	u32 cs0rcr2;
402 	u32 cs0wcr1;
403 	u32 cs0wcr2;
404 
405 	u32 cs1gcr1;
406 	u32 cs1gcr2;
407 	u32 cs1rcr1;
408 	u32 cs1rcr2;
409 	u32 cs1wcr1;
410 	u32 cs1wcr2;
411 
412 	u32 cs2gcr1;
413 	u32 cs2gcr2;
414 	u32 cs2rcr1;
415 	u32 cs2rcr2;
416 	u32 cs2wcr1;
417 	u32 cs2wcr2;
418 
419 	u32 cs3gcr1;
420 	u32 cs3gcr2;
421 	u32 cs3rcr1;
422 	u32 cs3rcr2;
423 	u32 cs3wcr1;
424 	u32 cs3wcr2;
425 
426 	u32 unused[12];
427 
428 	u32 wcr;
429 	u32 wiar;
430 	u32 ear;
431 };
432 
433 /* System Reset Controller (SRC) */
434 struct src {
435 	u32	scr;
436 	u32	sbmr1;
437 	u32	srsr;
438 	u32	reserved1[2];
439 	u32	sisr;
440 	u32	simr;
441 	u32     sbmr2;
442 	u32     gpr1;
443 	u32     gpr2;
444 	u32     gpr3;
445 	u32     gpr4;
446 	u32     gpr5;
447 	u32     gpr6;
448 	u32     gpr7;
449 	u32     gpr8;
450 	u32     gpr9;
451 	u32     gpr10;
452 };
453 
454 #define SRC_SCR_M4_ENABLE_OFFSET                22
455 #define SRC_SCR_M4_ENABLE_MASK                  (1 << 22)
456 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET         4
457 #define SRC_SCR_M4C_NON_SCLR_RST_MASK           (1 << 4)
458 
459 /* GPR1 bitfields */
460 #define IOMUXC_GPR1_APP_CLK_REQ_N		BIT(30)
461 #define IOMUXC_GPR1_PCIE_EXIT_L1		BIT(28)
462 #define IOMUXC_GPR1_PCIE_RDY_L23		BIT(27)
463 #define IOMUXC_GPR1_PCIE_ENTER_L1		BIT(26)
464 #define IOMUXC_GPR1_MIPI_COLOR_SW		BIT(25)
465 #define IOMUXC_GPR1_DPI_OFF			BIT(24)
466 #define IOMUXC_GPR1_EXC_MON_SLVE		BIT(22)
467 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET		21
468 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK		(1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
469 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(20)
470 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(19)
471 #define IOMUXC_GPR1_PCIE_TEST_PD			BIT(18)
472 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2		BIT(17)
473 #define IOMUXC_GPR1_PCIE_REF_CLK_EN		BIT(16)
474 #define IOMUXC_GPR1_USB_EXP_MODE			BIT(15)
475 #define IOMUXC_GPR1_PCIE_INT			BIT(14)
476 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET		13
477 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK		(1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
478 #define IOMUXC_GPR1_GINT				BIT(12)
479 #define IOMUXC_GPR1_ADDRS3_MASK			(0x3 << 10)
480 #define IOMUXC_GPR1_ADDRS3_32MB			(0x0 << 10)
481 #define IOMUXC_GPR1_ADDRS3_64MB			(0x1 << 10)
482 #define IOMUXC_GPR1_ADDRS3_128MB			(0x2 << 10)
483 #define IOMUXC_GPR1_ACT_CS3			BIT(9)
484 #define IOMUXC_GPR1_ADDRS2_MASK			(0x3 << 7)
485 #define IOMUXC_GPR1_ACT_CS2			BIT(6)
486 #define IOMUXC_GPR1_ADDRS1_MASK			(0x3 << 4)
487 #define IOMUXC_GPR1_ACT_CS1			BIT(3)
488 #define IOMUXC_GPR1_ADDRS0_OFFSET		(1)
489 #define IOMUXC_GPR1_ADDRS0_MASK			(0x3 << 1)
490 #define IOMUXC_GPR1_ACT_CS0			BIT(0)
491 
492 /* GPR3 bitfields */
493 #define IOMUXC_GPR3_GPU_DBG_OFFSET		29
494 #define IOMUXC_GPR3_GPU_DBG_MASK		(3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
495 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET	28
496 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
497 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET	27
498 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
499 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET	26
500 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
501 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET	25
502 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
503 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET		21
504 #define IOMUXC_GPR3_OCRAM_CTL_MASK		(0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
505 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET		17
506 #define IOMUXC_GPR3_OCRAM_STATUS_MASK		(0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
507 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET	16
508 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
509 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET	15
510 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
511 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET	14
512 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
513 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET	13
514 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
515 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET	12
516 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
517 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET	11
518 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
519 #define IOMUXC_GPR3_IPU_DIAG_OFFSET		10
520 #define IOMUXC_GPR3_IPU_DIAG_MASK		(1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
521 
522 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0	0
523 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1	1
524 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0	2
525 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1	3
526 
527 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET	8
528 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
529 
530 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET	6
531 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
532 
533 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET		4
534 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
535 
536 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET		2
537 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
538 
539 /* gpr12 bitfields */
540 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN		BIT(27)
541 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN		BIT(26)
542 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN		BIT(25)
543 #define IOMUXC_GPR12_ARMP_APB_CLK_EN		BIT(24)
544 #define IOMUXC_GPR12_DEVICE_TYPE		(0xf << 12)
545 #define IOMUXC_GPR12_PCIE_CTL_2			BIT(10)
546 #define IOMUXC_GPR12_LOS_LEVEL			(0x1f << 4)
547 
548 struct iomuxc {
549 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
550 	u8 reserved[0x4000];
551 #endif
552 	u32 gpr[14];
553 };
554 
555 struct gpc {
556 	u32	cntr;
557 	u32	pgr;
558 	u32	imr1;
559 	u32	imr2;
560 	u32	imr3;
561 	u32	imr4;
562 	u32	isr1;
563 	u32	isr2;
564 	u32	isr3;
565 	u32	isr4;
566 };
567 
568 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
569 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
570 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16
571 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK			(7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
572 
573 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET			15
574 #define IOMUXC_GPR2_BGREF_RRMODE_MASK			(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
575 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES		(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
576 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES		(0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
577 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH	0
578 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW	1
579 
580 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET		10
581 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
582 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
583 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
584 
585 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET		9
586 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
587 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
588 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
589 
590 #define IOMUXC_GPR2_BITMAP_SPWG	0
591 #define IOMUXC_GPR2_BITMAP_JEIDA	1
592 
593 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET		8
594 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
595 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
596 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
597 
598 #define IOMUXC_GPR2_DATA_WIDTH_18	0
599 #define IOMUXC_GPR2_DATA_WIDTH_24	1
600 
601 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET		7
602 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
603 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
604 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
605 
606 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET		6
607 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
608 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
609 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
610 
611 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET		5
612 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
613 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
614 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
615 
616 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET		4
617 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK			(1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
618 
619 #define IOMUXC_GPR2_MODE_DISABLED	0
620 #define IOMUXC_GPR2_MODE_ENABLED_DI0	1
621 #define IOMUXC_GPR2_MODE_ENABLED_DI1	3
622 
623 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET		2
624 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
625 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
626 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
627 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
628 
629 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET		0
630 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
631 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
632 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
633 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
634 
635 /* ECSPI registers */
636 struct cspi_regs {
637 	u32 rxdata;
638 	u32 txdata;
639 	u32 ctrl;
640 	u32 cfg;
641 	u32 intr;
642 	u32 dma;
643 	u32 stat;
644 	u32 period;
645 };
646 
647 /*
648  * CSPI register definitions
649  */
650 #define MXC_ECSPI
651 #define MXC_CSPICTRL_EN		(1 << 0)
652 #define MXC_CSPICTRL_MODE	(1 << 1)
653 #define MXC_CSPICTRL_XCH	(1 << 2)
654 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
655 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
656 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
657 #define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
658 #define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
659 #define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
660 #define MXC_CSPICTRL_MAXBITS	0xfff
661 #define MXC_CSPICTRL_TC		(1 << 7)
662 #define MXC_CSPICTRL_RXOVF	(1 << 6)
663 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
664 #define MAX_SPI_BYTES	32
665 #define SPI_MAX_NUM	4
666 
667 /* Bit position inside CTRL register to be associated with SS */
668 #define MXC_CSPICTRL_CHAN	18
669 
670 /* Bit position inside CON register to be associated with SS */
671 #define MXC_CSPICON_PHA		0  /* SCLK phase control */
672 #define MXC_CSPICON_POL		4  /* SCLK polarity */
673 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
674 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
675 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
676 #define MXC_SPI_BASE_ADDRESSES \
677 	ECSPI1_BASE_ADDR, \
678 	ECSPI2_BASE_ADDR, \
679 	ECSPI3_BASE_ADDR, \
680 	ECSPI4_BASE_ADDR
681 #else
682 #define MXC_SPI_BASE_ADDRESSES \
683 	ECSPI1_BASE_ADDR, \
684 	ECSPI2_BASE_ADDR, \
685 	ECSPI3_BASE_ADDR, \
686 	ECSPI4_BASE_ADDR, \
687 	ECSPI5_BASE_ADDR
688 #endif
689 
690 struct ocotp_regs {
691 	u32	ctrl;
692 	u32	ctrl_set;
693 	u32     ctrl_clr;
694 	u32	ctrl_tog;
695 	u32	timing;
696 	u32     rsvd0[3];
697 	u32     data;
698 	u32     rsvd1[3];
699 	u32     read_ctrl;
700 	u32     rsvd2[3];
701 	u32	read_fuse_data;
702 	u32     rsvd3[3];
703 	u32	sw_sticky;
704 	u32     rsvd4[3];
705 	u32     scs;
706 	u32     scs_set;
707 	u32     scs_clr;
708 	u32     scs_tog;
709 	u32     crc_addr;
710 	u32     rsvd5[3];
711 	u32     crc_value;
712 	u32     rsvd6[3];
713 	u32     version;
714 	u32     rsvd7[0xdb];
715 
716 	/* fuse banks */
717 	struct fuse_bank {
718 		u32	fuse_regs[0x20];
719 	} bank[0];
720 };
721 
722 struct fuse_bank0_regs {
723 	u32	lock;
724 	u32	rsvd0[3];
725 	u32	uid_low;
726 	u32	rsvd1[3];
727 	u32	uid_high;
728 	u32	rsvd2[3];
729 	u32	cfg2;
730 	u32	rsvd3[3];
731 	u32	cfg3;
732 	u32	rsvd4[3];
733 	u32	cfg4;
734 	u32	rsvd5[3];
735 	u32	cfg5;
736 	u32	rsvd6[3];
737 	u32	cfg6;
738 	u32	rsvd7[3];
739 };
740 
741 struct fuse_bank1_regs {
742 	u32	mem0;
743 	u32	rsvd0[3];
744 	u32	mem1;
745 	u32	rsvd1[3];
746 	u32	mem2;
747 	u32	rsvd2[3];
748 	u32	mem3;
749 	u32	rsvd3[3];
750 	u32	mem4;
751 	u32	rsvd4[3];
752 	u32	ana0;
753 	u32	rsvd5[3];
754 	u32	ana1;
755 	u32	rsvd6[3];
756 	u32	ana2;
757 	u32	rsvd7[3];
758 };
759 
760 struct fuse_bank4_regs {
761 	u32 sjc_resp_low;
762 	u32 rsvd0[3];
763 	u32 sjc_resp_high;
764 	u32 rsvd1[3];
765 	u32 mac_addr0;
766 	u32 rsvd2[3];
767 	u32 mac_addr1;
768 	u32 rsvd3[3];
769 	u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
770 	u32 rsvd4[7];
771 	u32 gp1;
772 	u32 rsvd5[3];
773 	u32 gp2;
774 	u32 rsvd6[3];
775 };
776 
777 struct aipstz_regs {
778 	u32	mprot0;
779 	u32	mprot1;
780 	u32	rsvd[0xe];
781 	u32	opacr0;
782 	u32	opacr1;
783 	u32	opacr2;
784 	u32	opacr3;
785 	u32	opacr4;
786 };
787 
788 struct anatop_regs {
789 	u32	pll_sys;		/* 0x000 */
790 	u32	pll_sys_set;		/* 0x004 */
791 	u32	pll_sys_clr;		/* 0x008 */
792 	u32	pll_sys_tog;		/* 0x00c */
793 	u32	usb1_pll_480_ctrl;	/* 0x010 */
794 	u32	usb1_pll_480_ctrl_set;	/* 0x014 */
795 	u32	usb1_pll_480_ctrl_clr;	/* 0x018 */
796 	u32	usb1_pll_480_ctrl_tog;	/* 0x01c */
797 	u32	usb2_pll_480_ctrl;	/* 0x020 */
798 	u32	usb2_pll_480_ctrl_set;	/* 0x024 */
799 	u32	usb2_pll_480_ctrl_clr;	/* 0x028 */
800 	u32	usb2_pll_480_ctrl_tog;	/* 0x02c */
801 	u32	pll_528;		/* 0x030 */
802 	u32	pll_528_set;		/* 0x034 */
803 	u32	pll_528_clr;		/* 0x038 */
804 	u32	pll_528_tog;		/* 0x03c */
805 	u32	pll_528_ss;		/* 0x040 */
806 	u32	rsvd0[3];
807 	u32	pll_528_num;		/* 0x050 */
808 	u32	rsvd1[3];
809 	u32	pll_528_denom;		/* 0x060 */
810 	u32	rsvd2[3];
811 	u32	pll_audio;		/* 0x070 */
812 	u32	pll_audio_set;		/* 0x074 */
813 	u32	pll_audio_clr;		/* 0x078 */
814 	u32	pll_audio_tog;		/* 0x07c */
815 	u32	pll_audio_num;		/* 0x080 */
816 	u32	rsvd3[3];
817 	u32	pll_audio_denom;	/* 0x090 */
818 	u32	rsvd4[3];
819 	u32	pll_video;		/* 0x0a0 */
820 	u32	pll_video_set;		/* 0x0a4 */
821 	u32	pll_video_clr;		/* 0x0a8 */
822 	u32	pll_video_tog;		/* 0x0ac */
823 	u32	pll_video_num;		/* 0x0b0 */
824 	u32	rsvd5[3];
825 	u32	pll_video_denom;	/* 0x0c0 */
826 	u32	rsvd6[3];
827 	u32	pll_mlb;		/* 0x0d0 */
828 	u32	pll_mlb_set;		/* 0x0d4 */
829 	u32	pll_mlb_clr;		/* 0x0d8 */
830 	u32	pll_mlb_tog;		/* 0x0dc */
831 	u32	pll_enet;		/* 0x0e0 */
832 	u32	pll_enet_set;		/* 0x0e4 */
833 	u32	pll_enet_clr;		/* 0x0e8 */
834 	u32	pll_enet_tog;		/* 0x0ec */
835 	u32	pfd_480;		/* 0x0f0 */
836 	u32	pfd_480_set;		/* 0x0f4 */
837 	u32	pfd_480_clr;		/* 0x0f8 */
838 	u32	pfd_480_tog;		/* 0x0fc */
839 	u32	pfd_528;		/* 0x100 */
840 	u32	pfd_528_set;		/* 0x104 */
841 	u32	pfd_528_clr;		/* 0x108 */
842 	u32	pfd_528_tog;		/* 0x10c */
843 	u32	reg_1p1;		/* 0x110 */
844 	u32	reg_1p1_set;		/* 0x114 */
845 	u32	reg_1p1_clr;		/* 0x118 */
846 	u32	reg_1p1_tog;		/* 0x11c */
847 	u32	reg_3p0;		/* 0x120 */
848 	u32	reg_3p0_set;		/* 0x124 */
849 	u32	reg_3p0_clr;		/* 0x128 */
850 	u32	reg_3p0_tog;		/* 0x12c */
851 	u32	reg_2p5;		/* 0x130 */
852 	u32	reg_2p5_set;		/* 0x134 */
853 	u32	reg_2p5_clr;		/* 0x138 */
854 	u32	reg_2p5_tog;		/* 0x13c */
855 	u32	reg_core;		/* 0x140 */
856 	u32	reg_core_set;		/* 0x144 */
857 	u32	reg_core_clr;		/* 0x148 */
858 	u32	reg_core_tog;		/* 0x14c */
859 	u32	ana_misc0;		/* 0x150 */
860 	u32	ana_misc0_set;		/* 0x154 */
861 	u32	ana_misc0_clr;		/* 0x158 */
862 	u32	ana_misc0_tog;		/* 0x15c */
863 	u32	ana_misc1;		/* 0x160 */
864 	u32	ana_misc1_set;		/* 0x164 */
865 	u32	ana_misc1_clr;		/* 0x168 */
866 	u32	ana_misc1_tog;		/* 0x16c */
867 	u32	ana_misc2;		/* 0x170 */
868 	u32	ana_misc2_set;		/* 0x174 */
869 	u32	ana_misc2_clr;		/* 0x178 */
870 	u32	ana_misc2_tog;		/* 0x17c */
871 	u32	tempsense0;		/* 0x180 */
872 	u32	tempsense0_set;		/* 0x184 */
873 	u32	tempsense0_clr;		/* 0x188 */
874 	u32	tempsense0_tog;		/* 0x18c */
875 	u32	tempsense1;		/* 0x190 */
876 	u32	tempsense1_set;		/* 0x194 */
877 	u32	tempsense1_clr;		/* 0x198 */
878 	u32	tempsense1_tog;		/* 0x19c */
879 	u32	usb1_vbus_detect;	/* 0x1a0 */
880 	u32	usb1_vbus_detect_set;	/* 0x1a4 */
881 	u32	usb1_vbus_detect_clr;	/* 0x1a8 */
882 	u32	usb1_vbus_detect_tog;	/* 0x1ac */
883 	u32	usb1_chrg_detect;	/* 0x1b0 */
884 	u32	usb1_chrg_detect_set;	/* 0x1b4 */
885 	u32	usb1_chrg_detect_clr;	/* 0x1b8 */
886 	u32	usb1_chrg_detect_tog;	/* 0x1bc */
887 	u32	usb1_vbus_det_stat;	/* 0x1c0 */
888 	u32	usb1_vbus_det_stat_set;	/* 0x1c4 */
889 	u32	usb1_vbus_det_stat_clr;	/* 0x1c8 */
890 	u32	usb1_vbus_det_stat_tog;	/* 0x1cc */
891 	u32	usb1_chrg_det_stat;	/* 0x1d0 */
892 	u32	usb1_chrg_det_stat_set;	/* 0x1d4 */
893 	u32	usb1_chrg_det_stat_clr;	/* 0x1d8 */
894 	u32	usb1_chrg_det_stat_tog;	/* 0x1dc */
895 	u32	usb1_loopback;		/* 0x1e0 */
896 	u32	usb1_loopback_set;	/* 0x1e4 */
897 	u32	usb1_loopback_clr;	/* 0x1e8 */
898 	u32	usb1_loopback_tog;	/* 0x1ec */
899 	u32	usb1_misc;		/* 0x1f0 */
900 	u32	usb1_misc_set;		/* 0x1f4 */
901 	u32	usb1_misc_clr;		/* 0x1f8 */
902 	u32	usb1_misc_tog;		/* 0x1fc */
903 	u32	usb2_vbus_detect;	/* 0x200 */
904 	u32	usb2_vbus_detect_set;	/* 0x204 */
905 	u32	usb2_vbus_detect_clr;	/* 0x208 */
906 	u32	usb2_vbus_detect_tog;	/* 0x20c */
907 	u32	usb2_chrg_detect;	/* 0x210 */
908 	u32	usb2_chrg_detect_set;	/* 0x214 */
909 	u32	usb2_chrg_detect_clr;	/* 0x218 */
910 	u32	usb2_chrg_detect_tog;	/* 0x21c */
911 	u32	usb2_vbus_det_stat;	/* 0x220 */
912 	u32	usb2_vbus_det_stat_set;	/* 0x224 */
913 	u32	usb2_vbus_det_stat_clr;	/* 0x228 */
914 	u32	usb2_vbus_det_stat_tog;	/* 0x22c */
915 	u32	usb2_chrg_det_stat;	/* 0x230 */
916 	u32	usb2_chrg_det_stat_set;	/* 0x234 */
917 	u32	usb2_chrg_det_stat_clr;	/* 0x238 */
918 	u32	usb2_chrg_det_stat_tog;	/* 0x23c */
919 	u32	usb2_loopback;		/* 0x240 */
920 	u32	usb2_loopback_set;	/* 0x244 */
921 	u32	usb2_loopback_clr;	/* 0x248 */
922 	u32	usb2_loopback_tog;	/* 0x24c */
923 	u32	usb2_misc;		/* 0x250 */
924 	u32	usb2_misc_set;		/* 0x254 */
925 	u32	usb2_misc_clr;		/* 0x258 */
926 	u32	usb2_misc_tog;		/* 0x25c */
927 	u32	digprog;		/* 0x260 */
928 	u32	reserved1[7];
929 	u32	digprog_sololite;	/* 0x280 */
930 };
931 
932 #define ANATOP_PFD_FRAC_SHIFT(n)	((n)*8)
933 #define ANATOP_PFD_FRAC_MASK(n)	(0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
934 #define ANATOP_PFD_STABLE_SHIFT(n)	(6+((n)*8))
935 #define ANATOP_PFD_STABLE_MASK(n)	(1<<ANATOP_PFD_STABLE_SHIFT(n))
936 #define ANATOP_PFD_CLKGATE_SHIFT(n)	(7+((n)*8))
937 #define ANATOP_PFD_CLKGATE_MASK(n)	(1<<ANATOP_PFD_CLKGATE_SHIFT(n))
938 
939 struct wdog_regs {
940 	u16	wcr;	/* Control */
941 	u16	wsr;	/* Service */
942 	u16	wrsr;	/* Reset Status */
943 	u16	wicr;	/* Interrupt Control */
944 	u16	wmcr;	/* Miscellaneous Control */
945 };
946 
947 #define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
948 #define PWMCR_DOZEEN		(1 << 24)
949 #define PWMCR_WAITEN		(1 << 23)
950 #define PWMCR_DBGEN		(1 << 22)
951 #define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
952 #define PWMCR_CLKSRC_IPG	(1 << 16)
953 #define PWMCR_EN		(1 << 0)
954 
955 struct pwm_regs {
956 	u32	cr;
957 	u32	sr;
958 	u32	ir;
959 	u32	sar;
960 	u32	pr;
961 	u32	cnr;
962 };
963 #endif /* __ASSEMBLER__*/
964 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
965