1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 17 */ 18 19 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 20 #define __ASM_ARCH_MX6_IMX_REGS_H__ 21 22 #define ARCH_MXC 23 24 #define CONFIG_SYS_CACHELINE_SIZE 32 25 26 #define ROMCP_ARB_BASE_ADDR 0x00000000 27 #define ROMCP_ARB_END_ADDR 0x000FFFFF 28 29 #ifdef CONFIG_MX6SL 30 #define GPU_2D_ARB_BASE_ADDR 0x02200000 31 #define GPU_2D_ARB_END_ADDR 0x02203FFF 32 #define OPENVG_ARB_BASE_ADDR 0x02204000 33 #define OPENVG_ARB_END_ADDR 0x02207FFF 34 #else 35 #define CAAM_ARB_BASE_ADDR 0x00100000 36 #define CAAM_ARB_END_ADDR 0x00103FFF 37 #define APBH_DMA_ARB_BASE_ADDR 0x00110000 38 #define APBH_DMA_ARB_END_ADDR 0x00117FFF 39 #define HDMI_ARB_BASE_ADDR 0x00120000 40 #define HDMI_ARB_END_ADDR 0x00128FFF 41 #define GPU_3D_ARB_BASE_ADDR 0x00130000 42 #define GPU_3D_ARB_END_ADDR 0x00133FFF 43 #define GPU_2D_ARB_BASE_ADDR 0x00134000 44 #define GPU_2D_ARB_END_ADDR 0x00137FFF 45 #define DTCP_ARB_BASE_ADDR 0x00138000 46 #define DTCP_ARB_END_ADDR 0x0013BFFF 47 #endif /* CONFIG_MX6SL */ 48 49 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 50 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 51 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 52 53 /* GPV - PL301 configuration ports */ 54 #ifdef CONFIG_MX6SL 55 #define GPV2_BASE_ADDR 0x00D00000 56 #else 57 #define GPV2_BASE_ADDR 0x00200000 58 #endif 59 60 #define GPV3_BASE_ADDR 0x00300000 61 #define GPV4_BASE_ADDR 0x00800000 62 #define IRAM_BASE_ADDR 0x00900000 63 #define SCU_BASE_ADDR 0x00A00000 64 #define IC_INTERFACES_BASE_ADDR 0x00A00100 65 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 66 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 67 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 68 #define GPV0_BASE_ADDR 0x00B00000 69 #define GPV1_BASE_ADDR 0x00C00000 70 #define PCIE_ARB_BASE_ADDR 0x01000000 71 #define PCIE_ARB_END_ADDR 0x01FFFFFF 72 73 #define AIPS1_ARB_BASE_ADDR 0x02000000 74 #define AIPS1_ARB_END_ADDR 0x020FFFFF 75 #define AIPS2_ARB_BASE_ADDR 0x02100000 76 #define AIPS2_ARB_END_ADDR 0x021FFFFF 77 #define SATA_ARB_BASE_ADDR 0x02200000 78 #define SATA_ARB_END_ADDR 0x02203FFF 79 #define OPENVG_ARB_BASE_ADDR 0x02204000 80 #define OPENVG_ARB_END_ADDR 0x02207FFF 81 #define HSI_ARB_BASE_ADDR 0x02208000 82 #define HSI_ARB_END_ADDR 0x0220BFFF 83 #define IPU1_ARB_BASE_ADDR 0x02400000 84 #define IPU1_ARB_END_ADDR 0x027FFFFF 85 #define IPU2_ARB_BASE_ADDR 0x02800000 86 #define IPU2_ARB_END_ADDR 0x02BFFFFF 87 #define WEIM_ARB_BASE_ADDR 0x08000000 88 #define WEIM_ARB_END_ADDR 0x0FFFFFFF 89 90 #ifdef CONFIG_MX6SL 91 #define MMDC0_ARB_BASE_ADDR 0x80000000 92 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF 93 #define MMDC1_ARB_BASE_ADDR 0xC0000000 94 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 95 #else 96 #define MMDC0_ARB_BASE_ADDR 0x10000000 97 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF 98 #define MMDC1_ARB_BASE_ADDR 0x80000000 99 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 100 #endif 101 102 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR 103 #define IPU_SOC_OFFSET 0x00200000 104 105 /* Defines for Blocks connected via AIPS (SkyBlue) */ 106 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 107 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 108 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 109 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 110 111 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 112 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 113 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 114 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 115 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 116 #ifdef CONFIG_MX6SL 117 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 118 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) 119 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 120 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 121 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 122 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 123 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 124 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) 125 #else 126 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 127 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 128 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 129 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 130 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 131 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 132 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 133 #endif 134 135 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 136 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 137 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 138 139 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 140 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 141 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 142 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 143 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 144 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 145 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 146 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 147 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 148 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 149 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 150 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 151 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 152 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 153 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 154 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 155 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 156 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 157 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 158 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 159 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 160 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 161 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 162 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 163 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 164 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 165 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 166 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 167 #ifdef CONFIG_MX6SL 168 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 169 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 170 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 171 #else 172 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 173 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 174 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 175 #endif 176 177 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 178 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 179 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 180 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 181 #ifdef CONFIG_MX6SL 182 #define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 183 #define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 184 #else 185 #define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 186 #define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 187 #endif 188 189 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 190 #ifdef CONFIG_MX6SL 191 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 192 #else 193 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 194 #endif 195 196 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 197 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 198 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 199 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 200 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 201 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 202 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 203 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 204 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 205 #ifdef CONFIG_MX6SL 206 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 207 #else 208 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 209 #endif 210 211 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 212 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 213 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 214 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 215 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 216 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 217 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 218 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 219 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 220 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 221 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 222 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 223 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 224 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 225 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 226 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 227 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 228 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 229 230 #define CHIP_REV_1_0 0x10 231 #define IRAM_SIZE 0x00040000 232 #define FEC_QUIRK_ENET_MAC 233 234 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 235 #include <asm/types.h> 236 237 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 238 239 /* System Reset Controller (SRC) */ 240 struct src { 241 u32 scr; 242 u32 sbmr1; 243 u32 srsr; 244 u32 reserved1[2]; 245 u32 sisr; 246 u32 simr; 247 u32 sbmr2; 248 u32 gpr1; 249 u32 gpr2; 250 u32 gpr3; 251 u32 gpr4; 252 u32 gpr5; 253 u32 gpr6; 254 u32 gpr7; 255 u32 gpr8; 256 u32 gpr9; 257 u32 gpr10; 258 }; 259 260 /* GPR3 bitfields */ 261 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 262 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) 263 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 264 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) 265 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 266 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) 267 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 268 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) 269 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 270 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) 271 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 272 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) 273 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 274 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) 275 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 276 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) 277 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 278 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) 279 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 280 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) 281 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 282 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) 283 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 284 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) 285 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 286 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) 287 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 288 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) 289 290 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 291 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 292 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 293 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 294 295 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 296 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) 297 298 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 299 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) 300 301 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 302 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) 303 304 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 305 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) 306 307 308 struct iomuxc { 309 u32 gpr[14]; 310 u32 omux[5]; 311 /* mux and pad registers */ 312 }; 313 314 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 315 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) 316 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 317 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) 318 319 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 320 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 321 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 322 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 323 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 324 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 325 326 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 327 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 328 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 329 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 330 331 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 332 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 333 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 334 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 335 336 #define IOMUXC_GPR2_BITMAP_SPWG 0 337 #define IOMUXC_GPR2_BITMAP_JEIDA 1 338 339 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 340 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 341 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 342 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 343 344 #define IOMUXC_GPR2_DATA_WIDTH_18 0 345 #define IOMUXC_GPR2_DATA_WIDTH_24 1 346 347 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 348 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 349 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 350 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 351 352 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 353 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 354 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 355 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 356 357 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 358 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 359 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 360 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 361 362 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 363 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) 364 365 #define IOMUXC_GPR2_MODE_DISABLED 0 366 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 367 #define IOMUXC_GPR2_MODE_ENABLED_DI1 2 368 369 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 370 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 371 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 372 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 373 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 374 375 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 376 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 377 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 378 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 379 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 380 381 /* ECSPI registers */ 382 struct cspi_regs { 383 u32 rxdata; 384 u32 txdata; 385 u32 ctrl; 386 u32 cfg; 387 u32 intr; 388 u32 dma; 389 u32 stat; 390 u32 period; 391 }; 392 393 /* 394 * CSPI register definitions 395 */ 396 #define MXC_ECSPI 397 #define MXC_CSPICTRL_EN (1 << 0) 398 #define MXC_CSPICTRL_MODE (1 << 1) 399 #define MXC_CSPICTRL_XCH (1 << 2) 400 #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 401 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 402 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 403 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 404 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 405 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 406 #define MXC_CSPICTRL_MAXBITS 0xfff 407 #define MXC_CSPICTRL_TC (1 << 7) 408 #define MXC_CSPICTRL_RXOVF (1 << 6) 409 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 410 #define MAX_SPI_BYTES 32 411 412 /* Bit position inside CTRL register to be associated with SS */ 413 #define MXC_CSPICTRL_CHAN 18 414 415 /* Bit position inside CON register to be associated with SS */ 416 #define MXC_CSPICON_POL 4 417 #define MXC_CSPICON_PHA 0 418 #define MXC_CSPICON_SSPOL 12 419 #ifdef CONFIG_MX6SL 420 #define MXC_SPI_BASE_ADDRESSES \ 421 ECSPI1_BASE_ADDR, \ 422 ECSPI2_BASE_ADDR, \ 423 ECSPI3_BASE_ADDR, \ 424 ECSPI4_BASE_ADDR 425 #else 426 #define MXC_SPI_BASE_ADDRESSES \ 427 ECSPI1_BASE_ADDR, \ 428 ECSPI2_BASE_ADDR, \ 429 ECSPI3_BASE_ADDR, \ 430 ECSPI4_BASE_ADDR, \ 431 ECSPI5_BASE_ADDR 432 #endif 433 434 struct ocotp_regs { 435 u32 ctrl; 436 u32 ctrl_set; 437 u32 ctrl_clr; 438 u32 ctrl_tog; 439 u32 timing; 440 u32 rsvd0[3]; 441 u32 data; 442 u32 rsvd1[3]; 443 u32 read_ctrl; 444 u32 rsvd2[3]; 445 u32 read_fuse_data; 446 u32 rsvd3[3]; 447 u32 sw_sticky; 448 u32 rsvd4[3]; 449 u32 scs; 450 u32 scs_set; 451 u32 scs_clr; 452 u32 scs_tog; 453 u32 crc_addr; 454 u32 rsvd5[3]; 455 u32 crc_value; 456 u32 rsvd6[3]; 457 u32 version; 458 u32 rsvd7[0xdb]; 459 460 struct fuse_bank { 461 u32 fuse_regs[0x20]; 462 } bank[16]; 463 }; 464 465 struct fuse_bank0_regs { 466 u32 lock; 467 u32 rsvd0[3]; 468 u32 uid_low; 469 u32 rsvd1[3]; 470 u32 uid_high; 471 u32 rsvd2[0x17]; 472 }; 473 474 struct fuse_bank4_regs { 475 u32 sjc_resp_low; 476 u32 rsvd0[3]; 477 u32 sjc_resp_high; 478 u32 rsvd1[3]; 479 u32 mac_addr_low; 480 u32 rsvd2[3]; 481 u32 mac_addr_high; 482 u32 rsvd3[0xb]; 483 u32 gp1; 484 u32 rsvd4[3]; 485 u32 gp2; 486 u32 rsvd5[3]; 487 }; 488 489 struct aipstz_regs { 490 u32 mprot0; 491 u32 mprot1; 492 u32 rsvd[0xe]; 493 u32 opacr0; 494 u32 opacr1; 495 u32 opacr2; 496 u32 opacr3; 497 u32 opacr4; 498 }; 499 500 struct anatop_regs { 501 u32 pll_sys; /* 0x000 */ 502 u32 pll_sys_set; /* 0x004 */ 503 u32 pll_sys_clr; /* 0x008 */ 504 u32 pll_sys_tog; /* 0x00c */ 505 u32 usb1_pll_480_ctrl; /* 0x010 */ 506 u32 usb1_pll_480_ctrl_set; /* 0x014 */ 507 u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 508 u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 509 u32 usb2_pll_480_ctrl; /* 0x020 */ 510 u32 usb2_pll_480_ctrl_set; /* 0x024 */ 511 u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 512 u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 513 u32 pll_528; /* 0x030 */ 514 u32 pll_528_set; /* 0x034 */ 515 u32 pll_528_clr; /* 0x038 */ 516 u32 pll_528_tog; /* 0x03c */ 517 u32 pll_528_ss; /* 0x040 */ 518 u32 rsvd0[3]; 519 u32 pll_528_num; /* 0x050 */ 520 u32 rsvd1[3]; 521 u32 pll_528_denom; /* 0x060 */ 522 u32 rsvd2[3]; 523 u32 pll_audio; /* 0x070 */ 524 u32 pll_audio_set; /* 0x074 */ 525 u32 pll_audio_clr; /* 0x078 */ 526 u32 pll_audio_tog; /* 0x07c */ 527 u32 pll_audio_num; /* 0x080 */ 528 u32 rsvd3[3]; 529 u32 pll_audio_denom; /* 0x090 */ 530 u32 rsvd4[3]; 531 u32 pll_video; /* 0x0a0 */ 532 u32 pll_video_set; /* 0x0a4 */ 533 u32 pll_video_clr; /* 0x0a8 */ 534 u32 pll_video_tog; /* 0x0ac */ 535 u32 pll_video_num; /* 0x0b0 */ 536 u32 rsvd5[3]; 537 u32 pll_video_denom; /* 0x0c0 */ 538 u32 rsvd6[3]; 539 u32 pll_mlb; /* 0x0d0 */ 540 u32 pll_mlb_set; /* 0x0d4 */ 541 u32 pll_mlb_clr; /* 0x0d8 */ 542 u32 pll_mlb_tog; /* 0x0dc */ 543 u32 pll_enet; /* 0x0e0 */ 544 u32 pll_enet_set; /* 0x0e4 */ 545 u32 pll_enet_clr; /* 0x0e8 */ 546 u32 pll_enet_tog; /* 0x0ec */ 547 u32 pfd_480; /* 0x0f0 */ 548 u32 pfd_480_set; /* 0x0f4 */ 549 u32 pfd_480_clr; /* 0x0f8 */ 550 u32 pfd_480_tog; /* 0x0fc */ 551 u32 pfd_528; /* 0x100 */ 552 u32 pfd_528_set; /* 0x104 */ 553 u32 pfd_528_clr; /* 0x108 */ 554 u32 pfd_528_tog; /* 0x10c */ 555 u32 reg_1p1; /* 0x110 */ 556 u32 reg_1p1_set; /* 0x114 */ 557 u32 reg_1p1_clr; /* 0x118 */ 558 u32 reg_1p1_tog; /* 0x11c */ 559 u32 reg_3p0; /* 0x120 */ 560 u32 reg_3p0_set; /* 0x124 */ 561 u32 reg_3p0_clr; /* 0x128 */ 562 u32 reg_3p0_tog; /* 0x12c */ 563 u32 reg_2p5; /* 0x130 */ 564 u32 reg_2p5_set; /* 0x134 */ 565 u32 reg_2p5_clr; /* 0x138 */ 566 u32 reg_2p5_tog; /* 0x13c */ 567 u32 reg_core; /* 0x140 */ 568 u32 reg_core_set; /* 0x144 */ 569 u32 reg_core_clr; /* 0x148 */ 570 u32 reg_core_tog; /* 0x14c */ 571 u32 ana_misc0; /* 0x150 */ 572 u32 ana_misc0_set; /* 0x154 */ 573 u32 ana_misc0_clr; /* 0x158 */ 574 u32 ana_misc0_tog; /* 0x15c */ 575 u32 ana_misc1; /* 0x160 */ 576 u32 ana_misc1_set; /* 0x164 */ 577 u32 ana_misc1_clr; /* 0x168 */ 578 u32 ana_misc1_tog; /* 0x16c */ 579 u32 ana_misc2; /* 0x170 */ 580 u32 ana_misc2_set; /* 0x174 */ 581 u32 ana_misc2_clr; /* 0x178 */ 582 u32 ana_misc2_tog; /* 0x17c */ 583 u32 tempsense0; /* 0x180 */ 584 u32 tempsense0_set; /* 0x184 */ 585 u32 tempsense0_clr; /* 0x188 */ 586 u32 tempsense0_tog; /* 0x18c */ 587 u32 tempsense1; /* 0x190 */ 588 u32 tempsense1_set; /* 0x194 */ 589 u32 tempsense1_clr; /* 0x198 */ 590 u32 tempsense1_tog; /* 0x19c */ 591 u32 usb1_vbus_detect; /* 0x1a0 */ 592 u32 usb1_vbus_detect_set; /* 0x1a4 */ 593 u32 usb1_vbus_detect_clr; /* 0x1a8 */ 594 u32 usb1_vbus_detect_tog; /* 0x1ac */ 595 u32 usb1_chrg_detect; /* 0x1b0 */ 596 u32 usb1_chrg_detect_set; /* 0x1b4 */ 597 u32 usb1_chrg_detect_clr; /* 0x1b8 */ 598 u32 usb1_chrg_detect_tog; /* 0x1bc */ 599 u32 usb1_vbus_det_stat; /* 0x1c0 */ 600 u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 601 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 602 u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 603 u32 usb1_chrg_det_stat; /* 0x1d0 */ 604 u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 605 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 606 u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 607 u32 usb1_loopback; /* 0x1e0 */ 608 u32 usb1_loopback_set; /* 0x1e4 */ 609 u32 usb1_loopback_clr; /* 0x1e8 */ 610 u32 usb1_loopback_tog; /* 0x1ec */ 611 u32 usb1_misc; /* 0x1f0 */ 612 u32 usb1_misc_set; /* 0x1f4 */ 613 u32 usb1_misc_clr; /* 0x1f8 */ 614 u32 usb1_misc_tog; /* 0x1fc */ 615 u32 usb2_vbus_detect; /* 0x200 */ 616 u32 usb2_vbus_detect_set; /* 0x204 */ 617 u32 usb2_vbus_detect_clr; /* 0x208 */ 618 u32 usb2_vbus_detect_tog; /* 0x20c */ 619 u32 usb2_chrg_detect; /* 0x210 */ 620 u32 usb2_chrg_detect_set; /* 0x214 */ 621 u32 usb2_chrg_detect_clr; /* 0x218 */ 622 u32 usb2_chrg_detect_tog; /* 0x21c */ 623 u32 usb2_vbus_det_stat; /* 0x220 */ 624 u32 usb2_vbus_det_stat_set; /* 0x224 */ 625 u32 usb2_vbus_det_stat_clr; /* 0x228 */ 626 u32 usb2_vbus_det_stat_tog; /* 0x22c */ 627 u32 usb2_chrg_det_stat; /* 0x230 */ 628 u32 usb2_chrg_det_stat_set; /* 0x234 */ 629 u32 usb2_chrg_det_stat_clr; /* 0x238 */ 630 u32 usb2_chrg_det_stat_tog; /* 0x23c */ 631 u32 usb2_loopback; /* 0x240 */ 632 u32 usb2_loopback_set; /* 0x244 */ 633 u32 usb2_loopback_clr; /* 0x248 */ 634 u32 usb2_loopback_tog; /* 0x24c */ 635 u32 usb2_misc; /* 0x250 */ 636 u32 usb2_misc_set; /* 0x254 */ 637 u32 usb2_misc_clr; /* 0x258 */ 638 u32 usb2_misc_tog; /* 0x25c */ 639 u32 digprog; /* 0x260 */ 640 u32 reserved1[7]; 641 u32 digprog_sololite; /* 0x280 */ 642 }; 643 644 #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 645 #define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT) 646 #define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6 647 #define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT) 648 #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7 649 #define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT) 650 #define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8 651 #define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT) 652 #define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14 653 #define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT) 654 #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15 655 #define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT) 656 #define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16 657 #define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT) 658 #define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22 659 #define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT) 660 #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23 661 #define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT) 662 #define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24 663 #define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT) 664 #define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30 665 #define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT) 666 #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31 667 668 struct iomuxc_base_regs { 669 u32 gpr[14]; /* 0x000 */ 670 u32 obsrv[5]; /* 0x038 */ 671 u32 swmux_ctl[197]; /* 0x04c */ 672 u32 swpad_ctl[250]; /* 0x360 */ 673 u32 swgrp[26]; /* 0x748 */ 674 u32 daisy[104]; /* 0x7b0..94c */ 675 }; 676 677 struct wdog_regs { 678 u16 wcr; /* Control */ 679 u16 wsr; /* Service */ 680 u16 wrsr; /* Reset Status */ 681 u16 wicr; /* Interrupt Control */ 682 u16 wmcr; /* Miscellaneous Control */ 683 }; 684 685 #endif /* __ASSEMBLER__*/ 686 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 687