1 /*
2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
9 
10 #define ARCH_MXC
11 
12 #define ROMCP_ARB_BASE_ADDR             0x00000000
13 #define ROMCP_ARB_END_ADDR              0x000FFFFF
14 
15 #ifdef CONFIG_MX6SL
16 #define GPU_2D_ARB_BASE_ADDR            0x02200000
17 #define GPU_2D_ARB_END_ADDR             0x02203FFF
18 #define OPENVG_ARB_BASE_ADDR            0x02204000
19 #define OPENVG_ARB_END_ADDR             0x02207FFF
20 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
21 #define CAAM_ARB_BASE_ADDR              0x00100000
22 #define CAAM_ARB_END_ADDR               0x00107FFF
23 #define GPU_ARB_BASE_ADDR               0x01800000
24 #define GPU_ARB_END_ADDR                0x01803FFF
25 #define APBH_DMA_ARB_BASE_ADDR          0x01804000
26 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
27 #define M4_BOOTROM_BASE_ADDR			0x007F8000
28 
29 #elif !defined(CONFIG_MX6SLL)
30 #define CAAM_ARB_BASE_ADDR              0x00100000
31 #define CAAM_ARB_END_ADDR               0x00103FFF
32 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
33 #define APBH_DMA_ARB_END_ADDR           0x00117FFF
34 #define HDMI_ARB_BASE_ADDR              0x00120000
35 #define HDMI_ARB_END_ADDR               0x00128FFF
36 #define GPU_3D_ARB_BASE_ADDR            0x00130000
37 #define GPU_3D_ARB_END_ADDR             0x00133FFF
38 #define GPU_2D_ARB_BASE_ADDR            0x00134000
39 #define GPU_2D_ARB_END_ADDR             0x00137FFF
40 #define DTCP_ARB_BASE_ADDR              0x00138000
41 #define DTCP_ARB_END_ADDR               0x0013BFFF
42 #endif	/* CONFIG_MX6SL */
43 
44 #define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
45 #define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
46 #define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
47 
48 /* GPV - PL301 configuration ports */
49 #if (defined(CONFIG_MX6SX) || \
50 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
51 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
52 #define GPV2_BASE_ADDR                  0x00D00000
53 #define GPV3_BASE_ADDR			0x00E00000
54 #define GPV4_BASE_ADDR			0x00F00000
55 #define GPV5_BASE_ADDR			0x01000000
56 #define GPV6_BASE_ADDR			0x01100000
57 #define PCIE_ARB_BASE_ADDR              0x08000000
58 #define PCIE_ARB_END_ADDR               0x08FFFFFF
59 
60 #else
61 #define GPV2_BASE_ADDR			0x00200000
62 #define GPV3_BASE_ADDR			0x00300000
63 #define GPV4_BASE_ADDR			0x00800000
64 #define PCIE_ARB_BASE_ADDR              0x01000000
65 #define PCIE_ARB_END_ADDR               0x01FFFFFF
66 #endif
67 
68 #define IRAM_BASE_ADDR			0x00900000
69 #define SCU_BASE_ADDR                   0x00A00000
70 #define IC_INTERFACES_BASE_ADDR         0x00A00100
71 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
72 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
73 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
74 #define L2_PL310_BASE			0x00A02000
75 #define GPV0_BASE_ADDR                  0x00B00000
76 #define GPV1_BASE_ADDR                  0x00C00000
77 
78 #define AIPS1_ARB_BASE_ADDR             0x02000000
79 #define AIPS1_ARB_END_ADDR              0x020FFFFF
80 #define AIPS2_ARB_BASE_ADDR             0x02100000
81 #define AIPS2_ARB_END_ADDR              0x021FFFFF
82 /* AIPS3 only on i.MX6SX */
83 #define AIPS3_ARB_BASE_ADDR             0x02200000
84 #define AIPS3_ARB_END_ADDR              0x022FFFFF
85 #ifdef CONFIG_MX6SX
86 #define WEIM_ARB_BASE_ADDR              0x50000000
87 #define WEIM_ARB_END_ADDR               0x57FFFFFF
88 #define QSPI0_AMBA_BASE                0x60000000
89 #define QSPI0_AMBA_END                 0x6FFFFFFF
90 #define QSPI1_AMBA_BASE                0x70000000
91 #define QSPI1_AMBA_END                 0x7FFFFFFF
92 #elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
93 #define WEIM_ARB_BASE_ADDR              0x50000000
94 #define WEIM_ARB_END_ADDR               0x57FFFFFF
95 #define QSPI0_AMBA_BASE                 0x60000000
96 #define QSPI0_AMBA_END                  0x6FFFFFFF
97 #elif !defined(CONFIG_MX6SLL)
98 #define SATA_ARB_BASE_ADDR              0x02200000
99 #define SATA_ARB_END_ADDR               0x02203FFF
100 #define OPENVG_ARB_BASE_ADDR            0x02204000
101 #define OPENVG_ARB_END_ADDR             0x02207FFF
102 #define HSI_ARB_BASE_ADDR               0x02208000
103 #define HSI_ARB_END_ADDR                0x0220BFFF
104 #define IPU1_ARB_BASE_ADDR              0x02400000
105 #define IPU1_ARB_END_ADDR               0x027FFFFF
106 #define IPU2_ARB_BASE_ADDR              0x02800000
107 #define IPU2_ARB_END_ADDR               0x02BFFFFF
108 #define WEIM_ARB_BASE_ADDR              0x08000000
109 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
110 #endif
111 
112 #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
113 	defined(CONFIG_MX6SX) || \
114 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
115 #define MMDC0_ARB_BASE_ADDR             0x80000000
116 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
117 #define MMDC1_ARB_BASE_ADDR             0xC0000000
118 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
119 #else
120 #define MMDC0_ARB_BASE_ADDR             0x10000000
121 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
122 #define MMDC1_ARB_BASE_ADDR             0x80000000
123 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
124 #endif
125 
126 #ifndef CONFIG_MX6SX
127 #define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
128 #define IPU_SOC_OFFSET			0x00200000
129 #endif
130 
131 /* Defines for Blocks connected via AIPS (SkyBlue) */
132 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
133 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
134 #define ATZ3_BASE_ADDR              AIPS3_ARB_BASE_ADDR
135 #define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
136 #define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
137 #define AIPS3_BASE_ADDR             AIPS3_ON_BASE_ADDR
138 
139 #define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
140 #define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
141 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
142 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
143 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
144 
145 #define MX6SL_UART5_BASE_ADDR       (ATZ1_BASE_ADDR + 0x18000)
146 #define MX6SLL_UART4_BASE_ADDR      (ATZ1_BASE_ADDR + 0x18000)
147 #define MX6UL_UART7_BASE_ADDR       (ATZ1_BASE_ADDR + 0x18000)
148 #define MX6SL_UART2_BASE_ADDR       (ATZ1_BASE_ADDR + 0x24000)
149 #define MX6SLL_UART2_BASE_ADDR      (ATZ1_BASE_ADDR + 0x24000)
150 #define MX6UL_UART8_BASE_ADDR       (ATZ1_BASE_ADDR + 0x24000)
151 #define MX6SL_UART3_BASE_ADDR       (ATZ1_BASE_ADDR + 0x34000)
152 #define MX6SLL_UART3_BASE_ADDR      (ATZ1_BASE_ADDR + 0x34000)
153 #define MX6SL_UART4_BASE_ADDR       (ATZ1_BASE_ADDR + 0x38000)
154 
155 #ifndef CONFIG_MX6SX
156 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
157 #endif
158 #define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
159 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
160 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
161 #define UART8_BASE                  (ATZ1_BASE_ADDR + 0x24000)
162 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
163 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
164 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
165 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
166 
167 #ifndef CONFIG_MX6SX
168 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
169 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
170 #endif
171 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
172 
173 #define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
174 #define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
175 #define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
176 #define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
177 #define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
178 #define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
179 #define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
180 /* QOSC on i.MX6SLL */
181 #define QOSC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
182 #define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
183 #define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
184 #define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
185 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
186 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
187 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
188 #define MX6UL_SNVS_LP_BASE_ADDR     (AIPS1_OFF_BASE_ADDR + 0x30000)
189 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
190 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
191 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
192 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
193 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
194 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
195 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
196 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
197 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
198 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
199 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
200 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
201 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
202 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
203 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
204 #define IOMUXC_GPR_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x64000)
205 #ifdef CONFIG_MX6SLL
206 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x68000)
207 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
208 #define PXP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x70000)
209 #define EPDC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
210 #define DCP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
211 #elif defined(CONFIG_MX6SL)
212 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
213 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
214 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
215 #elif defined(CONFIG_MX6SX)
216 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
217 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
218 #define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)
219 #define SEMAPHORE1_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x74000)
220 #define SEMAPHORE2_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x78000)
221 #define RDC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
222 #else
223 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
224 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
225 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
226 #endif
227 
228 #define MX6SL_LCDIF_BASE_ADDR      (AIPS1_OFF_BASE_ADDR + 0x78000)
229 #define MX6SLL_LCDIF_BASE_ADDR      (AIPS1_OFF_BASE_ADDR + 0x78000)
230 
231 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
232 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
233 #define AIPS3_ON_BASE_ADDR          (ATZ3_BASE_ADDR + 0x7C000)
234 #define AIPS3_OFF_BASE_ADDR         (ATZ3_BASE_ADDR + 0x80000)
235 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
236 #define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
237 
238 #define CONFIG_SYS_FSL_SEC_OFFSET   0
239 #define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
240 				     CONFIG_SYS_FSL_SEC_OFFSET)
241 #define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
242 #define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
243 				     CONFIG_SYS_FSL_JR0_OFFSET)
244 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
245 
246 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
247 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
248 
249 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
250 #ifdef CONFIG_MX6SL
251 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
252 #else
253 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
254 #endif
255 
256 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
257 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
258 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
259 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
260 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
261 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
262 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
263 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
264 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
265 /* i.MX6SL/SLL */
266 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
267 #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
268 #define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
269 #else
270 /* i.MX6SX */
271 #define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
272 #endif
273 /* i.MX6DQ/SDL */
274 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
275 
276 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
277 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
278 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
279 #ifdef CONFIG_MX6SLL
280 #define IOMUXC_GPR_SNVS_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x44000)
281 #define IOMUXC_SNVS_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x48000)
282 #endif
283 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
284 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
285 #define MX6UL_LCDIF1_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x48000)
286 #define MX6ULL_LCDIF1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x48000)
287 #ifdef CONFIG_MX6SX
288 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
289 #else
290 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
291 #endif
292 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
293 #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
294 #define SCTR_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
295 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
296 #define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
297 #elif defined(CONFIG_MX6SX)
298 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
299 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
300 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
301 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
302 #define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
303 #else
304 #define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
305 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
306 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
307 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
308 #endif
309 #define MX6UL_WDOG3_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x64000)
310 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
311 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
312 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
313 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
314 #define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
315 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
316 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
317 /* i.MX6SLL */
318 #define MTR_MASTER_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x7C000)
319 
320 #ifdef CONFIG_MX6SX
321 #define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
322 #define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
323 #define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)
324 #define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
325 #define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
326 #define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
327 #define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
328 #define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
329 #define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
330 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
331 #define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
332 #define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
333 #define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
334 #define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
335 #define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
336 #define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
337 #define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
338 #define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
339 #define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
340 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
341 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
342 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
343 #elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
344 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
345 #define DCP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x80000)
346 #define RNGB_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
347 #define UART8_IPS_BASE_ADDR         (AIPS3_ARB_BASE_ADDR + 0x88000)
348 #define EPDC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x8C000)
349 #define IOMUXC_SNVS_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x90000)
350 #define SNVS_GPR_BASE_ADDR          (AIPS3_ARB_BASE_ADDR + 0x94000)
351 #endif
352 
353 #define NOC_DDR_BASE_ADDR           (GPV0_BASE_ADDR + 0xB0000)
354 
355 /* Only for i.MX6SX */
356 #define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
357 #define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
358 #define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
359 
360 #if !(defined(CONFIG_MX6SX) || \
361 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
362 	defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
363 #define IRAM_SIZE                    0x00040000
364 #else
365 #define IRAM_SIZE                    0x00020000
366 #endif
367 #define FEC_QUIRK_ENET_MAC
368 
369 #include <asm/mach-imx/regs-lcdif.h>
370 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
371 #include <asm/types.h>
372 
373 /* only for i.MX6SX/UL */
374 #define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ?	\
375 			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR))
376 #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ?	\
377 			  MX6SLL_LCDIF_BASE_ADDR :		\
378 			  (is_cpu_type(MXC_CPU_MX6SL)) ?	\
379 			  MX6SL_LCDIF_BASE_ADDR :		\
380 			  ((is_cpu_type(MXC_CPU_MX6UL)) ?	\
381 			  MX6UL_LCDIF1_BASE_ADDR :		\
382 			  ((is_mx6ull()) ?	\
383 			  MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
384 
385 
386 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
387 
388 #define SRC_SCR_CORE_1_RESET_OFFSET     14
389 #define SRC_SCR_CORE_1_RESET_MASK       (1<<SRC_SCR_CORE_1_RESET_OFFSET)
390 #define SRC_SCR_CORE_2_RESET_OFFSET     15
391 #define SRC_SCR_CORE_2_RESET_MASK       (1<<SRC_SCR_CORE_2_RESET_OFFSET)
392 #define SRC_SCR_CORE_3_RESET_OFFSET     16
393 #define SRC_SCR_CORE_3_RESET_MASK       (1<<SRC_SCR_CORE_3_RESET_OFFSET)
394 #define SRC_SCR_CORE_1_ENABLE_OFFSET    22
395 #define SRC_SCR_CORE_1_ENABLE_MASK      (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
396 #define SRC_SCR_CORE_2_ENABLE_OFFSET    23
397 #define SRC_SCR_CORE_2_ENABLE_MASK      (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
398 #define SRC_SCR_CORE_3_ENABLE_OFFSET    24
399 #define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
400 
401 struct rdc_regs {
402 	u32	vir;		/* Version information */
403 	u32	reserved1[8];
404 	u32	stat;		/* Status */
405 	u32	intctrl;	/* Interrupt and Control */
406 	u32	intstat;	/* Interrupt Status */
407 	u32	reserved2[116];
408 	u32	mda[32];	/* Master Domain Assignment */
409 	u32	reserved3[96];
410 	u32	pdap[104];	/* Peripheral Domain Access Permissions */
411 	u32	reserved4[88];
412 	struct {
413 		u32 mrsa;	/* Memory Region Start Address */
414 		u32 mrea;	/* Memory Region End Address */
415 		u32 mrc;	/* Memory Region Control */
416 		u32 mrvs;	/* Memory Region Violation Status */
417 	} mem_region[55];
418 };
419 
420 struct rdc_sema_regs {
421 	u8	gate[64];	/* Gate */
422 	u16	rstgt;		/* Reset Gate */
423 };
424 
425 /* WEIM registers */
426 struct weim {
427 	u32 cs0gcr1;
428 	u32 cs0gcr2;
429 	u32 cs0rcr1;
430 	u32 cs0rcr2;
431 	u32 cs0wcr1;
432 	u32 cs0wcr2;
433 
434 	u32 cs1gcr1;
435 	u32 cs1gcr2;
436 	u32 cs1rcr1;
437 	u32 cs1rcr2;
438 	u32 cs1wcr1;
439 	u32 cs1wcr2;
440 
441 	u32 cs2gcr1;
442 	u32 cs2gcr2;
443 	u32 cs2rcr1;
444 	u32 cs2rcr2;
445 	u32 cs2wcr1;
446 	u32 cs2wcr2;
447 
448 	u32 cs3gcr1;
449 	u32 cs3gcr2;
450 	u32 cs3rcr1;
451 	u32 cs3rcr2;
452 	u32 cs3wcr1;
453 	u32 cs3wcr2;
454 
455 	u32 unused[12];
456 
457 	u32 wcr;
458 	u32 wiar;
459 	u32 ear;
460 };
461 
462 /* System Reset Controller (SRC) */
463 struct src {
464 	u32	scr;
465 	u32	sbmr1;
466 	u32	srsr;
467 	u32	reserved1[2];
468 	u32	sisr;
469 	u32	simr;
470 	u32     sbmr2;
471 	u32     gpr1;
472 	u32     gpr2;
473 	u32     gpr3;
474 	u32     gpr4;
475 	u32     gpr5;
476 	u32     gpr6;
477 	u32     gpr7;
478 	u32     gpr8;
479 	u32     gpr9;
480 	u32     gpr10;
481 };
482 
483 #define src_base ((struct src *)SRC_BASE_ADDR)
484 
485 #define SRC_M4_REG_OFFSET		0
486 #define SRC_M4_ENABLE_OFFSET		22
487 #define SRC_M4_ENABLE_MASK		BIT(22)
488 #define SRC_M4C_NON_SCLR_RST_OFFSET	4
489 #define SRC_M4C_NON_SCLR_RST_MASK	BIT(4)
490 
491 /* GPR1 bitfields */
492 #define IOMUXC_GPR1_APP_CLK_REQ_N		BIT(30)
493 #define IOMUXC_GPR1_PCIE_EXIT_L1		BIT(28)
494 #define IOMUXC_GPR1_PCIE_RDY_L23		BIT(27)
495 #define IOMUXC_GPR1_PCIE_ENTER_L1		BIT(26)
496 #define IOMUXC_GPR1_MIPI_COLOR_SW		BIT(25)
497 #define IOMUXC_GPR1_DPI_OFF			BIT(24)
498 #define IOMUXC_GPR1_EXC_MON_SLVE		BIT(22)
499 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET		21
500 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK		(1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
501 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(20)
502 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(19)
503 #define IOMUXC_GPR1_PCIE_TEST_PD			BIT(18)
504 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2		BIT(17)
505 #define IOMUXC_GPR1_PCIE_REF_CLK_EN		BIT(16)
506 #define IOMUXC_GPR1_USB_EXP_MODE			BIT(15)
507 #define IOMUXC_GPR1_PCIE_INT			BIT(14)
508 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET		13
509 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK		(1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
510 #define IOMUXC_GPR1_GINT				BIT(12)
511 #define IOMUXC_GPR1_ADDRS3_MASK			(0x3 << 10)
512 #define IOMUXC_GPR1_ADDRS3_32MB			(0x0 << 10)
513 #define IOMUXC_GPR1_ADDRS3_64MB			(0x1 << 10)
514 #define IOMUXC_GPR1_ADDRS3_128MB			(0x2 << 10)
515 #define IOMUXC_GPR1_ACT_CS3			BIT(9)
516 #define IOMUXC_GPR1_ADDRS2_MASK			(0x3 << 7)
517 #define IOMUXC_GPR1_ACT_CS2			BIT(6)
518 #define IOMUXC_GPR1_ADDRS1_MASK			(0x3 << 4)
519 #define IOMUXC_GPR1_ACT_CS1			BIT(3)
520 #define IOMUXC_GPR1_ADDRS0_OFFSET		(1)
521 #define IOMUXC_GPR1_ADDRS0_MASK			(0x3 << 1)
522 #define IOMUXC_GPR1_ACT_CS0			BIT(0)
523 
524 /* GPR3 bitfields */
525 #define IOMUXC_GPR3_GPU_DBG_OFFSET		29
526 #define IOMUXC_GPR3_GPU_DBG_MASK		(3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
527 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET	28
528 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
529 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET	27
530 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
531 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET	26
532 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
533 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET	25
534 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
535 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET		21
536 #define IOMUXC_GPR3_OCRAM_CTL_MASK		(0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
537 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET		17
538 #define IOMUXC_GPR3_OCRAM_STATUS_MASK		(0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
539 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET	16
540 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
541 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET	15
542 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
543 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET	14
544 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
545 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET	13
546 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
547 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET	12
548 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
549 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET	11
550 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
551 #define IOMUXC_GPR3_IPU_DIAG_OFFSET		10
552 #define IOMUXC_GPR3_IPU_DIAG_MASK		(1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
553 
554 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0	0
555 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1	1
556 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0	2
557 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1	3
558 
559 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET	8
560 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
561 
562 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET	6
563 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
564 
565 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET		4
566 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
567 
568 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET		2
569 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
570 
571 /* gpr12 bitfields */
572 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN		BIT(27)
573 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN		BIT(26)
574 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN		BIT(25)
575 #define IOMUXC_GPR12_ARMP_APB_CLK_EN		BIT(24)
576 #define IOMUXC_GPR12_DEVICE_TYPE		(0xf << 12)
577 #define IOMUXC_GPR12_PCIE_CTL_2			BIT(10)
578 #define IOMUXC_GPR12_LOS_LEVEL			(0x1f << 4)
579 
580 struct iomuxc {
581 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
582 	u8 reserved[0x4000];
583 #endif
584 	u32 gpr[14];
585 };
586 
587 struct gpc {
588 	u32	cntr;
589 	u32	pgr;
590 	u32	imr1;
591 	u32	imr2;
592 	u32	imr3;
593 	u32	imr4;
594 	u32	isr1;
595 	u32	isr2;
596 	u32	isr3;
597 	u32	isr4;
598 };
599 
600 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
601 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
602 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16
603 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK			(7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
604 
605 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET			15
606 #define IOMUXC_GPR2_BGREF_RRMODE_MASK			(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
607 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES		(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
608 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES		(0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
609 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH	0
610 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW	1
611 
612 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET		10
613 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
614 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
615 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
616 
617 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET		9
618 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
619 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
620 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
621 
622 #define IOMUXC_GPR2_BITMAP_SPWG	0
623 #define IOMUXC_GPR2_BITMAP_JEIDA	1
624 
625 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET		8
626 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
627 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
628 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
629 
630 #define IOMUXC_GPR2_DATA_WIDTH_18	0
631 #define IOMUXC_GPR2_DATA_WIDTH_24	1
632 
633 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET		7
634 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
635 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
636 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
637 
638 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET		6
639 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
640 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
641 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
642 
643 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET		5
644 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
645 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
646 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
647 
648 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET		4
649 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK			(1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
650 
651 #define IOMUXC_GPR2_MODE_DISABLED	0
652 #define IOMUXC_GPR2_MODE_ENABLED_DI0	1
653 #define IOMUXC_GPR2_MODE_ENABLED_DI1	3
654 
655 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET		2
656 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
657 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
658 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
659 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
660 
661 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET		0
662 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
663 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
664 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
665 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
666 
667 /* ECSPI registers */
668 struct cspi_regs {
669 	u32 rxdata;
670 	u32 txdata;
671 	u32 ctrl;
672 	u32 cfg;
673 	u32 intr;
674 	u32 dma;
675 	u32 stat;
676 	u32 period;
677 };
678 
679 /*
680  * CSPI register definitions
681  */
682 #define MXC_ECSPI
683 #define MXC_CSPICTRL_EN		(1 << 0)
684 #define MXC_CSPICTRL_MODE	(1 << 1)
685 #define MXC_CSPICTRL_XCH	(1 << 2)
686 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
687 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
688 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
689 #define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
690 #define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
691 #define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
692 #define MXC_CSPICTRL_MAXBITS	0xfff
693 #define MXC_CSPICTRL_TC		(1 << 7)
694 #define MXC_CSPICTRL_RXOVF	(1 << 6)
695 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
696 #define MAX_SPI_BYTES	32
697 #define SPI_MAX_NUM	4
698 
699 /* Bit position inside CTRL register to be associated with SS */
700 #define MXC_CSPICTRL_CHAN	18
701 
702 /* Bit position inside CON register to be associated with SS */
703 #define MXC_CSPICON_PHA		0  /* SCLK phase control */
704 #define MXC_CSPICON_POL		4  /* SCLK polarity */
705 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
706 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
707 #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
708 	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
709 #define MXC_SPI_BASE_ADDRESSES \
710 	ECSPI1_BASE_ADDR, \
711 	ECSPI2_BASE_ADDR, \
712 	ECSPI3_BASE_ADDR, \
713 	ECSPI4_BASE_ADDR
714 #else
715 #define MXC_SPI_BASE_ADDRESSES \
716 	ECSPI1_BASE_ADDR, \
717 	ECSPI2_BASE_ADDR, \
718 	ECSPI3_BASE_ADDR, \
719 	ECSPI4_BASE_ADDR, \
720 	ECSPI5_BASE_ADDR
721 #endif
722 
723 struct ocotp_regs {
724 	u32	ctrl;
725 	u32	ctrl_set;
726 	u32     ctrl_clr;
727 	u32	ctrl_tog;
728 	u32	timing;
729 	u32     rsvd0[3];
730 	u32     data;
731 	u32     rsvd1[3];
732 	u32     read_ctrl;
733 	u32     rsvd2[3];
734 	u32	read_fuse_data;
735 	u32     rsvd3[3];
736 	u32	sw_sticky;
737 	u32     rsvd4[3];
738 	u32     scs;
739 	u32     scs_set;
740 	u32     scs_clr;
741 	u32     scs_tog;
742 	u32     crc_addr;
743 	u32     rsvd5[3];
744 	u32     crc_value;
745 	u32     rsvd6[3];
746 	u32     version;
747 	u32     rsvd7[0xdb];
748 
749 	/* fuse banks */
750 	struct fuse_bank {
751 		u32	fuse_regs[0x20];
752 	} bank[0];
753 };
754 
755 struct fuse_bank0_regs {
756 	u32	lock;
757 	u32	rsvd0[3];
758 	u32	uid_low;
759 	u32	rsvd1[3];
760 	u32	uid_high;
761 	u32	rsvd2[3];
762 	u32	cfg2;
763 	u32	rsvd3[3];
764 	u32	cfg3;
765 	u32	rsvd4[3];
766 	u32	cfg4;
767 	u32	rsvd5[3];
768 	u32	cfg5;
769 	u32	rsvd6[3];
770 	u32	cfg6;
771 	u32	rsvd7[3];
772 };
773 
774 struct fuse_bank1_regs {
775 	u32	mem0;
776 	u32	rsvd0[3];
777 	u32	mem1;
778 	u32	rsvd1[3];
779 	u32	mem2;
780 	u32	rsvd2[3];
781 	u32	mem3;
782 	u32	rsvd3[3];
783 	u32	mem4;
784 	u32	rsvd4[3];
785 	u32	ana0;
786 	u32	rsvd5[3];
787 	u32	ana1;
788 	u32	rsvd6[3];
789 	u32	ana2;
790 	u32	rsvd7[3];
791 };
792 
793 struct fuse_bank4_regs {
794 	u32 sjc_resp_low;
795 	u32 rsvd0[3];
796 	u32 sjc_resp_high;
797 	u32 rsvd1[3];
798 	u32 mac_addr0;
799 	u32 rsvd2[3];
800 	u32 mac_addr1;
801 	u32 rsvd3[3];
802 	u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
803 	u32 rsvd4[7];
804 	u32 gp1;
805 	u32 rsvd5[3];
806 	u32 gp2;
807 	u32 rsvd6[3];
808 };
809 
810 struct aipstz_regs {
811 	u32	mprot0;
812 	u32	mprot1;
813 	u32	rsvd[0xe];
814 	u32	opacr0;
815 	u32	opacr1;
816 	u32	opacr2;
817 	u32	opacr3;
818 	u32	opacr4;
819 };
820 
821 struct anatop_regs {
822 	u32	pll_sys;		/* 0x000 */
823 	u32	pll_sys_set;		/* 0x004 */
824 	u32	pll_sys_clr;		/* 0x008 */
825 	u32	pll_sys_tog;		/* 0x00c */
826 	u32	usb1_pll_480_ctrl;	/* 0x010 */
827 	u32	usb1_pll_480_ctrl_set;	/* 0x014 */
828 	u32	usb1_pll_480_ctrl_clr;	/* 0x018 */
829 	u32	usb1_pll_480_ctrl_tog;	/* 0x01c */
830 	u32	usb2_pll_480_ctrl;	/* 0x020 */
831 	u32	usb2_pll_480_ctrl_set;	/* 0x024 */
832 	u32	usb2_pll_480_ctrl_clr;	/* 0x028 */
833 	u32	usb2_pll_480_ctrl_tog;	/* 0x02c */
834 	u32	pll_528;		/* 0x030 */
835 	u32	pll_528_set;		/* 0x034 */
836 	u32	pll_528_clr;		/* 0x038 */
837 	u32	pll_528_tog;		/* 0x03c */
838 	u32	pll_528_ss;		/* 0x040 */
839 	u32	rsvd0[3];
840 	u32	pll_528_num;		/* 0x050 */
841 	u32	rsvd1[3];
842 	u32	pll_528_denom;		/* 0x060 */
843 	u32	rsvd2[3];
844 	u32	pll_audio;		/* 0x070 */
845 	u32	pll_audio_set;		/* 0x074 */
846 	u32	pll_audio_clr;		/* 0x078 */
847 	u32	pll_audio_tog;		/* 0x07c */
848 	u32	pll_audio_num;		/* 0x080 */
849 	u32	rsvd3[3];
850 	u32	pll_audio_denom;	/* 0x090 */
851 	u32	rsvd4[3];
852 	u32	pll_video;		/* 0x0a0 */
853 	u32	pll_video_set;		/* 0x0a4 */
854 	u32	pll_video_clr;		/* 0x0a8 */
855 	u32	pll_video_tog;		/* 0x0ac */
856 	u32	pll_video_num;		/* 0x0b0 */
857 	u32	rsvd5[3];
858 	u32	pll_video_denom;	/* 0x0c0 */
859 	u32	rsvd6[3];
860 	u32	pll_mlb;		/* 0x0d0 */
861 	u32	pll_mlb_set;		/* 0x0d4 */
862 	u32	pll_mlb_clr;		/* 0x0d8 */
863 	u32	pll_mlb_tog;		/* 0x0dc */
864 	u32	pll_enet;		/* 0x0e0 */
865 	u32	pll_enet_set;		/* 0x0e4 */
866 	u32	pll_enet_clr;		/* 0x0e8 */
867 	u32	pll_enet_tog;		/* 0x0ec */
868 	u32	pfd_480;		/* 0x0f0 */
869 	u32	pfd_480_set;		/* 0x0f4 */
870 	u32	pfd_480_clr;		/* 0x0f8 */
871 	u32	pfd_480_tog;		/* 0x0fc */
872 	u32	pfd_528;		/* 0x100 */
873 	u32	pfd_528_set;		/* 0x104 */
874 	u32	pfd_528_clr;		/* 0x108 */
875 	u32	pfd_528_tog;		/* 0x10c */
876 	u32	reg_1p1;		/* 0x110 */
877 	u32	reg_1p1_set;		/* 0x114 */
878 	u32	reg_1p1_clr;		/* 0x118 */
879 	u32	reg_1p1_tog;		/* 0x11c */
880 	u32	reg_3p0;		/* 0x120 */
881 	u32	reg_3p0_set;		/* 0x124 */
882 	u32	reg_3p0_clr;		/* 0x128 */
883 	u32	reg_3p0_tog;		/* 0x12c */
884 	u32	reg_2p5;		/* 0x130 */
885 	u32	reg_2p5_set;		/* 0x134 */
886 	u32	reg_2p5_clr;		/* 0x138 */
887 	u32	reg_2p5_tog;		/* 0x13c */
888 	u32	reg_core;		/* 0x140 */
889 	u32	reg_core_set;		/* 0x144 */
890 	u32	reg_core_clr;		/* 0x148 */
891 	u32	reg_core_tog;		/* 0x14c */
892 	u32	ana_misc0;		/* 0x150 */
893 	u32	ana_misc0_set;		/* 0x154 */
894 	u32	ana_misc0_clr;		/* 0x158 */
895 	u32	ana_misc0_tog;		/* 0x15c */
896 	u32	ana_misc1;		/* 0x160 */
897 	u32	ana_misc1_set;		/* 0x164 */
898 	u32	ana_misc1_clr;		/* 0x168 */
899 	u32	ana_misc1_tog;		/* 0x16c */
900 	u32	ana_misc2;		/* 0x170 */
901 	u32	ana_misc2_set;		/* 0x174 */
902 	u32	ana_misc2_clr;		/* 0x178 */
903 	u32	ana_misc2_tog;		/* 0x17c */
904 	u32	tempsense0;		/* 0x180 */
905 	u32	tempsense0_set;		/* 0x184 */
906 	u32	tempsense0_clr;		/* 0x188 */
907 	u32	tempsense0_tog;		/* 0x18c */
908 	u32	tempsense1;		/* 0x190 */
909 	u32	tempsense1_set;		/* 0x194 */
910 	u32	tempsense1_clr;		/* 0x198 */
911 	u32	tempsense1_tog;		/* 0x19c */
912 	u32	usb1_vbus_detect;	/* 0x1a0 */
913 	u32	usb1_vbus_detect_set;	/* 0x1a4 */
914 	u32	usb1_vbus_detect_clr;	/* 0x1a8 */
915 	u32	usb1_vbus_detect_tog;	/* 0x1ac */
916 	u32	usb1_chrg_detect;	/* 0x1b0 */
917 	u32	usb1_chrg_detect_set;	/* 0x1b4 */
918 	u32	usb1_chrg_detect_clr;	/* 0x1b8 */
919 	u32	usb1_chrg_detect_tog;	/* 0x1bc */
920 	u32	usb1_vbus_det_stat;	/* 0x1c0 */
921 	u32	usb1_vbus_det_stat_set;	/* 0x1c4 */
922 	u32	usb1_vbus_det_stat_clr;	/* 0x1c8 */
923 	u32	usb1_vbus_det_stat_tog;	/* 0x1cc */
924 	u32	usb1_chrg_det_stat;	/* 0x1d0 */
925 	u32	usb1_chrg_det_stat_set;	/* 0x1d4 */
926 	u32	usb1_chrg_det_stat_clr;	/* 0x1d8 */
927 	u32	usb1_chrg_det_stat_tog;	/* 0x1dc */
928 	u32	usb1_loopback;		/* 0x1e0 */
929 	u32	usb1_loopback_set;	/* 0x1e4 */
930 	u32	usb1_loopback_clr;	/* 0x1e8 */
931 	u32	usb1_loopback_tog;	/* 0x1ec */
932 	u32	usb1_misc;		/* 0x1f0 */
933 	u32	usb1_misc_set;		/* 0x1f4 */
934 	u32	usb1_misc_clr;		/* 0x1f8 */
935 	u32	usb1_misc_tog;		/* 0x1fc */
936 	u32	usb2_vbus_detect;	/* 0x200 */
937 	u32	usb2_vbus_detect_set;	/* 0x204 */
938 	u32	usb2_vbus_detect_clr;	/* 0x208 */
939 	u32	usb2_vbus_detect_tog;	/* 0x20c */
940 	u32	usb2_chrg_detect;	/* 0x210 */
941 	u32	usb2_chrg_detect_set;	/* 0x214 */
942 	u32	usb2_chrg_detect_clr;	/* 0x218 */
943 	u32	usb2_chrg_detect_tog;	/* 0x21c */
944 	u32	usb2_vbus_det_stat;	/* 0x220 */
945 	u32	usb2_vbus_det_stat_set;	/* 0x224 */
946 	u32	usb2_vbus_det_stat_clr;	/* 0x228 */
947 	u32	usb2_vbus_det_stat_tog;	/* 0x22c */
948 	u32	usb2_chrg_det_stat;	/* 0x230 */
949 	u32	usb2_chrg_det_stat_set;	/* 0x234 */
950 	u32	usb2_chrg_det_stat_clr;	/* 0x238 */
951 	u32	usb2_chrg_det_stat_tog;	/* 0x23c */
952 	u32	usb2_loopback;		/* 0x240 */
953 	u32	usb2_loopback_set;	/* 0x244 */
954 	u32	usb2_loopback_clr;	/* 0x248 */
955 	u32	usb2_loopback_tog;	/* 0x24c */
956 	u32	usb2_misc;		/* 0x250 */
957 	u32	usb2_misc_set;		/* 0x254 */
958 	u32	usb2_misc_clr;		/* 0x258 */
959 	u32	usb2_misc_tog;		/* 0x25c */
960 	u32	digprog;		/* 0x260 */
961 	u32	reserved1[7];
962 	u32	digprog_sololite;	/* 0x280 */
963 };
964 
965 #define ANATOP_PFD_FRAC_SHIFT(n)	((n)*8)
966 #define ANATOP_PFD_FRAC_MASK(n)	(0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
967 #define ANATOP_PFD_STABLE_SHIFT(n)	(6+((n)*8))
968 #define ANATOP_PFD_STABLE_MASK(n)	(1<<ANATOP_PFD_STABLE_SHIFT(n))
969 #define ANATOP_PFD_CLKGATE_SHIFT(n)	(7+((n)*8))
970 #define ANATOP_PFD_CLKGATE_MASK(n)	(1<<ANATOP_PFD_CLKGATE_SHIFT(n))
971 
972 struct wdog_regs {
973 	u16	wcr;	/* Control */
974 	u16	wsr;	/* Service */
975 	u16	wrsr;	/* Reset Status */
976 	u16	wicr;	/* Interrupt Control */
977 	u16	wmcr;	/* Miscellaneous Control */
978 };
979 
980 #define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
981 #define PWMCR_DOZEEN		(1 << 24)
982 #define PWMCR_WAITEN		(1 << 23)
983 #define PWMCR_DBGEN		(1 << 22)
984 #define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
985 #define PWMCR_CLKSRC_IPG	(1 << 16)
986 #define PWMCR_EN		(1 << 0)
987 
988 struct pwm_regs {
989 	u32	cr;
990 	u32	sr;
991 	u32	ir;
992 	u32	sar;
993 	u32	pr;
994 	u32	cnr;
995 };
996 #endif /* __ASSEMBLER__*/
997 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
998