1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 8 #define __ASM_ARCH_MX6_IMX_REGS_H__ 9 10 #define ARCH_MXC 11 12 #ifdef CONFIG_MX6UL 13 #define CONFIG_SYS_CACHELINE_SIZE 64 14 #else 15 #define CONFIG_SYS_CACHELINE_SIZE 32 16 #endif 17 18 #define ROMCP_ARB_BASE_ADDR 0x00000000 19 #define ROMCP_ARB_END_ADDR 0x000FFFFF 20 21 #ifdef CONFIG_MX6SL 22 #define GPU_2D_ARB_BASE_ADDR 0x02200000 23 #define GPU_2D_ARB_END_ADDR 0x02203FFF 24 #define OPENVG_ARB_BASE_ADDR 0x02204000 25 #define OPENVG_ARB_END_ADDR 0x02207FFF 26 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 27 #define CAAM_ARB_BASE_ADDR 0x00100000 28 #define CAAM_ARB_END_ADDR 0x00107FFF 29 #define GPU_ARB_BASE_ADDR 0x01800000 30 #define GPU_ARB_END_ADDR 0x01803FFF 31 #define APBH_DMA_ARB_BASE_ADDR 0x01804000 32 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF 33 #define M4_BOOTROM_BASE_ADDR 0x007F8000 34 35 #else 36 #define CAAM_ARB_BASE_ADDR 0x00100000 37 #define CAAM_ARB_END_ADDR 0x00103FFF 38 #define APBH_DMA_ARB_BASE_ADDR 0x00110000 39 #define APBH_DMA_ARB_END_ADDR 0x00117FFF 40 #define HDMI_ARB_BASE_ADDR 0x00120000 41 #define HDMI_ARB_END_ADDR 0x00128FFF 42 #define GPU_3D_ARB_BASE_ADDR 0x00130000 43 #define GPU_3D_ARB_END_ADDR 0x00133FFF 44 #define GPU_2D_ARB_BASE_ADDR 0x00134000 45 #define GPU_2D_ARB_END_ADDR 0x00137FFF 46 #define DTCP_ARB_BASE_ADDR 0x00138000 47 #define DTCP_ARB_END_ADDR 0x0013BFFF 48 #endif /* CONFIG_MX6SL */ 49 50 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 51 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 52 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 53 54 /* GPV - PL301 configuration ports */ 55 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 56 #define GPV2_BASE_ADDR 0x00D00000 57 #else 58 #define GPV2_BASE_ADDR 0x00200000 59 #endif 60 61 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 62 #define GPV3_BASE_ADDR 0x00E00000 63 #define GPV4_BASE_ADDR 0x00F00000 64 #define GPV5_BASE_ADDR 0x01000000 65 #define GPV6_BASE_ADDR 0x01100000 66 #define PCIE_ARB_BASE_ADDR 0x08000000 67 #define PCIE_ARB_END_ADDR 0x08FFFFFF 68 69 #else 70 #define GPV3_BASE_ADDR 0x00300000 71 #define GPV4_BASE_ADDR 0x00800000 72 #define PCIE_ARB_BASE_ADDR 0x01000000 73 #define PCIE_ARB_END_ADDR 0x01FFFFFF 74 #endif 75 76 #define IRAM_BASE_ADDR 0x00900000 77 #define SCU_BASE_ADDR 0x00A00000 78 #define IC_INTERFACES_BASE_ADDR 0x00A00100 79 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 80 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 81 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 82 #define L2_PL310_BASE 0x00A02000 83 #define GPV0_BASE_ADDR 0x00B00000 84 #define GPV1_BASE_ADDR 0x00C00000 85 86 #define AIPS1_ARB_BASE_ADDR 0x02000000 87 #define AIPS1_ARB_END_ADDR 0x020FFFFF 88 #define AIPS2_ARB_BASE_ADDR 0x02100000 89 #define AIPS2_ARB_END_ADDR 0x021FFFFF 90 /* AIPS3 only on i.MX6SX */ 91 #define AIPS3_ARB_BASE_ADDR 0x02200000 92 #define AIPS3_ARB_END_ADDR 0x022FFFFF 93 #ifdef CONFIG_MX6SX 94 #define WEIM_ARB_BASE_ADDR 0x50000000 95 #define WEIM_ARB_END_ADDR 0x57FFFFFF 96 #define QSPI0_AMBA_BASE 0x60000000 97 #define QSPI0_AMBA_END 0x6FFFFFFF 98 #define QSPI1_AMBA_BASE 0x70000000 99 #define QSPI1_AMBA_END 0x7FFFFFFF 100 #elif defined(CONFIG_MX6UL) 101 #define WEIM_ARB_BASE_ADDR 0x50000000 102 #define WEIM_ARB_END_ADDR 0x57FFFFFF 103 #define QSPI0_AMBA_BASE 0x60000000 104 #define QSPI0_AMBA_END 0x6FFFFFFF 105 #else 106 #define SATA_ARB_BASE_ADDR 0x02200000 107 #define SATA_ARB_END_ADDR 0x02203FFF 108 #define OPENVG_ARB_BASE_ADDR 0x02204000 109 #define OPENVG_ARB_END_ADDR 0x02207FFF 110 #define HSI_ARB_BASE_ADDR 0x02208000 111 #define HSI_ARB_END_ADDR 0x0220BFFF 112 #define IPU1_ARB_BASE_ADDR 0x02400000 113 #define IPU1_ARB_END_ADDR 0x027FFFFF 114 #define IPU2_ARB_BASE_ADDR 0x02800000 115 #define IPU2_ARB_END_ADDR 0x02BFFFFF 116 #define WEIM_ARB_BASE_ADDR 0x08000000 117 #define WEIM_ARB_END_ADDR 0x0FFFFFFF 118 #endif 119 120 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 121 #define MMDC0_ARB_BASE_ADDR 0x80000000 122 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF 123 #define MMDC1_ARB_BASE_ADDR 0xC0000000 124 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 125 #else 126 #define MMDC0_ARB_BASE_ADDR 0x10000000 127 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF 128 #define MMDC1_ARB_BASE_ADDR 0x80000000 129 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 130 #endif 131 132 #ifndef CONFIG_MX6SX 133 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR 134 #define IPU_SOC_OFFSET 0x00200000 135 #endif 136 137 /* Defines for Blocks connected via AIPS (SkyBlue) */ 138 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 139 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 140 #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR 141 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 142 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 143 #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR 144 145 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 146 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 147 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 148 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 149 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 150 #ifdef CONFIG_MX6SL 151 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 152 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) 153 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 154 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 155 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 156 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 157 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 158 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) 159 #else 160 #ifndef CONFIG_MX6SX 161 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 162 #endif 163 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 164 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 165 #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) 166 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 167 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 168 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 169 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 170 #endif 171 172 #ifndef CONFIG_MX6SX 173 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 174 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 175 #endif 176 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 177 178 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 179 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 180 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 181 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 182 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 183 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 184 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 185 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 186 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 187 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 188 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 189 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 190 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 191 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 192 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 193 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 194 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 195 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 196 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 197 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 198 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 199 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 200 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 201 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 202 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 203 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 204 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 205 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 206 #ifdef CONFIG_MX6SL 207 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 208 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 209 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 210 #elif CONFIG_MX6SX 211 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 212 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 213 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) 214 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 215 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 216 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) 217 #else 218 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 219 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 220 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 221 #endif 222 223 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 224 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 225 #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) 226 #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) 227 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 228 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 229 230 #define CONFIG_SYS_FSL_SEC_OFFSET 0 231 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ 232 CONFIG_SYS_FSL_SEC_OFFSET) 233 #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 234 #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ 235 CONFIG_SYS_FSL_JR0_OFFSET) 236 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 237 238 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 239 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 240 241 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 242 #ifdef CONFIG_MX6SL 243 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 244 #else 245 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 246 #endif 247 248 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 249 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 250 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 251 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 252 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 253 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 254 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 255 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 256 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 257 /* i.MX6SL */ 258 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 259 #ifdef CONFIG_MX6UL 260 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 261 #else 262 /* i.MX6SX */ 263 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 264 #endif 265 /* i.MX6DQ/SDL */ 266 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 267 268 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 269 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 270 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 271 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 272 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 273 #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 274 #ifdef CONFIG_MX6SX 275 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 276 #else 277 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 278 #endif 279 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 280 #ifdef CONFIG_MX6UL 281 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 282 #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 283 #elif defined(CONFIG_MX6SX) 284 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 285 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 286 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 287 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 288 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 289 #else 290 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 291 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 292 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 293 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 294 #endif 295 #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 296 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 297 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 298 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 299 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 300 #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 301 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 302 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 303 304 #ifdef CONFIG_MX6SX 305 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) 306 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) 307 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) 308 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) 309 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) 310 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) 311 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) 312 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) 313 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) 314 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) 315 #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) 316 #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) 317 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) 318 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) 319 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) 320 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) 321 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) 322 #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) 323 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) 324 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) 325 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) 326 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) 327 #endif 328 /* Only for i.MX6SX */ 329 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) 330 #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) 331 #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) 332 333 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 334 #define IRAM_SIZE 0x00040000 335 #else 336 #define IRAM_SIZE 0x00020000 337 #endif 338 #define FEC_QUIRK_ENET_MAC 339 340 #include <asm/imx-common/regs-lcdif.h> 341 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 342 #include <asm/types.h> 343 344 /* only for i.MX6SX/UL */ 345 #define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \ 346 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) 347 #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ 348 MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR) 349 350 351 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 352 353 #define SRC_SCR_CORE_1_RESET_OFFSET 14 354 #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET) 355 #define SRC_SCR_CORE_2_RESET_OFFSET 15 356 #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET) 357 #define SRC_SCR_CORE_3_RESET_OFFSET 16 358 #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET) 359 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22 360 #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET) 361 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23 362 #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET) 363 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24 364 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) 365 366 struct rdc_regs { 367 u32 vir; /* Version information */ 368 u32 reserved1[8]; 369 u32 stat; /* Status */ 370 u32 intctrl; /* Interrupt and Control */ 371 u32 intstat; /* Interrupt Status */ 372 u32 reserved2[116]; 373 u32 mda[32]; /* Master Domain Assignment */ 374 u32 reserved3[96]; 375 u32 pdap[104]; /* Peripheral Domain Access Permissions */ 376 u32 reserved4[88]; 377 struct { 378 u32 mrsa; /* Memory Region Start Address */ 379 u32 mrea; /* Memory Region End Address */ 380 u32 mrc; /* Memory Region Control */ 381 u32 mrvs; /* Memory Region Violation Status */ 382 } mem_region[55]; 383 }; 384 385 struct rdc_sema_regs { 386 u8 gate[64]; /* Gate */ 387 u16 rstgt; /* Reset Gate */ 388 }; 389 390 /* WEIM registers */ 391 struct weim { 392 u32 cs0gcr1; 393 u32 cs0gcr2; 394 u32 cs0rcr1; 395 u32 cs0rcr2; 396 u32 cs0wcr1; 397 u32 cs0wcr2; 398 399 u32 cs1gcr1; 400 u32 cs1gcr2; 401 u32 cs1rcr1; 402 u32 cs1rcr2; 403 u32 cs1wcr1; 404 u32 cs1wcr2; 405 406 u32 cs2gcr1; 407 u32 cs2gcr2; 408 u32 cs2rcr1; 409 u32 cs2rcr2; 410 u32 cs2wcr1; 411 u32 cs2wcr2; 412 413 u32 cs3gcr1; 414 u32 cs3gcr2; 415 u32 cs3rcr1; 416 u32 cs3rcr2; 417 u32 cs3wcr1; 418 u32 cs3wcr2; 419 420 u32 unused[12]; 421 422 u32 wcr; 423 u32 wiar; 424 u32 ear; 425 }; 426 427 /* System Reset Controller (SRC) */ 428 struct src { 429 u32 scr; 430 u32 sbmr1; 431 u32 srsr; 432 u32 reserved1[2]; 433 u32 sisr; 434 u32 simr; 435 u32 sbmr2; 436 u32 gpr1; 437 u32 gpr2; 438 u32 gpr3; 439 u32 gpr4; 440 u32 gpr5; 441 u32 gpr6; 442 u32 gpr7; 443 u32 gpr8; 444 u32 gpr9; 445 u32 gpr10; 446 }; 447 448 #define SRC_SCR_M4_ENABLE_OFFSET 22 449 #define SRC_SCR_M4_ENABLE_MASK (1 << 22) 450 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4 451 #define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4) 452 453 /* GPR1 bitfields */ 454 #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) 455 #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) 456 #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) 457 #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) 458 #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) 459 #define IOMUXC_GPR1_DPI_OFF BIT(24) 460 #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) 461 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 462 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) 463 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) 464 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) 465 #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) 466 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) 467 #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16) 468 #define IOMUXC_GPR1_USB_EXP_MODE BIT(15) 469 #define IOMUXC_GPR1_PCIE_INT BIT(14) 470 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 471 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) 472 #define IOMUXC_GPR1_GINT BIT(12) 473 #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10) 474 #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10) 475 #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10) 476 #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) 477 #define IOMUXC_GPR1_ACT_CS3 BIT(9) 478 #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7) 479 #define IOMUXC_GPR1_ACT_CS2 BIT(6) 480 #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4) 481 #define IOMUXC_GPR1_ACT_CS1 BIT(3) 482 #define IOMUXC_GPR1_ADDRS0_OFFSET (1) 483 #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1) 484 #define IOMUXC_GPR1_ACT_CS0 BIT(0) 485 486 /* GPR3 bitfields */ 487 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 488 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) 489 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 490 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) 491 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 492 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) 493 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 494 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) 495 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 496 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) 497 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 498 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) 499 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 500 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) 501 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 502 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) 503 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 504 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) 505 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 506 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) 507 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 508 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) 509 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 510 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) 511 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 512 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) 513 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 514 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) 515 516 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 517 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 518 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 519 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 520 521 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 522 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) 523 524 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 525 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) 526 527 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 528 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) 529 530 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 531 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) 532 533 /* gpr12 bitfields */ 534 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27) 535 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26) 536 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25) 537 #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24) 538 #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12) 539 #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10) 540 #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) 541 542 struct iomuxc { 543 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 544 u8 reserved[0x4000]; 545 #endif 546 u32 gpr[14]; 547 }; 548 549 struct gpc { 550 u32 cntr; 551 u32 pgr; 552 u32 imr1; 553 u32 imr2; 554 u32 imr3; 555 u32 imr4; 556 u32 isr1; 557 u32 isr2; 558 u32 isr3; 559 u32 isr4; 560 }; 561 562 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 563 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) 564 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 565 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) 566 567 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 568 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 569 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 570 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 571 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 572 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 573 574 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 575 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 576 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 577 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 578 579 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 580 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 581 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 582 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 583 584 #define IOMUXC_GPR2_BITMAP_SPWG 0 585 #define IOMUXC_GPR2_BITMAP_JEIDA 1 586 587 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 588 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 589 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 590 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 591 592 #define IOMUXC_GPR2_DATA_WIDTH_18 0 593 #define IOMUXC_GPR2_DATA_WIDTH_24 1 594 595 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 596 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 597 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 598 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 599 600 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 601 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 602 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 603 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 604 605 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 606 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 607 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 608 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 609 610 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 611 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) 612 613 #define IOMUXC_GPR2_MODE_DISABLED 0 614 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 615 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3 616 617 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 618 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 619 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 620 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 621 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 622 623 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 624 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 625 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 626 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 627 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 628 629 /* ECSPI registers */ 630 struct cspi_regs { 631 u32 rxdata; 632 u32 txdata; 633 u32 ctrl; 634 u32 cfg; 635 u32 intr; 636 u32 dma; 637 u32 stat; 638 u32 period; 639 }; 640 641 /* 642 * CSPI register definitions 643 */ 644 #define MXC_ECSPI 645 #define MXC_CSPICTRL_EN (1 << 0) 646 #define MXC_CSPICTRL_MODE (1 << 1) 647 #define MXC_CSPICTRL_XCH (1 << 2) 648 #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 649 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 650 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 651 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 652 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 653 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 654 #define MXC_CSPICTRL_MAXBITS 0xfff 655 #define MXC_CSPICTRL_TC (1 << 7) 656 #define MXC_CSPICTRL_RXOVF (1 << 6) 657 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 658 #define MAX_SPI_BYTES 32 659 #define SPI_MAX_NUM 4 660 661 /* Bit position inside CTRL register to be associated with SS */ 662 #define MXC_CSPICTRL_CHAN 18 663 664 /* Bit position inside CON register to be associated with SS */ 665 #define MXC_CSPICON_PHA 0 /* SCLK phase control */ 666 #define MXC_CSPICON_POL 4 /* SCLK polarity */ 667 #define MXC_CSPICON_SSPOL 12 /* SS polarity */ 668 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 669 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) 670 #define MXC_SPI_BASE_ADDRESSES \ 671 ECSPI1_BASE_ADDR, \ 672 ECSPI2_BASE_ADDR, \ 673 ECSPI3_BASE_ADDR, \ 674 ECSPI4_BASE_ADDR 675 #else 676 #define MXC_SPI_BASE_ADDRESSES \ 677 ECSPI1_BASE_ADDR, \ 678 ECSPI2_BASE_ADDR, \ 679 ECSPI3_BASE_ADDR, \ 680 ECSPI4_BASE_ADDR, \ 681 ECSPI5_BASE_ADDR 682 #endif 683 684 struct ocotp_regs { 685 u32 ctrl; 686 u32 ctrl_set; 687 u32 ctrl_clr; 688 u32 ctrl_tog; 689 u32 timing; 690 u32 rsvd0[3]; 691 u32 data; 692 u32 rsvd1[3]; 693 u32 read_ctrl; 694 u32 rsvd2[3]; 695 u32 read_fuse_data; 696 u32 rsvd3[3]; 697 u32 sw_sticky; 698 u32 rsvd4[3]; 699 u32 scs; 700 u32 scs_set; 701 u32 scs_clr; 702 u32 scs_tog; 703 u32 crc_addr; 704 u32 rsvd5[3]; 705 u32 crc_value; 706 u32 rsvd6[3]; 707 u32 version; 708 u32 rsvd7[0xdb]; 709 710 /* fuse banks */ 711 struct fuse_bank { 712 u32 fuse_regs[0x20]; 713 } bank[0]; 714 }; 715 716 struct fuse_bank0_regs { 717 u32 lock; 718 u32 rsvd0[3]; 719 u32 uid_low; 720 u32 rsvd1[3]; 721 u32 uid_high; 722 u32 rsvd2[3]; 723 u32 cfg2; 724 u32 rsvd3[3]; 725 u32 cfg3; 726 u32 rsvd4[3]; 727 u32 cfg4; 728 u32 rsvd5[3]; 729 u32 cfg5; 730 u32 rsvd6[3]; 731 u32 cfg6; 732 u32 rsvd7[3]; 733 }; 734 735 struct fuse_bank1_regs { 736 u32 mem0; 737 u32 rsvd0[3]; 738 u32 mem1; 739 u32 rsvd1[3]; 740 u32 mem2; 741 u32 rsvd2[3]; 742 u32 mem3; 743 u32 rsvd3[3]; 744 u32 mem4; 745 u32 rsvd4[3]; 746 u32 ana0; 747 u32 rsvd5[3]; 748 u32 ana1; 749 u32 rsvd6[3]; 750 u32 ana2; 751 u32 rsvd7[3]; 752 }; 753 754 struct fuse_bank4_regs { 755 u32 sjc_resp_low; 756 u32 rsvd0[3]; 757 u32 sjc_resp_high; 758 u32 rsvd1[3]; 759 u32 mac_addr0; 760 u32 rsvd2[3]; 761 u32 mac_addr1; 762 u32 rsvd3[3]; 763 u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/ 764 u32 rsvd4[7]; 765 u32 gp1; 766 u32 rsvd5[3]; 767 u32 gp2; 768 u32 rsvd6[3]; 769 }; 770 771 struct aipstz_regs { 772 u32 mprot0; 773 u32 mprot1; 774 u32 rsvd[0xe]; 775 u32 opacr0; 776 u32 opacr1; 777 u32 opacr2; 778 u32 opacr3; 779 u32 opacr4; 780 }; 781 782 struct anatop_regs { 783 u32 pll_sys; /* 0x000 */ 784 u32 pll_sys_set; /* 0x004 */ 785 u32 pll_sys_clr; /* 0x008 */ 786 u32 pll_sys_tog; /* 0x00c */ 787 u32 usb1_pll_480_ctrl; /* 0x010 */ 788 u32 usb1_pll_480_ctrl_set; /* 0x014 */ 789 u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 790 u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 791 u32 usb2_pll_480_ctrl; /* 0x020 */ 792 u32 usb2_pll_480_ctrl_set; /* 0x024 */ 793 u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 794 u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 795 u32 pll_528; /* 0x030 */ 796 u32 pll_528_set; /* 0x034 */ 797 u32 pll_528_clr; /* 0x038 */ 798 u32 pll_528_tog; /* 0x03c */ 799 u32 pll_528_ss; /* 0x040 */ 800 u32 rsvd0[3]; 801 u32 pll_528_num; /* 0x050 */ 802 u32 rsvd1[3]; 803 u32 pll_528_denom; /* 0x060 */ 804 u32 rsvd2[3]; 805 u32 pll_audio; /* 0x070 */ 806 u32 pll_audio_set; /* 0x074 */ 807 u32 pll_audio_clr; /* 0x078 */ 808 u32 pll_audio_tog; /* 0x07c */ 809 u32 pll_audio_num; /* 0x080 */ 810 u32 rsvd3[3]; 811 u32 pll_audio_denom; /* 0x090 */ 812 u32 rsvd4[3]; 813 u32 pll_video; /* 0x0a0 */ 814 u32 pll_video_set; /* 0x0a4 */ 815 u32 pll_video_clr; /* 0x0a8 */ 816 u32 pll_video_tog; /* 0x0ac */ 817 u32 pll_video_num; /* 0x0b0 */ 818 u32 rsvd5[3]; 819 u32 pll_video_denom; /* 0x0c0 */ 820 u32 rsvd6[3]; 821 u32 pll_mlb; /* 0x0d0 */ 822 u32 pll_mlb_set; /* 0x0d4 */ 823 u32 pll_mlb_clr; /* 0x0d8 */ 824 u32 pll_mlb_tog; /* 0x0dc */ 825 u32 pll_enet; /* 0x0e0 */ 826 u32 pll_enet_set; /* 0x0e4 */ 827 u32 pll_enet_clr; /* 0x0e8 */ 828 u32 pll_enet_tog; /* 0x0ec */ 829 u32 pfd_480; /* 0x0f0 */ 830 u32 pfd_480_set; /* 0x0f4 */ 831 u32 pfd_480_clr; /* 0x0f8 */ 832 u32 pfd_480_tog; /* 0x0fc */ 833 u32 pfd_528; /* 0x100 */ 834 u32 pfd_528_set; /* 0x104 */ 835 u32 pfd_528_clr; /* 0x108 */ 836 u32 pfd_528_tog; /* 0x10c */ 837 u32 reg_1p1; /* 0x110 */ 838 u32 reg_1p1_set; /* 0x114 */ 839 u32 reg_1p1_clr; /* 0x118 */ 840 u32 reg_1p1_tog; /* 0x11c */ 841 u32 reg_3p0; /* 0x120 */ 842 u32 reg_3p0_set; /* 0x124 */ 843 u32 reg_3p0_clr; /* 0x128 */ 844 u32 reg_3p0_tog; /* 0x12c */ 845 u32 reg_2p5; /* 0x130 */ 846 u32 reg_2p5_set; /* 0x134 */ 847 u32 reg_2p5_clr; /* 0x138 */ 848 u32 reg_2p5_tog; /* 0x13c */ 849 u32 reg_core; /* 0x140 */ 850 u32 reg_core_set; /* 0x144 */ 851 u32 reg_core_clr; /* 0x148 */ 852 u32 reg_core_tog; /* 0x14c */ 853 u32 ana_misc0; /* 0x150 */ 854 u32 ana_misc0_set; /* 0x154 */ 855 u32 ana_misc0_clr; /* 0x158 */ 856 u32 ana_misc0_tog; /* 0x15c */ 857 u32 ana_misc1; /* 0x160 */ 858 u32 ana_misc1_set; /* 0x164 */ 859 u32 ana_misc1_clr; /* 0x168 */ 860 u32 ana_misc1_tog; /* 0x16c */ 861 u32 ana_misc2; /* 0x170 */ 862 u32 ana_misc2_set; /* 0x174 */ 863 u32 ana_misc2_clr; /* 0x178 */ 864 u32 ana_misc2_tog; /* 0x17c */ 865 u32 tempsense0; /* 0x180 */ 866 u32 tempsense0_set; /* 0x184 */ 867 u32 tempsense0_clr; /* 0x188 */ 868 u32 tempsense0_tog; /* 0x18c */ 869 u32 tempsense1; /* 0x190 */ 870 u32 tempsense1_set; /* 0x194 */ 871 u32 tempsense1_clr; /* 0x198 */ 872 u32 tempsense1_tog; /* 0x19c */ 873 u32 usb1_vbus_detect; /* 0x1a0 */ 874 u32 usb1_vbus_detect_set; /* 0x1a4 */ 875 u32 usb1_vbus_detect_clr; /* 0x1a8 */ 876 u32 usb1_vbus_detect_tog; /* 0x1ac */ 877 u32 usb1_chrg_detect; /* 0x1b0 */ 878 u32 usb1_chrg_detect_set; /* 0x1b4 */ 879 u32 usb1_chrg_detect_clr; /* 0x1b8 */ 880 u32 usb1_chrg_detect_tog; /* 0x1bc */ 881 u32 usb1_vbus_det_stat; /* 0x1c0 */ 882 u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 883 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 884 u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 885 u32 usb1_chrg_det_stat; /* 0x1d0 */ 886 u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 887 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 888 u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 889 u32 usb1_loopback; /* 0x1e0 */ 890 u32 usb1_loopback_set; /* 0x1e4 */ 891 u32 usb1_loopback_clr; /* 0x1e8 */ 892 u32 usb1_loopback_tog; /* 0x1ec */ 893 u32 usb1_misc; /* 0x1f0 */ 894 u32 usb1_misc_set; /* 0x1f4 */ 895 u32 usb1_misc_clr; /* 0x1f8 */ 896 u32 usb1_misc_tog; /* 0x1fc */ 897 u32 usb2_vbus_detect; /* 0x200 */ 898 u32 usb2_vbus_detect_set; /* 0x204 */ 899 u32 usb2_vbus_detect_clr; /* 0x208 */ 900 u32 usb2_vbus_detect_tog; /* 0x20c */ 901 u32 usb2_chrg_detect; /* 0x210 */ 902 u32 usb2_chrg_detect_set; /* 0x214 */ 903 u32 usb2_chrg_detect_clr; /* 0x218 */ 904 u32 usb2_chrg_detect_tog; /* 0x21c */ 905 u32 usb2_vbus_det_stat; /* 0x220 */ 906 u32 usb2_vbus_det_stat_set; /* 0x224 */ 907 u32 usb2_vbus_det_stat_clr; /* 0x228 */ 908 u32 usb2_vbus_det_stat_tog; /* 0x22c */ 909 u32 usb2_chrg_det_stat; /* 0x230 */ 910 u32 usb2_chrg_det_stat_set; /* 0x234 */ 911 u32 usb2_chrg_det_stat_clr; /* 0x238 */ 912 u32 usb2_chrg_det_stat_tog; /* 0x23c */ 913 u32 usb2_loopback; /* 0x240 */ 914 u32 usb2_loopback_set; /* 0x244 */ 915 u32 usb2_loopback_clr; /* 0x248 */ 916 u32 usb2_loopback_tog; /* 0x24c */ 917 u32 usb2_misc; /* 0x250 */ 918 u32 usb2_misc_set; /* 0x254 */ 919 u32 usb2_misc_clr; /* 0x258 */ 920 u32 usb2_misc_tog; /* 0x25c */ 921 u32 digprog; /* 0x260 */ 922 u32 reserved1[7]; 923 u32 digprog_sololite; /* 0x280 */ 924 }; 925 926 #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) 927 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) 928 #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) 929 #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) 930 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) 931 #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) 932 933 struct wdog_regs { 934 u16 wcr; /* Control */ 935 u16 wsr; /* Service */ 936 u16 wrsr; /* Reset Status */ 937 u16 wicr; /* Interrupt Control */ 938 u16 wmcr; /* Miscellaneous Control */ 939 }; 940 941 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) 942 #define PWMCR_DOZEEN (1 << 24) 943 #define PWMCR_WAITEN (1 << 23) 944 #define PWMCR_DBGEN (1 << 22) 945 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) 946 #define PWMCR_CLKSRC_IPG (1 << 16) 947 #define PWMCR_EN (1 << 0) 948 949 struct pwm_regs { 950 u32 cr; 951 u32 sr; 952 u32 ir; 953 u32 sar; 954 u32 pr; 955 u32 cnr; 956 }; 957 #endif /* __ASSEMBLER__*/ 958 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 959