1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 8 #define __ASM_ARCH_MX6_IMX_REGS_H__ 9 10 #define ARCH_MXC 11 12 #define ROMCP_ARB_BASE_ADDR 0x00000000 13 #define ROMCP_ARB_END_ADDR 0x000FFFFF 14 15 #ifdef CONFIG_MX6SL 16 #define GPU_2D_ARB_BASE_ADDR 0x02200000 17 #define GPU_2D_ARB_END_ADDR 0x02203FFF 18 #define OPENVG_ARB_BASE_ADDR 0x02204000 19 #define OPENVG_ARB_END_ADDR 0x02207FFF 20 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 21 #define CAAM_ARB_BASE_ADDR 0x00100000 22 #define CAAM_ARB_END_ADDR 0x00107FFF 23 #define GPU_ARB_BASE_ADDR 0x01800000 24 #define GPU_ARB_END_ADDR 0x01803FFF 25 #define APBH_DMA_ARB_BASE_ADDR 0x01804000 26 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF 27 #define M4_BOOTROM_BASE_ADDR 0x007F8000 28 29 #else 30 #define CAAM_ARB_BASE_ADDR 0x00100000 31 #define CAAM_ARB_END_ADDR 0x00103FFF 32 #define APBH_DMA_ARB_BASE_ADDR 0x00110000 33 #define APBH_DMA_ARB_END_ADDR 0x00117FFF 34 #define HDMI_ARB_BASE_ADDR 0x00120000 35 #define HDMI_ARB_END_ADDR 0x00128FFF 36 #define GPU_3D_ARB_BASE_ADDR 0x00130000 37 #define GPU_3D_ARB_END_ADDR 0x00133FFF 38 #define GPU_2D_ARB_BASE_ADDR 0x00134000 39 #define GPU_2D_ARB_END_ADDR 0x00137FFF 40 #define DTCP_ARB_BASE_ADDR 0x00138000 41 #define DTCP_ARB_END_ADDR 0x0013BFFF 42 #endif /* CONFIG_MX6SL */ 43 44 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 45 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 46 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 47 48 /* GPV - PL301 configuration ports */ 49 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 50 #define GPV2_BASE_ADDR 0x00D00000 51 #else 52 #define GPV2_BASE_ADDR 0x00200000 53 #endif 54 55 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 56 #define GPV3_BASE_ADDR 0x00E00000 57 #define GPV4_BASE_ADDR 0x00F00000 58 #define GPV5_BASE_ADDR 0x01000000 59 #define GPV6_BASE_ADDR 0x01100000 60 #define PCIE_ARB_BASE_ADDR 0x08000000 61 #define PCIE_ARB_END_ADDR 0x08FFFFFF 62 63 #else 64 #define GPV3_BASE_ADDR 0x00300000 65 #define GPV4_BASE_ADDR 0x00800000 66 #define PCIE_ARB_BASE_ADDR 0x01000000 67 #define PCIE_ARB_END_ADDR 0x01FFFFFF 68 #endif 69 70 #define IRAM_BASE_ADDR 0x00900000 71 #define SCU_BASE_ADDR 0x00A00000 72 #define IC_INTERFACES_BASE_ADDR 0x00A00100 73 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 74 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 75 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 76 #define L2_PL310_BASE 0x00A02000 77 #define GPV0_BASE_ADDR 0x00B00000 78 #define GPV1_BASE_ADDR 0x00C00000 79 80 #define AIPS1_ARB_BASE_ADDR 0x02000000 81 #define AIPS1_ARB_END_ADDR 0x020FFFFF 82 #define AIPS2_ARB_BASE_ADDR 0x02100000 83 #define AIPS2_ARB_END_ADDR 0x021FFFFF 84 /* AIPS3 only on i.MX6SX */ 85 #define AIPS3_ARB_BASE_ADDR 0x02200000 86 #define AIPS3_ARB_END_ADDR 0x022FFFFF 87 #ifdef CONFIG_MX6SX 88 #define WEIM_ARB_BASE_ADDR 0x50000000 89 #define WEIM_ARB_END_ADDR 0x57FFFFFF 90 #define QSPI0_AMBA_BASE 0x60000000 91 #define QSPI0_AMBA_END 0x6FFFFFFF 92 #define QSPI1_AMBA_BASE 0x70000000 93 #define QSPI1_AMBA_END 0x7FFFFFFF 94 #elif defined(CONFIG_MX6UL) 95 #define WEIM_ARB_BASE_ADDR 0x50000000 96 #define WEIM_ARB_END_ADDR 0x57FFFFFF 97 #define QSPI0_AMBA_BASE 0x60000000 98 #define QSPI0_AMBA_END 0x6FFFFFFF 99 #else 100 #define SATA_ARB_BASE_ADDR 0x02200000 101 #define SATA_ARB_END_ADDR 0x02203FFF 102 #define OPENVG_ARB_BASE_ADDR 0x02204000 103 #define OPENVG_ARB_END_ADDR 0x02207FFF 104 #define HSI_ARB_BASE_ADDR 0x02208000 105 #define HSI_ARB_END_ADDR 0x0220BFFF 106 #define IPU1_ARB_BASE_ADDR 0x02400000 107 #define IPU1_ARB_END_ADDR 0x027FFFFF 108 #define IPU2_ARB_BASE_ADDR 0x02800000 109 #define IPU2_ARB_END_ADDR 0x02BFFFFF 110 #define WEIM_ARB_BASE_ADDR 0x08000000 111 #define WEIM_ARB_END_ADDR 0x0FFFFFFF 112 #endif 113 114 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 115 #define MMDC0_ARB_BASE_ADDR 0x80000000 116 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF 117 #define MMDC1_ARB_BASE_ADDR 0xC0000000 118 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 119 #else 120 #define MMDC0_ARB_BASE_ADDR 0x10000000 121 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF 122 #define MMDC1_ARB_BASE_ADDR 0x80000000 123 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 124 #endif 125 126 #ifndef CONFIG_MX6SX 127 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR 128 #define IPU_SOC_OFFSET 0x00200000 129 #endif 130 131 /* Defines for Blocks connected via AIPS (SkyBlue) */ 132 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 133 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 134 #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR 135 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 136 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 137 #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR 138 139 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 140 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 141 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 142 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 143 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 144 #ifdef CONFIG_MX6SL 145 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 146 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) 147 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 148 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 149 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 150 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 151 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 152 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) 153 #else 154 #ifndef CONFIG_MX6SX 155 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 156 #endif 157 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 158 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 159 #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) 160 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 161 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 162 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 163 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 164 #endif 165 166 #ifndef CONFIG_MX6SX 167 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 168 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 169 #endif 170 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 171 172 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 173 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 174 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 175 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 176 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 177 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 178 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 179 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 180 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 181 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 182 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 183 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 184 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 185 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 186 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 187 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 188 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 189 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 190 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 191 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 192 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 193 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 194 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 195 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 196 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 197 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 198 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 199 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 200 #ifdef CONFIG_MX6SL 201 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 202 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 203 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 204 #elif CONFIG_MX6SX 205 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 206 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 207 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) 208 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 209 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 210 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) 211 #else 212 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 213 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 214 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 215 #endif 216 217 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 218 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 219 #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) 220 #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) 221 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 222 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 223 224 #define CONFIG_SYS_FSL_SEC_OFFSET 0 225 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ 226 CONFIG_SYS_FSL_SEC_OFFSET) 227 #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 228 #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ 229 CONFIG_SYS_FSL_JR0_OFFSET) 230 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 231 232 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 233 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 234 235 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 236 #ifdef CONFIG_MX6SL 237 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 238 #else 239 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 240 #endif 241 242 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 243 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 244 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 245 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 246 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 247 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 248 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 249 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 250 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 251 /* i.MX6SL */ 252 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 253 #ifdef CONFIG_MX6UL 254 #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 255 #else 256 /* i.MX6SX */ 257 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 258 #endif 259 /* i.MX6DQ/SDL */ 260 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 261 262 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 263 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 264 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 265 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 266 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 267 #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 268 #ifdef CONFIG_MX6SX 269 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 270 #else 271 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 272 #endif 273 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 274 #ifdef CONFIG_MX6UL 275 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 276 #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 277 #elif defined(CONFIG_MX6SX) 278 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 279 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 280 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 281 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 282 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 283 #else 284 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 285 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 286 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 287 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 288 #endif 289 #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 290 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 291 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 292 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 293 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 294 #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 295 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 296 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 297 298 #ifdef CONFIG_MX6SX 299 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) 300 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) 301 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) 302 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) 303 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) 304 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) 305 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) 306 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) 307 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) 308 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) 309 #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) 310 #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) 311 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) 312 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) 313 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) 314 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) 315 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) 316 #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) 317 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) 318 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) 319 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) 320 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) 321 #endif 322 /* Only for i.MX6SX */ 323 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) 324 #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) 325 #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) 326 327 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 328 #define IRAM_SIZE 0x00040000 329 #else 330 #define IRAM_SIZE 0x00020000 331 #endif 332 #define FEC_QUIRK_ENET_MAC 333 334 #include <asm/imx-common/regs-lcdif.h> 335 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 336 #include <asm/types.h> 337 338 /* only for i.MX6SX/UL */ 339 #define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \ 340 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) 341 #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ 342 MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR) 343 344 345 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 346 347 #define SRC_SCR_CORE_1_RESET_OFFSET 14 348 #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET) 349 #define SRC_SCR_CORE_2_RESET_OFFSET 15 350 #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET) 351 #define SRC_SCR_CORE_3_RESET_OFFSET 16 352 #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET) 353 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22 354 #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET) 355 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23 356 #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET) 357 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24 358 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) 359 360 struct rdc_regs { 361 u32 vir; /* Version information */ 362 u32 reserved1[8]; 363 u32 stat; /* Status */ 364 u32 intctrl; /* Interrupt and Control */ 365 u32 intstat; /* Interrupt Status */ 366 u32 reserved2[116]; 367 u32 mda[32]; /* Master Domain Assignment */ 368 u32 reserved3[96]; 369 u32 pdap[104]; /* Peripheral Domain Access Permissions */ 370 u32 reserved4[88]; 371 struct { 372 u32 mrsa; /* Memory Region Start Address */ 373 u32 mrea; /* Memory Region End Address */ 374 u32 mrc; /* Memory Region Control */ 375 u32 mrvs; /* Memory Region Violation Status */ 376 } mem_region[55]; 377 }; 378 379 struct rdc_sema_regs { 380 u8 gate[64]; /* Gate */ 381 u16 rstgt; /* Reset Gate */ 382 }; 383 384 /* WEIM registers */ 385 struct weim { 386 u32 cs0gcr1; 387 u32 cs0gcr2; 388 u32 cs0rcr1; 389 u32 cs0rcr2; 390 u32 cs0wcr1; 391 u32 cs0wcr2; 392 393 u32 cs1gcr1; 394 u32 cs1gcr2; 395 u32 cs1rcr1; 396 u32 cs1rcr2; 397 u32 cs1wcr1; 398 u32 cs1wcr2; 399 400 u32 cs2gcr1; 401 u32 cs2gcr2; 402 u32 cs2rcr1; 403 u32 cs2rcr2; 404 u32 cs2wcr1; 405 u32 cs2wcr2; 406 407 u32 cs3gcr1; 408 u32 cs3gcr2; 409 u32 cs3rcr1; 410 u32 cs3rcr2; 411 u32 cs3wcr1; 412 u32 cs3wcr2; 413 414 u32 unused[12]; 415 416 u32 wcr; 417 u32 wiar; 418 u32 ear; 419 }; 420 421 /* System Reset Controller (SRC) */ 422 struct src { 423 u32 scr; 424 u32 sbmr1; 425 u32 srsr; 426 u32 reserved1[2]; 427 u32 sisr; 428 u32 simr; 429 u32 sbmr2; 430 u32 gpr1; 431 u32 gpr2; 432 u32 gpr3; 433 u32 gpr4; 434 u32 gpr5; 435 u32 gpr6; 436 u32 gpr7; 437 u32 gpr8; 438 u32 gpr9; 439 u32 gpr10; 440 }; 441 442 #define SRC_SCR_M4_ENABLE_OFFSET 22 443 #define SRC_SCR_M4_ENABLE_MASK (1 << 22) 444 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4 445 #define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4) 446 447 /* GPR1 bitfields */ 448 #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) 449 #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) 450 #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) 451 #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) 452 #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) 453 #define IOMUXC_GPR1_DPI_OFF BIT(24) 454 #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) 455 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 456 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) 457 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) 458 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) 459 #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) 460 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) 461 #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16) 462 #define IOMUXC_GPR1_USB_EXP_MODE BIT(15) 463 #define IOMUXC_GPR1_PCIE_INT BIT(14) 464 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 465 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) 466 #define IOMUXC_GPR1_GINT BIT(12) 467 #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10) 468 #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10) 469 #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10) 470 #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) 471 #define IOMUXC_GPR1_ACT_CS3 BIT(9) 472 #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7) 473 #define IOMUXC_GPR1_ACT_CS2 BIT(6) 474 #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4) 475 #define IOMUXC_GPR1_ACT_CS1 BIT(3) 476 #define IOMUXC_GPR1_ADDRS0_OFFSET (1) 477 #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1) 478 #define IOMUXC_GPR1_ACT_CS0 BIT(0) 479 480 /* GPR3 bitfields */ 481 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 482 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) 483 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 484 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) 485 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 486 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) 487 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 488 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) 489 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 490 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) 491 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 492 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) 493 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 494 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) 495 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 496 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) 497 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 498 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) 499 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 500 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) 501 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 502 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) 503 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 504 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) 505 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 506 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) 507 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 508 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) 509 510 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 511 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 512 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 513 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 514 515 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 516 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) 517 518 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 519 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) 520 521 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 522 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) 523 524 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 525 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) 526 527 /* gpr12 bitfields */ 528 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27) 529 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26) 530 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25) 531 #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24) 532 #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12) 533 #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10) 534 #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) 535 536 struct iomuxc { 537 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 538 u8 reserved[0x4000]; 539 #endif 540 u32 gpr[14]; 541 }; 542 543 struct gpc { 544 u32 cntr; 545 u32 pgr; 546 u32 imr1; 547 u32 imr2; 548 u32 imr3; 549 u32 imr4; 550 u32 isr1; 551 u32 isr2; 552 u32 isr3; 553 u32 isr4; 554 }; 555 556 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 557 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) 558 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 559 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) 560 561 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 562 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 563 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 564 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 565 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 566 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 567 568 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 569 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 570 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 571 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 572 573 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 574 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 575 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 576 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 577 578 #define IOMUXC_GPR2_BITMAP_SPWG 0 579 #define IOMUXC_GPR2_BITMAP_JEIDA 1 580 581 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 582 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 583 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 584 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 585 586 #define IOMUXC_GPR2_DATA_WIDTH_18 0 587 #define IOMUXC_GPR2_DATA_WIDTH_24 1 588 589 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 590 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 591 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 592 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 593 594 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 595 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 596 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 597 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 598 599 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 600 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 601 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 602 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 603 604 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 605 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) 606 607 #define IOMUXC_GPR2_MODE_DISABLED 0 608 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 609 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3 610 611 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 612 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 613 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 614 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 615 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 616 617 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 618 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 619 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 620 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 621 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 622 623 /* ECSPI registers */ 624 struct cspi_regs { 625 u32 rxdata; 626 u32 txdata; 627 u32 ctrl; 628 u32 cfg; 629 u32 intr; 630 u32 dma; 631 u32 stat; 632 u32 period; 633 }; 634 635 /* 636 * CSPI register definitions 637 */ 638 #define MXC_ECSPI 639 #define MXC_CSPICTRL_EN (1 << 0) 640 #define MXC_CSPICTRL_MODE (1 << 1) 641 #define MXC_CSPICTRL_XCH (1 << 2) 642 #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 643 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 644 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 645 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 646 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 647 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 648 #define MXC_CSPICTRL_MAXBITS 0xfff 649 #define MXC_CSPICTRL_TC (1 << 7) 650 #define MXC_CSPICTRL_RXOVF (1 << 6) 651 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 652 #define MAX_SPI_BYTES 32 653 #define SPI_MAX_NUM 4 654 655 /* Bit position inside CTRL register to be associated with SS */ 656 #define MXC_CSPICTRL_CHAN 18 657 658 /* Bit position inside CON register to be associated with SS */ 659 #define MXC_CSPICON_PHA 0 /* SCLK phase control */ 660 #define MXC_CSPICON_POL 4 /* SCLK polarity */ 661 #define MXC_CSPICON_SSPOL 12 /* SS polarity */ 662 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 663 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) 664 #define MXC_SPI_BASE_ADDRESSES \ 665 ECSPI1_BASE_ADDR, \ 666 ECSPI2_BASE_ADDR, \ 667 ECSPI3_BASE_ADDR, \ 668 ECSPI4_BASE_ADDR 669 #else 670 #define MXC_SPI_BASE_ADDRESSES \ 671 ECSPI1_BASE_ADDR, \ 672 ECSPI2_BASE_ADDR, \ 673 ECSPI3_BASE_ADDR, \ 674 ECSPI4_BASE_ADDR, \ 675 ECSPI5_BASE_ADDR 676 #endif 677 678 struct ocotp_regs { 679 u32 ctrl; 680 u32 ctrl_set; 681 u32 ctrl_clr; 682 u32 ctrl_tog; 683 u32 timing; 684 u32 rsvd0[3]; 685 u32 data; 686 u32 rsvd1[3]; 687 u32 read_ctrl; 688 u32 rsvd2[3]; 689 u32 read_fuse_data; 690 u32 rsvd3[3]; 691 u32 sw_sticky; 692 u32 rsvd4[3]; 693 u32 scs; 694 u32 scs_set; 695 u32 scs_clr; 696 u32 scs_tog; 697 u32 crc_addr; 698 u32 rsvd5[3]; 699 u32 crc_value; 700 u32 rsvd6[3]; 701 u32 version; 702 u32 rsvd7[0xdb]; 703 704 /* fuse banks */ 705 struct fuse_bank { 706 u32 fuse_regs[0x20]; 707 } bank[0]; 708 }; 709 710 struct fuse_bank0_regs { 711 u32 lock; 712 u32 rsvd0[3]; 713 u32 uid_low; 714 u32 rsvd1[3]; 715 u32 uid_high; 716 u32 rsvd2[3]; 717 u32 cfg2; 718 u32 rsvd3[3]; 719 u32 cfg3; 720 u32 rsvd4[3]; 721 u32 cfg4; 722 u32 rsvd5[3]; 723 u32 cfg5; 724 u32 rsvd6[3]; 725 u32 cfg6; 726 u32 rsvd7[3]; 727 }; 728 729 struct fuse_bank1_regs { 730 u32 mem0; 731 u32 rsvd0[3]; 732 u32 mem1; 733 u32 rsvd1[3]; 734 u32 mem2; 735 u32 rsvd2[3]; 736 u32 mem3; 737 u32 rsvd3[3]; 738 u32 mem4; 739 u32 rsvd4[3]; 740 u32 ana0; 741 u32 rsvd5[3]; 742 u32 ana1; 743 u32 rsvd6[3]; 744 u32 ana2; 745 u32 rsvd7[3]; 746 }; 747 748 struct fuse_bank4_regs { 749 u32 sjc_resp_low; 750 u32 rsvd0[3]; 751 u32 sjc_resp_high; 752 u32 rsvd1[3]; 753 u32 mac_addr0; 754 u32 rsvd2[3]; 755 u32 mac_addr1; 756 u32 rsvd3[3]; 757 u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/ 758 u32 rsvd4[7]; 759 u32 gp1; 760 u32 rsvd5[3]; 761 u32 gp2; 762 u32 rsvd6[3]; 763 }; 764 765 struct aipstz_regs { 766 u32 mprot0; 767 u32 mprot1; 768 u32 rsvd[0xe]; 769 u32 opacr0; 770 u32 opacr1; 771 u32 opacr2; 772 u32 opacr3; 773 u32 opacr4; 774 }; 775 776 struct anatop_regs { 777 u32 pll_sys; /* 0x000 */ 778 u32 pll_sys_set; /* 0x004 */ 779 u32 pll_sys_clr; /* 0x008 */ 780 u32 pll_sys_tog; /* 0x00c */ 781 u32 usb1_pll_480_ctrl; /* 0x010 */ 782 u32 usb1_pll_480_ctrl_set; /* 0x014 */ 783 u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 784 u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 785 u32 usb2_pll_480_ctrl; /* 0x020 */ 786 u32 usb2_pll_480_ctrl_set; /* 0x024 */ 787 u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 788 u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 789 u32 pll_528; /* 0x030 */ 790 u32 pll_528_set; /* 0x034 */ 791 u32 pll_528_clr; /* 0x038 */ 792 u32 pll_528_tog; /* 0x03c */ 793 u32 pll_528_ss; /* 0x040 */ 794 u32 rsvd0[3]; 795 u32 pll_528_num; /* 0x050 */ 796 u32 rsvd1[3]; 797 u32 pll_528_denom; /* 0x060 */ 798 u32 rsvd2[3]; 799 u32 pll_audio; /* 0x070 */ 800 u32 pll_audio_set; /* 0x074 */ 801 u32 pll_audio_clr; /* 0x078 */ 802 u32 pll_audio_tog; /* 0x07c */ 803 u32 pll_audio_num; /* 0x080 */ 804 u32 rsvd3[3]; 805 u32 pll_audio_denom; /* 0x090 */ 806 u32 rsvd4[3]; 807 u32 pll_video; /* 0x0a0 */ 808 u32 pll_video_set; /* 0x0a4 */ 809 u32 pll_video_clr; /* 0x0a8 */ 810 u32 pll_video_tog; /* 0x0ac */ 811 u32 pll_video_num; /* 0x0b0 */ 812 u32 rsvd5[3]; 813 u32 pll_video_denom; /* 0x0c0 */ 814 u32 rsvd6[3]; 815 u32 pll_mlb; /* 0x0d0 */ 816 u32 pll_mlb_set; /* 0x0d4 */ 817 u32 pll_mlb_clr; /* 0x0d8 */ 818 u32 pll_mlb_tog; /* 0x0dc */ 819 u32 pll_enet; /* 0x0e0 */ 820 u32 pll_enet_set; /* 0x0e4 */ 821 u32 pll_enet_clr; /* 0x0e8 */ 822 u32 pll_enet_tog; /* 0x0ec */ 823 u32 pfd_480; /* 0x0f0 */ 824 u32 pfd_480_set; /* 0x0f4 */ 825 u32 pfd_480_clr; /* 0x0f8 */ 826 u32 pfd_480_tog; /* 0x0fc */ 827 u32 pfd_528; /* 0x100 */ 828 u32 pfd_528_set; /* 0x104 */ 829 u32 pfd_528_clr; /* 0x108 */ 830 u32 pfd_528_tog; /* 0x10c */ 831 u32 reg_1p1; /* 0x110 */ 832 u32 reg_1p1_set; /* 0x114 */ 833 u32 reg_1p1_clr; /* 0x118 */ 834 u32 reg_1p1_tog; /* 0x11c */ 835 u32 reg_3p0; /* 0x120 */ 836 u32 reg_3p0_set; /* 0x124 */ 837 u32 reg_3p0_clr; /* 0x128 */ 838 u32 reg_3p0_tog; /* 0x12c */ 839 u32 reg_2p5; /* 0x130 */ 840 u32 reg_2p5_set; /* 0x134 */ 841 u32 reg_2p5_clr; /* 0x138 */ 842 u32 reg_2p5_tog; /* 0x13c */ 843 u32 reg_core; /* 0x140 */ 844 u32 reg_core_set; /* 0x144 */ 845 u32 reg_core_clr; /* 0x148 */ 846 u32 reg_core_tog; /* 0x14c */ 847 u32 ana_misc0; /* 0x150 */ 848 u32 ana_misc0_set; /* 0x154 */ 849 u32 ana_misc0_clr; /* 0x158 */ 850 u32 ana_misc0_tog; /* 0x15c */ 851 u32 ana_misc1; /* 0x160 */ 852 u32 ana_misc1_set; /* 0x164 */ 853 u32 ana_misc1_clr; /* 0x168 */ 854 u32 ana_misc1_tog; /* 0x16c */ 855 u32 ana_misc2; /* 0x170 */ 856 u32 ana_misc2_set; /* 0x174 */ 857 u32 ana_misc2_clr; /* 0x178 */ 858 u32 ana_misc2_tog; /* 0x17c */ 859 u32 tempsense0; /* 0x180 */ 860 u32 tempsense0_set; /* 0x184 */ 861 u32 tempsense0_clr; /* 0x188 */ 862 u32 tempsense0_tog; /* 0x18c */ 863 u32 tempsense1; /* 0x190 */ 864 u32 tempsense1_set; /* 0x194 */ 865 u32 tempsense1_clr; /* 0x198 */ 866 u32 tempsense1_tog; /* 0x19c */ 867 u32 usb1_vbus_detect; /* 0x1a0 */ 868 u32 usb1_vbus_detect_set; /* 0x1a4 */ 869 u32 usb1_vbus_detect_clr; /* 0x1a8 */ 870 u32 usb1_vbus_detect_tog; /* 0x1ac */ 871 u32 usb1_chrg_detect; /* 0x1b0 */ 872 u32 usb1_chrg_detect_set; /* 0x1b4 */ 873 u32 usb1_chrg_detect_clr; /* 0x1b8 */ 874 u32 usb1_chrg_detect_tog; /* 0x1bc */ 875 u32 usb1_vbus_det_stat; /* 0x1c0 */ 876 u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 877 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 878 u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 879 u32 usb1_chrg_det_stat; /* 0x1d0 */ 880 u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 881 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 882 u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 883 u32 usb1_loopback; /* 0x1e0 */ 884 u32 usb1_loopback_set; /* 0x1e4 */ 885 u32 usb1_loopback_clr; /* 0x1e8 */ 886 u32 usb1_loopback_tog; /* 0x1ec */ 887 u32 usb1_misc; /* 0x1f0 */ 888 u32 usb1_misc_set; /* 0x1f4 */ 889 u32 usb1_misc_clr; /* 0x1f8 */ 890 u32 usb1_misc_tog; /* 0x1fc */ 891 u32 usb2_vbus_detect; /* 0x200 */ 892 u32 usb2_vbus_detect_set; /* 0x204 */ 893 u32 usb2_vbus_detect_clr; /* 0x208 */ 894 u32 usb2_vbus_detect_tog; /* 0x20c */ 895 u32 usb2_chrg_detect; /* 0x210 */ 896 u32 usb2_chrg_detect_set; /* 0x214 */ 897 u32 usb2_chrg_detect_clr; /* 0x218 */ 898 u32 usb2_chrg_detect_tog; /* 0x21c */ 899 u32 usb2_vbus_det_stat; /* 0x220 */ 900 u32 usb2_vbus_det_stat_set; /* 0x224 */ 901 u32 usb2_vbus_det_stat_clr; /* 0x228 */ 902 u32 usb2_vbus_det_stat_tog; /* 0x22c */ 903 u32 usb2_chrg_det_stat; /* 0x230 */ 904 u32 usb2_chrg_det_stat_set; /* 0x234 */ 905 u32 usb2_chrg_det_stat_clr; /* 0x238 */ 906 u32 usb2_chrg_det_stat_tog; /* 0x23c */ 907 u32 usb2_loopback; /* 0x240 */ 908 u32 usb2_loopback_set; /* 0x244 */ 909 u32 usb2_loopback_clr; /* 0x248 */ 910 u32 usb2_loopback_tog; /* 0x24c */ 911 u32 usb2_misc; /* 0x250 */ 912 u32 usb2_misc_set; /* 0x254 */ 913 u32 usb2_misc_clr; /* 0x258 */ 914 u32 usb2_misc_tog; /* 0x25c */ 915 u32 digprog; /* 0x260 */ 916 u32 reserved1[7]; 917 u32 digprog_sololite; /* 0x280 */ 918 }; 919 920 #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) 921 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) 922 #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) 923 #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) 924 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) 925 #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) 926 927 struct wdog_regs { 928 u16 wcr; /* Control */ 929 u16 wsr; /* Service */ 930 u16 wrsr; /* Reset Status */ 931 u16 wicr; /* Interrupt Control */ 932 u16 wmcr; /* Miscellaneous Control */ 933 }; 934 935 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) 936 #define PWMCR_DOZEEN (1 << 24) 937 #define PWMCR_WAITEN (1 << 23) 938 #define PWMCR_DBGEN (1 << 22) 939 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) 940 #define PWMCR_CLKSRC_IPG (1 << 16) 941 #define PWMCR_EN (1 << 0) 942 943 struct pwm_regs { 944 u32 cr; 945 u32 sr; 946 u32 ir; 947 u32 sar; 948 u32 pr; 949 u32 cnr; 950 }; 951 #endif /* __ASSEMBLER__*/ 952 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 953