1 /*
2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
9 
10 #define ARCH_MXC
11 
12 #ifdef CONFIG_MX6UL
13 #define CONFIG_SYS_CACHELINE_SIZE	64
14 #else
15 #define CONFIG_SYS_CACHELINE_SIZE	32
16 #endif
17 
18 #define ROMCP_ARB_BASE_ADDR             0x00000000
19 #define ROMCP_ARB_END_ADDR              0x000FFFFF
20 
21 #ifdef CONFIG_MX6SL
22 #define GPU_2D_ARB_BASE_ADDR            0x02200000
23 #define GPU_2D_ARB_END_ADDR             0x02203FFF
24 #define OPENVG_ARB_BASE_ADDR            0x02204000
25 #define OPENVG_ARB_END_ADDR             0x02207FFF
26 #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
27 #define CAAM_ARB_BASE_ADDR              0x00100000
28 #define CAAM_ARB_END_ADDR               0x00107FFF
29 #define GPU_ARB_BASE_ADDR               0x01800000
30 #define GPU_ARB_END_ADDR                0x01803FFF
31 #define APBH_DMA_ARB_BASE_ADDR          0x01804000
32 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
33 #define M4_BOOTROM_BASE_ADDR			0x007F8000
34 
35 #else
36 #define CAAM_ARB_BASE_ADDR              0x00100000
37 #define CAAM_ARB_END_ADDR               0x00103FFF
38 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
39 #define APBH_DMA_ARB_END_ADDR           0x00117FFF
40 #define HDMI_ARB_BASE_ADDR              0x00120000
41 #define HDMI_ARB_END_ADDR               0x00128FFF
42 #define GPU_3D_ARB_BASE_ADDR            0x00130000
43 #define GPU_3D_ARB_END_ADDR             0x00133FFF
44 #define GPU_2D_ARB_BASE_ADDR            0x00134000
45 #define GPU_2D_ARB_END_ADDR             0x00137FFF
46 #define DTCP_ARB_BASE_ADDR              0x00138000
47 #define DTCP_ARB_END_ADDR               0x0013BFFF
48 #endif	/* CONFIG_MX6SL */
49 
50 #define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
51 #define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
52 #define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
53 
54 /* GPV - PL301 configuration ports */
55 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
56 #define GPV2_BASE_ADDR                  0x00D00000
57 #else
58 #define GPV2_BASE_ADDR			0x00200000
59 #endif
60 
61 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
62 #define GPV3_BASE_ADDR			0x00E00000
63 #define GPV4_BASE_ADDR			0x00F00000
64 #define GPV5_BASE_ADDR			0x01000000
65 #define GPV6_BASE_ADDR			0x01100000
66 #define PCIE_ARB_BASE_ADDR              0x08000000
67 #define PCIE_ARB_END_ADDR               0x08FFFFFF
68 
69 #else
70 #define GPV3_BASE_ADDR			0x00300000
71 #define GPV4_BASE_ADDR			0x00800000
72 #define PCIE_ARB_BASE_ADDR              0x01000000
73 #define PCIE_ARB_END_ADDR               0x01FFFFFF
74 #endif
75 
76 #define IRAM_BASE_ADDR			0x00900000
77 #define SCU_BASE_ADDR                   0x00A00000
78 #define IC_INTERFACES_BASE_ADDR         0x00A00100
79 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
80 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
81 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
82 #define L2_PL310_BASE			0x00A02000
83 #define GPV0_BASE_ADDR                  0x00B00000
84 #define GPV1_BASE_ADDR                  0x00C00000
85 
86 #define AIPS1_ARB_BASE_ADDR             0x02000000
87 #define AIPS1_ARB_END_ADDR              0x020FFFFF
88 #define AIPS2_ARB_BASE_ADDR             0x02100000
89 #define AIPS2_ARB_END_ADDR              0x021FFFFF
90 /* AIPS3 only on i.MX6SX */
91 #define AIPS3_ARB_BASE_ADDR             0x02200000
92 #define AIPS3_ARB_END_ADDR              0x022FFFFF
93 #ifdef CONFIG_MX6SX
94 #define WEIM_ARB_BASE_ADDR              0x50000000
95 #define WEIM_ARB_END_ADDR               0x57FFFFFF
96 #define QSPI0_AMBA_BASE                0x60000000
97 #define QSPI0_AMBA_END                 0x6FFFFFFF
98 #define QSPI1_AMBA_BASE                0x70000000
99 #define QSPI1_AMBA_END                 0x7FFFFFFF
100 #elif defined(CONFIG_MX6UL)
101 #define WEIM_ARB_BASE_ADDR              0x50000000
102 #define WEIM_ARB_END_ADDR               0x57FFFFFF
103 #define QSPI0_AMBA_BASE                 0x60000000
104 #define QSPI0_AMBA_END                  0x6FFFFFFF
105 #else
106 #define SATA_ARB_BASE_ADDR              0x02200000
107 #define SATA_ARB_END_ADDR               0x02203FFF
108 #define OPENVG_ARB_BASE_ADDR            0x02204000
109 #define OPENVG_ARB_END_ADDR             0x02207FFF
110 #define HSI_ARB_BASE_ADDR               0x02208000
111 #define HSI_ARB_END_ADDR                0x0220BFFF
112 #define IPU1_ARB_BASE_ADDR              0x02400000
113 #define IPU1_ARB_END_ADDR               0x027FFFFF
114 #define IPU2_ARB_BASE_ADDR              0x02800000
115 #define IPU2_ARB_END_ADDR               0x02BFFFFF
116 #define WEIM_ARB_BASE_ADDR              0x08000000
117 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
118 #endif
119 
120 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
121 #define MMDC0_ARB_BASE_ADDR             0x80000000
122 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
123 #define MMDC1_ARB_BASE_ADDR             0xC0000000
124 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
125 #else
126 #define MMDC0_ARB_BASE_ADDR             0x10000000
127 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
128 #define MMDC1_ARB_BASE_ADDR             0x80000000
129 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
130 #endif
131 
132 #ifndef CONFIG_MX6SX
133 #define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
134 #define IPU_SOC_OFFSET			0x00200000
135 #endif
136 
137 /* Defines for Blocks connected via AIPS (SkyBlue) */
138 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
139 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
140 #define ATZ3_BASE_ADDR              AIPS3_ARB_BASE_ADDR
141 #define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
142 #define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
143 #define AIPS3_BASE_ADDR             AIPS3_ON_BASE_ADDR
144 
145 #define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
146 #define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
147 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
148 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
149 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
150 #ifdef CONFIG_MX6SL
151 #define UART5_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x18000)
152 #define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
153 #define UART2_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x24000)
154 #define SSI1_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x28000)
155 #define SSI2_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x2C000)
156 #define SSI3_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x30000)
157 #define UART3_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x34000)
158 #define UART4_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x38000)
159 #else
160 #ifndef CONFIG_MX6SX
161 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
162 #endif
163 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
164 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
165 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
166 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
167 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
168 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
169 #endif
170 
171 #ifndef CONFIG_MX6SX
172 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
173 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
174 #endif
175 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
176 
177 #define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
178 #define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
179 #define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
180 #define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
181 #define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
182 #define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
183 #define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
184 #define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
185 #define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
186 #define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
187 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
188 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
189 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
190 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
191 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
192 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
193 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
194 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
195 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
196 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
197 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
198 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
199 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
200 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
201 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
202 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
203 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
204 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
205 #ifdef CONFIG_MX6SL
206 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
207 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
208 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
209 #elif CONFIG_MX6SX
210 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
211 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
212 #define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)
213 #define SEMAPHORE1_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x74000)
214 #define SEMAPHORE2_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x78000)
215 #define RDC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
216 #else
217 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
218 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
219 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
220 #endif
221 
222 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
223 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
224 #define AIPS3_ON_BASE_ADDR          (ATZ3_BASE_ADDR + 0x7C000)
225 #define AIPS3_OFF_BASE_ADDR         (ATZ3_BASE_ADDR + 0x80000)
226 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
227 #define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
228 
229 #define CONFIG_SYS_FSL_SEC_ADDR     CAAM_BASE_ADDR
230 #define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + 0x1000)
231 
232 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
233 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
234 
235 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
236 #ifdef CONFIG_MX6SL
237 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
238 #else
239 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
240 #endif
241 
242 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
243 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
244 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
245 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
246 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
247 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
248 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
249 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
250 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
251 /* i.MX6SL */
252 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
253 #ifdef CONFIG_MX6UL
254 #define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
255 #else
256 /* i.MX6SX */
257 #define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
258 #endif
259 /* i.MX6DQ/SDL */
260 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
261 
262 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
263 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
264 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
265 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
266 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
267 #define MX6UL_LCDIF1_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x48000)
268 #ifdef CONFIG_MX6SX
269 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
270 #else
271 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
272 #endif
273 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
274 #ifdef CONFIG_MX6UL
275 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
276 #elif defined(CONFIG_MX6SX)
277 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
278 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
279 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
280 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
281 #define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
282 #else
283 #define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
284 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
285 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
286 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
287 #endif
288 #define MX6UL_WDOG3_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x64000)
289 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
290 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
291 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
292 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
293 #define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
294 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
295 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
296 
297 #ifdef CONFIG_MX6SX
298 #define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
299 #define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
300 #define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)
301 #define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
302 #define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
303 #define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
304 #define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
305 #define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
306 #define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
307 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
308 #define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
309 #define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
310 #define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
311 #define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
312 #define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
313 #define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
314 #define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
315 #define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
316 #define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
317 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
318 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
319 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
320 #endif
321 /* Only for i.MX6SX */
322 #define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
323 #define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
324 #define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
325 
326 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
327 #define IRAM_SIZE                    0x00040000
328 #else
329 #define IRAM_SIZE                    0x00020000
330 #endif
331 #define FEC_QUIRK_ENET_MAC
332 
333 #include <asm/imx-common/regs-lcdif.h>
334 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
335 #include <asm/types.h>
336 
337 /* only for i.MX6SX/UL */
338 #define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ?	\
339 			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR))
340 #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ?	\
341 			  MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)
342 
343 
344 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
345 
346 #define SRC_SCR_CORE_1_RESET_OFFSET     14
347 #define SRC_SCR_CORE_1_RESET_MASK       (1<<SRC_SCR_CORE_1_RESET_OFFSET)
348 #define SRC_SCR_CORE_2_RESET_OFFSET     15
349 #define SRC_SCR_CORE_2_RESET_MASK       (1<<SRC_SCR_CORE_2_RESET_OFFSET)
350 #define SRC_SCR_CORE_3_RESET_OFFSET     16
351 #define SRC_SCR_CORE_3_RESET_MASK       (1<<SRC_SCR_CORE_3_RESET_OFFSET)
352 #define SRC_SCR_CORE_1_ENABLE_OFFSET    22
353 #define SRC_SCR_CORE_1_ENABLE_MASK      (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
354 #define SRC_SCR_CORE_2_ENABLE_OFFSET    23
355 #define SRC_SCR_CORE_2_ENABLE_MASK      (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
356 #define SRC_SCR_CORE_3_ENABLE_OFFSET    24
357 #define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
358 
359 struct rdc_regs {
360 	u32	vir;		/* Version information */
361 	u32	reserved1[8];
362 	u32	stat;		/* Status */
363 	u32	intctrl;	/* Interrupt and Control */
364 	u32	intstat;	/* Interrupt Status */
365 	u32	reserved2[116];
366 	u32	mda[32];	/* Master Domain Assignment */
367 	u32	reserved3[96];
368 	u32	pdap[104];	/* Peripheral Domain Access Permissions */
369 	u32	reserved4[88];
370 	struct {
371 		u32 mrsa;	/* Memory Region Start Address */
372 		u32 mrea;	/* Memory Region End Address */
373 		u32 mrc;	/* Memory Region Control */
374 		u32 mrvs;	/* Memory Region Violation Status */
375 	} mem_region[55];
376 };
377 
378 struct rdc_sema_regs {
379 	u8	gate[64];	/* Gate */
380 	u16	rstgt;		/* Reset Gate */
381 };
382 
383 /* WEIM registers */
384 struct weim {
385 	u32 cs0gcr1;
386 	u32 cs0gcr2;
387 	u32 cs0rcr1;
388 	u32 cs0rcr2;
389 	u32 cs0wcr1;
390 	u32 cs0wcr2;
391 
392 	u32 cs1gcr1;
393 	u32 cs1gcr2;
394 	u32 cs1rcr1;
395 	u32 cs1rcr2;
396 	u32 cs1wcr1;
397 	u32 cs1wcr2;
398 
399 	u32 cs2gcr1;
400 	u32 cs2gcr2;
401 	u32 cs2rcr1;
402 	u32 cs2rcr2;
403 	u32 cs2wcr1;
404 	u32 cs2wcr2;
405 
406 	u32 cs3gcr1;
407 	u32 cs3gcr2;
408 	u32 cs3rcr1;
409 	u32 cs3rcr2;
410 	u32 cs3wcr1;
411 	u32 cs3wcr2;
412 
413 	u32 unused[12];
414 
415 	u32 wcr;
416 	u32 wiar;
417 	u32 ear;
418 };
419 
420 /* System Reset Controller (SRC) */
421 struct src {
422 	u32	scr;
423 	u32	sbmr1;
424 	u32	srsr;
425 	u32	reserved1[2];
426 	u32	sisr;
427 	u32	simr;
428 	u32     sbmr2;
429 	u32     gpr1;
430 	u32     gpr2;
431 	u32     gpr3;
432 	u32     gpr4;
433 	u32     gpr5;
434 	u32     gpr6;
435 	u32     gpr7;
436 	u32     gpr8;
437 	u32     gpr9;
438 	u32     gpr10;
439 };
440 
441 #define SRC_SCR_M4_ENABLE_OFFSET                22
442 #define SRC_SCR_M4_ENABLE_MASK                  (1 << 22)
443 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET         4
444 #define SRC_SCR_M4C_NON_SCLR_RST_MASK           (1 << 4)
445 
446 /* GPR1 bitfields */
447 #define IOMUXC_GPR1_APP_CLK_REQ_N		BIT(30)
448 #define IOMUXC_GPR1_PCIE_EXIT_L1		BIT(28)
449 #define IOMUXC_GPR1_PCIE_RDY_L23		BIT(27)
450 #define IOMUXC_GPR1_PCIE_ENTER_L1		BIT(26)
451 #define IOMUXC_GPR1_MIPI_COLOR_SW		BIT(25)
452 #define IOMUXC_GPR1_DPI_OFF			BIT(24)
453 #define IOMUXC_GPR1_EXC_MON_SLVE		BIT(22)
454 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET		21
455 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK		(1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
456 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(20)
457 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(19)
458 #define IOMUXC_GPR1_PCIE_TEST_PD			BIT(18)
459 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2		BIT(17)
460 #define IOMUXC_GPR1_PCIE_REF_CLK_EN		BIT(16)
461 #define IOMUXC_GPR1_USB_EXP_MODE			BIT(15)
462 #define IOMUXC_GPR1_PCIE_INT			BIT(14)
463 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET		13
464 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK		(1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
465 #define IOMUXC_GPR1_GINT				BIT(12)
466 #define IOMUXC_GPR1_ADDRS3_MASK			(0x3 << 10)
467 #define IOMUXC_GPR1_ADDRS3_32MB			(0x0 << 10)
468 #define IOMUXC_GPR1_ADDRS3_64MB			(0x1 << 10)
469 #define IOMUXC_GPR1_ADDRS3_128MB			(0x2 << 10)
470 #define IOMUXC_GPR1_ACT_CS3			BIT(9)
471 #define IOMUXC_GPR1_ADDRS2_MASK			(0x3 << 7)
472 #define IOMUXC_GPR1_ACT_CS2			BIT(6)
473 #define IOMUXC_GPR1_ADDRS1_MASK			(0x3 << 4)
474 #define IOMUXC_GPR1_ACT_CS1			BIT(3)
475 #define IOMUXC_GPR1_ADDRS0_OFFSET		(1)
476 #define IOMUXC_GPR1_ADDRS0_MASK			(0x3 << 1)
477 #define IOMUXC_GPR1_ACT_CS0			BIT(0)
478 
479 /* GPR3 bitfields */
480 #define IOMUXC_GPR3_GPU_DBG_OFFSET		29
481 #define IOMUXC_GPR3_GPU_DBG_MASK		(3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
482 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET	28
483 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
484 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET	27
485 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
486 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET	26
487 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
488 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET	25
489 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
490 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET		21
491 #define IOMUXC_GPR3_OCRAM_CTL_MASK		(0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
492 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET		17
493 #define IOMUXC_GPR3_OCRAM_STATUS_MASK		(0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
494 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET	16
495 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
496 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET	15
497 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
498 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET	14
499 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
500 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET	13
501 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
502 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET	12
503 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
504 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET	11
505 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
506 #define IOMUXC_GPR3_IPU_DIAG_OFFSET		10
507 #define IOMUXC_GPR3_IPU_DIAG_MASK		(1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
508 
509 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0	0
510 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1	1
511 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0	2
512 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1	3
513 
514 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET	8
515 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
516 
517 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET	6
518 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
519 
520 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET		4
521 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
522 
523 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET		2
524 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
525 
526 /* gpr12 bitfields */
527 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN		BIT(27)
528 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN		BIT(26)
529 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN		BIT(25)
530 #define IOMUXC_GPR12_ARMP_APB_CLK_EN		BIT(24)
531 #define IOMUXC_GPR12_DEVICE_TYPE		(0xf << 12)
532 #define IOMUXC_GPR12_PCIE_CTL_2			BIT(10)
533 #define IOMUXC_GPR12_LOS_LEVEL			(0x1f << 4)
534 
535 struct iomuxc {
536 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
537 	u8 reserved[0x4000];
538 #endif
539 	u32 gpr[14];
540 };
541 
542 struct gpc {
543 	u32	cntr;
544 	u32	pgr;
545 	u32	imr1;
546 	u32	imr2;
547 	u32	imr3;
548 	u32	imr4;
549 	u32	isr1;
550 	u32	isr2;
551 	u32	isr3;
552 	u32	isr4;
553 };
554 
555 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
556 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
557 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16
558 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK			(7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
559 
560 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET			15
561 #define IOMUXC_GPR2_BGREF_RRMODE_MASK			(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
562 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES		(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
563 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES		(0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
564 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH	0
565 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW	1
566 
567 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET		10
568 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
569 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
570 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
571 
572 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET		9
573 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
574 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
575 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
576 
577 #define IOMUXC_GPR2_BITMAP_SPWG	0
578 #define IOMUXC_GPR2_BITMAP_JEIDA	1
579 
580 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET		8
581 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
582 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
583 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
584 
585 #define IOMUXC_GPR2_DATA_WIDTH_18	0
586 #define IOMUXC_GPR2_DATA_WIDTH_24	1
587 
588 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET		7
589 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
590 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
591 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
592 
593 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET		6
594 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
595 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
596 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
597 
598 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET		5
599 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
600 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
601 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
602 
603 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET		4
604 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK			(1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
605 
606 #define IOMUXC_GPR2_MODE_DISABLED	0
607 #define IOMUXC_GPR2_MODE_ENABLED_DI0	1
608 #define IOMUXC_GPR2_MODE_ENABLED_DI1	3
609 
610 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET		2
611 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
612 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
613 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
614 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
615 
616 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET		0
617 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
618 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
619 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
620 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
621 
622 /* ECSPI registers */
623 struct cspi_regs {
624 	u32 rxdata;
625 	u32 txdata;
626 	u32 ctrl;
627 	u32 cfg;
628 	u32 intr;
629 	u32 dma;
630 	u32 stat;
631 	u32 period;
632 };
633 
634 /*
635  * CSPI register definitions
636  */
637 #define MXC_ECSPI
638 #define MXC_CSPICTRL_EN		(1 << 0)
639 #define MXC_CSPICTRL_MODE	(1 << 1)
640 #define MXC_CSPICTRL_XCH	(1 << 2)
641 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
642 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
643 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
644 #define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
645 #define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
646 #define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
647 #define MXC_CSPICTRL_MAXBITS	0xfff
648 #define MXC_CSPICTRL_TC		(1 << 7)
649 #define MXC_CSPICTRL_RXOVF	(1 << 6)
650 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
651 #define MAX_SPI_BYTES	32
652 #define SPI_MAX_NUM	4
653 
654 /* Bit position inside CTRL register to be associated with SS */
655 #define MXC_CSPICTRL_CHAN	18
656 
657 /* Bit position inside CON register to be associated with SS */
658 #define MXC_CSPICON_PHA		0  /* SCLK phase control */
659 #define MXC_CSPICON_POL		4  /* SCLK polarity */
660 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
661 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
662 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
663 #define MXC_SPI_BASE_ADDRESSES \
664 	ECSPI1_BASE_ADDR, \
665 	ECSPI2_BASE_ADDR, \
666 	ECSPI3_BASE_ADDR, \
667 	ECSPI4_BASE_ADDR
668 #else
669 #define MXC_SPI_BASE_ADDRESSES \
670 	ECSPI1_BASE_ADDR, \
671 	ECSPI2_BASE_ADDR, \
672 	ECSPI3_BASE_ADDR, \
673 	ECSPI4_BASE_ADDR, \
674 	ECSPI5_BASE_ADDR
675 #endif
676 
677 struct ocotp_regs {
678 	u32	ctrl;
679 	u32	ctrl_set;
680 	u32     ctrl_clr;
681 	u32	ctrl_tog;
682 	u32	timing;
683 	u32     rsvd0[3];
684 	u32     data;
685 	u32     rsvd1[3];
686 	u32     read_ctrl;
687 	u32     rsvd2[3];
688 	u32	read_fuse_data;
689 	u32     rsvd3[3];
690 	u32	sw_sticky;
691 	u32     rsvd4[3];
692 	u32     scs;
693 	u32     scs_set;
694 	u32     scs_clr;
695 	u32     scs_tog;
696 	u32     crc_addr;
697 	u32     rsvd5[3];
698 	u32     crc_value;
699 	u32     rsvd6[3];
700 	u32     version;
701 	u32     rsvd7[0xdb];
702 
703 	/* fuse banks */
704 	struct fuse_bank {
705 		u32	fuse_regs[0x20];
706 	} bank[0];
707 };
708 
709 struct fuse_bank0_regs {
710 	u32	lock;
711 	u32	rsvd0[3];
712 	u32	uid_low;
713 	u32	rsvd1[3];
714 	u32	uid_high;
715 	u32	rsvd2[3];
716 	u32	cfg2;
717 	u32	rsvd3[3];
718 	u32	cfg3;
719 	u32	rsvd4[3];
720 	u32	cfg4;
721 	u32	rsvd5[3];
722 	u32	cfg5;
723 	u32	rsvd6[3];
724 	u32	cfg6;
725 	u32	rsvd7[3];
726 };
727 
728 struct fuse_bank1_regs {
729 	u32	mem0;
730 	u32	rsvd0[3];
731 	u32	mem1;
732 	u32	rsvd1[3];
733 	u32	mem2;
734 	u32	rsvd2[3];
735 	u32	mem3;
736 	u32	rsvd3[3];
737 	u32	mem4;
738 	u32	rsvd4[3];
739 	u32	ana0;
740 	u32	rsvd5[3];
741 	u32	ana1;
742 	u32	rsvd6[3];
743 	u32	ana2;
744 	u32	rsvd7[3];
745 };
746 
747 struct fuse_bank4_regs {
748 	u32 sjc_resp_low;
749 	u32 rsvd0[3];
750 	u32 sjc_resp_high;
751 	u32 rsvd1[3];
752 	u32 mac_addr0;
753 	u32 rsvd2[3];
754 	u32 mac_addr1;
755 	u32 rsvd3[3];
756 	u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
757 	u32 rsvd4[7];
758 	u32 gp1;
759 	u32 rsvd5[3];
760 	u32 gp2;
761 	u32 rsvd6[3];
762 };
763 
764 struct aipstz_regs {
765 	u32	mprot0;
766 	u32	mprot1;
767 	u32	rsvd[0xe];
768 	u32	opacr0;
769 	u32	opacr1;
770 	u32	opacr2;
771 	u32	opacr3;
772 	u32	opacr4;
773 };
774 
775 struct anatop_regs {
776 	u32	pll_sys;		/* 0x000 */
777 	u32	pll_sys_set;		/* 0x004 */
778 	u32	pll_sys_clr;		/* 0x008 */
779 	u32	pll_sys_tog;		/* 0x00c */
780 	u32	usb1_pll_480_ctrl;	/* 0x010 */
781 	u32	usb1_pll_480_ctrl_set;	/* 0x014 */
782 	u32	usb1_pll_480_ctrl_clr;	/* 0x018 */
783 	u32	usb1_pll_480_ctrl_tog;	/* 0x01c */
784 	u32	usb2_pll_480_ctrl;	/* 0x020 */
785 	u32	usb2_pll_480_ctrl_set;	/* 0x024 */
786 	u32	usb2_pll_480_ctrl_clr;	/* 0x028 */
787 	u32	usb2_pll_480_ctrl_tog;	/* 0x02c */
788 	u32	pll_528;		/* 0x030 */
789 	u32	pll_528_set;		/* 0x034 */
790 	u32	pll_528_clr;		/* 0x038 */
791 	u32	pll_528_tog;		/* 0x03c */
792 	u32	pll_528_ss;		/* 0x040 */
793 	u32	rsvd0[3];
794 	u32	pll_528_num;		/* 0x050 */
795 	u32	rsvd1[3];
796 	u32	pll_528_denom;		/* 0x060 */
797 	u32	rsvd2[3];
798 	u32	pll_audio;		/* 0x070 */
799 	u32	pll_audio_set;		/* 0x074 */
800 	u32	pll_audio_clr;		/* 0x078 */
801 	u32	pll_audio_tog;		/* 0x07c */
802 	u32	pll_audio_num;		/* 0x080 */
803 	u32	rsvd3[3];
804 	u32	pll_audio_denom;	/* 0x090 */
805 	u32	rsvd4[3];
806 	u32	pll_video;		/* 0x0a0 */
807 	u32	pll_video_set;		/* 0x0a4 */
808 	u32	pll_video_clr;		/* 0x0a8 */
809 	u32	pll_video_tog;		/* 0x0ac */
810 	u32	pll_video_num;		/* 0x0b0 */
811 	u32	rsvd5[3];
812 	u32	pll_video_denom;	/* 0x0c0 */
813 	u32	rsvd6[3];
814 	u32	pll_mlb;		/* 0x0d0 */
815 	u32	pll_mlb_set;		/* 0x0d4 */
816 	u32	pll_mlb_clr;		/* 0x0d8 */
817 	u32	pll_mlb_tog;		/* 0x0dc */
818 	u32	pll_enet;		/* 0x0e0 */
819 	u32	pll_enet_set;		/* 0x0e4 */
820 	u32	pll_enet_clr;		/* 0x0e8 */
821 	u32	pll_enet_tog;		/* 0x0ec */
822 	u32	pfd_480;		/* 0x0f0 */
823 	u32	pfd_480_set;		/* 0x0f4 */
824 	u32	pfd_480_clr;		/* 0x0f8 */
825 	u32	pfd_480_tog;		/* 0x0fc */
826 	u32	pfd_528;		/* 0x100 */
827 	u32	pfd_528_set;		/* 0x104 */
828 	u32	pfd_528_clr;		/* 0x108 */
829 	u32	pfd_528_tog;		/* 0x10c */
830 	u32	reg_1p1;		/* 0x110 */
831 	u32	reg_1p1_set;		/* 0x114 */
832 	u32	reg_1p1_clr;		/* 0x118 */
833 	u32	reg_1p1_tog;		/* 0x11c */
834 	u32	reg_3p0;		/* 0x120 */
835 	u32	reg_3p0_set;		/* 0x124 */
836 	u32	reg_3p0_clr;		/* 0x128 */
837 	u32	reg_3p0_tog;		/* 0x12c */
838 	u32	reg_2p5;		/* 0x130 */
839 	u32	reg_2p5_set;		/* 0x134 */
840 	u32	reg_2p5_clr;		/* 0x138 */
841 	u32	reg_2p5_tog;		/* 0x13c */
842 	u32	reg_core;		/* 0x140 */
843 	u32	reg_core_set;		/* 0x144 */
844 	u32	reg_core_clr;		/* 0x148 */
845 	u32	reg_core_tog;		/* 0x14c */
846 	u32	ana_misc0;		/* 0x150 */
847 	u32	ana_misc0_set;		/* 0x154 */
848 	u32	ana_misc0_clr;		/* 0x158 */
849 	u32	ana_misc0_tog;		/* 0x15c */
850 	u32	ana_misc1;		/* 0x160 */
851 	u32	ana_misc1_set;		/* 0x164 */
852 	u32	ana_misc1_clr;		/* 0x168 */
853 	u32	ana_misc1_tog;		/* 0x16c */
854 	u32	ana_misc2;		/* 0x170 */
855 	u32	ana_misc2_set;		/* 0x174 */
856 	u32	ana_misc2_clr;		/* 0x178 */
857 	u32	ana_misc2_tog;		/* 0x17c */
858 	u32	tempsense0;		/* 0x180 */
859 	u32	tempsense0_set;		/* 0x184 */
860 	u32	tempsense0_clr;		/* 0x188 */
861 	u32	tempsense0_tog;		/* 0x18c */
862 	u32	tempsense1;		/* 0x190 */
863 	u32	tempsense1_set;		/* 0x194 */
864 	u32	tempsense1_clr;		/* 0x198 */
865 	u32	tempsense1_tog;		/* 0x19c */
866 	u32	usb1_vbus_detect;	/* 0x1a0 */
867 	u32	usb1_vbus_detect_set;	/* 0x1a4 */
868 	u32	usb1_vbus_detect_clr;	/* 0x1a8 */
869 	u32	usb1_vbus_detect_tog;	/* 0x1ac */
870 	u32	usb1_chrg_detect;	/* 0x1b0 */
871 	u32	usb1_chrg_detect_set;	/* 0x1b4 */
872 	u32	usb1_chrg_detect_clr;	/* 0x1b8 */
873 	u32	usb1_chrg_detect_tog;	/* 0x1bc */
874 	u32	usb1_vbus_det_stat;	/* 0x1c0 */
875 	u32	usb1_vbus_det_stat_set;	/* 0x1c4 */
876 	u32	usb1_vbus_det_stat_clr;	/* 0x1c8 */
877 	u32	usb1_vbus_det_stat_tog;	/* 0x1cc */
878 	u32	usb1_chrg_det_stat;	/* 0x1d0 */
879 	u32	usb1_chrg_det_stat_set;	/* 0x1d4 */
880 	u32	usb1_chrg_det_stat_clr;	/* 0x1d8 */
881 	u32	usb1_chrg_det_stat_tog;	/* 0x1dc */
882 	u32	usb1_loopback;		/* 0x1e0 */
883 	u32	usb1_loopback_set;	/* 0x1e4 */
884 	u32	usb1_loopback_clr;	/* 0x1e8 */
885 	u32	usb1_loopback_tog;	/* 0x1ec */
886 	u32	usb1_misc;		/* 0x1f0 */
887 	u32	usb1_misc_set;		/* 0x1f4 */
888 	u32	usb1_misc_clr;		/* 0x1f8 */
889 	u32	usb1_misc_tog;		/* 0x1fc */
890 	u32	usb2_vbus_detect;	/* 0x200 */
891 	u32	usb2_vbus_detect_set;	/* 0x204 */
892 	u32	usb2_vbus_detect_clr;	/* 0x208 */
893 	u32	usb2_vbus_detect_tog;	/* 0x20c */
894 	u32	usb2_chrg_detect;	/* 0x210 */
895 	u32	usb2_chrg_detect_set;	/* 0x214 */
896 	u32	usb2_chrg_detect_clr;	/* 0x218 */
897 	u32	usb2_chrg_detect_tog;	/* 0x21c */
898 	u32	usb2_vbus_det_stat;	/* 0x220 */
899 	u32	usb2_vbus_det_stat_set;	/* 0x224 */
900 	u32	usb2_vbus_det_stat_clr;	/* 0x228 */
901 	u32	usb2_vbus_det_stat_tog;	/* 0x22c */
902 	u32	usb2_chrg_det_stat;	/* 0x230 */
903 	u32	usb2_chrg_det_stat_set;	/* 0x234 */
904 	u32	usb2_chrg_det_stat_clr;	/* 0x238 */
905 	u32	usb2_chrg_det_stat_tog;	/* 0x23c */
906 	u32	usb2_loopback;		/* 0x240 */
907 	u32	usb2_loopback_set;	/* 0x244 */
908 	u32	usb2_loopback_clr;	/* 0x248 */
909 	u32	usb2_loopback_tog;	/* 0x24c */
910 	u32	usb2_misc;		/* 0x250 */
911 	u32	usb2_misc_set;		/* 0x254 */
912 	u32	usb2_misc_clr;		/* 0x258 */
913 	u32	usb2_misc_tog;		/* 0x25c */
914 	u32	digprog;		/* 0x260 */
915 	u32	reserved1[7];
916 	u32	digprog_sololite;	/* 0x280 */
917 };
918 
919 #define ANATOP_PFD_FRAC_SHIFT(n)	((n)*8)
920 #define ANATOP_PFD_FRAC_MASK(n)	(0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
921 #define ANATOP_PFD_STABLE_SHIFT(n)	(6+((n)*8))
922 #define ANATOP_PFD_STABLE_MASK(n)	(1<<ANATOP_PFD_STABLE_SHIFT(n))
923 #define ANATOP_PFD_CLKGATE_SHIFT(n)	(7+((n)*8))
924 #define ANATOP_PFD_CLKGATE_MASK(n)	(1<<ANATOP_PFD_CLKGATE_SHIFT(n))
925 
926 struct wdog_regs {
927 	u16	wcr;	/* Control */
928 	u16	wsr;	/* Service */
929 	u16	wrsr;	/* Reset Status */
930 	u16	wicr;	/* Interrupt Control */
931 	u16	wmcr;	/* Miscellaneous Control */
932 };
933 
934 #define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
935 #define PWMCR_DOZEEN		(1 << 24)
936 #define PWMCR_WAITEN		(1 << 23)
937 #define PWMCR_DBGEN		(1 << 22)
938 #define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
939 #define PWMCR_CLKSRC_IPG	(1 << 16)
940 #define PWMCR_EN		(1 << 0)
941 
942 struct pwm_regs {
943 	u32	cr;
944 	u32	sr;
945 	u32	ir;
946 	u32	sar;
947 	u32	pr;
948 	u32	cnr;
949 };
950 #endif /* __ASSEMBLER__*/
951 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
952