123608e23SJason Liu /* 223608e23SJason Liu * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 323608e23SJason Liu * 423608e23SJason Liu * This program is free software; you can redistribute it and/or modify 523608e23SJason Liu * it under the terms of the GNU General Public License as published by 623608e23SJason Liu * the Free Software Foundation; either version 2 of the License, or 723608e23SJason Liu * (at your option) any later version. 823608e23SJason Liu 923608e23SJason Liu * This program is distributed in the hope that it will be useful, 1023608e23SJason Liu * but WITHOUT ANY WARRANTY; without even the implied warranty of 1123608e23SJason Liu * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1223608e23SJason Liu * GNU General Public License for more details. 1323608e23SJason Liu 1423608e23SJason Liu * You should have received a copy of the GNU General Public License along 1523608e23SJason Liu * with this program; if not, write to the Free Software Foundation, Inc., 1623608e23SJason Liu * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 1723608e23SJason Liu */ 1823608e23SJason Liu 1923608e23SJason Liu #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 2023608e23SJason Liu #define __ASM_ARCH_MX6_IMX_REGS_H__ 2123608e23SJason Liu 22*c415919dSEric Nelson #define CONFIG_SYS_CACHELINE_SIZE 32 23*c415919dSEric Nelson 2423608e23SJason Liu #define ROMCP_ARB_BASE_ADDR 0x00000000 2523608e23SJason Liu #define ROMCP_ARB_END_ADDR 0x000FFFFF 2623608e23SJason Liu #define CAAM_ARB_BASE_ADDR 0x00100000 2723608e23SJason Liu #define CAAM_ARB_END_ADDR 0x00103FFF 2823608e23SJason Liu #define APBH_DMA_ARB_BASE_ADDR 0x00110000 2923608e23SJason Liu #define APBH_DMA_ARB_END_ADDR 0x00117FFF 3023608e23SJason Liu #define HDMI_ARB_BASE_ADDR 0x00120000 3123608e23SJason Liu #define HDMI_ARB_END_ADDR 0x00128FFF 3223608e23SJason Liu #define GPU_3D_ARB_BASE_ADDR 0x00130000 3323608e23SJason Liu #define GPU_3D_ARB_END_ADDR 0x00133FFF 3423608e23SJason Liu #define GPU_2D_ARB_BASE_ADDR 0x00134000 3523608e23SJason Liu #define GPU_2D_ARB_END_ADDR 0x00137FFF 3623608e23SJason Liu #define DTCP_ARB_BASE_ADDR 0x00138000 3723608e23SJason Liu #define DTCP_ARB_END_ADDR 0x0013BFFF 3823608e23SJason Liu 3923608e23SJason Liu /* GPV - PL301 configuration ports */ 4023608e23SJason Liu #define GPV2_BASE_ADDR 0x00200000 4123608e23SJason Liu #define GPV3_BASE_ADDR 0x00300000 4223608e23SJason Liu #define GPV4_BASE_ADDR 0x00800000 4323608e23SJason Liu #define IRAM_BASE_ADDR 0x00900000 4423608e23SJason Liu #define SCU_BASE_ADDR 0x00A00000 4523608e23SJason Liu #define IC_INTERFACES_BASE_ADDR 0x00A00100 4623608e23SJason Liu #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 4723608e23SJason Liu #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 4823608e23SJason Liu #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 4923608e23SJason Liu #define GPV0_BASE_ADDR 0x00B00000 5023608e23SJason Liu #define GPV1_BASE_ADDR 0x00C00000 5123608e23SJason Liu #define PCIE_ARB_BASE_ADDR 0x01000000 5223608e23SJason Liu #define PCIE_ARB_END_ADDR 0x01FFFFFF 5323608e23SJason Liu 5423608e23SJason Liu #define AIPS1_ARB_BASE_ADDR 0x02000000 5523608e23SJason Liu #define AIPS1_ARB_END_ADDR 0x020FFFFF 5623608e23SJason Liu #define AIPS2_ARB_BASE_ADDR 0x02100000 5723608e23SJason Liu #define AIPS2_ARB_END_ADDR 0x021FFFFF 5823608e23SJason Liu #define SATA_ARB_BASE_ADDR 0x02200000 5923608e23SJason Liu #define SATA_ARB_END_ADDR 0x02203FFF 6023608e23SJason Liu #define OPENVG_ARB_BASE_ADDR 0x02204000 6123608e23SJason Liu #define OPENVG_ARB_END_ADDR 0x02207FFF 6223608e23SJason Liu #define HSI_ARB_BASE_ADDR 0x02208000 6323608e23SJason Liu #define HSI_ARB_END_ADDR 0x0220BFFF 6423608e23SJason Liu #define IPU1_ARB_BASE_ADDR 0x02400000 6523608e23SJason Liu #define IPU1_ARB_END_ADDR 0x027FFFFF 6623608e23SJason Liu #define IPU2_ARB_BASE_ADDR 0x02800000 6723608e23SJason Liu #define IPU2_ARB_END_ADDR 0x02BFFFFF 6823608e23SJason Liu #define WEIM_ARB_BASE_ADDR 0x08000000 6923608e23SJason Liu #define WEIM_ARB_END_ADDR 0x0FFFFFFF 7023608e23SJason Liu 7123608e23SJason Liu #define MMDC0_ARB_BASE_ADDR 0x10000000 7223608e23SJason Liu #define MMDC0_ARB_END_ADDR 0x7FFFFFFF 7323608e23SJason Liu #define MMDC1_ARB_BASE_ADDR 0x80000000 7423608e23SJason Liu #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 7523608e23SJason Liu 7623608e23SJason Liu /* Defines for Blocks connected via AIPS (SkyBlue) */ 7723608e23SJason Liu #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 7823608e23SJason Liu #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 7923608e23SJason Liu #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 8023608e23SJason Liu #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 8123608e23SJason Liu 8223608e23SJason Liu #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 8323608e23SJason Liu #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 8423608e23SJason Liu #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 8523608e23SJason Liu #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 8623608e23SJason Liu #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 8723608e23SJason Liu #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 8823608e23SJason Liu #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 8923608e23SJason Liu #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 9023608e23SJason Liu #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 9123608e23SJason Liu #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 9223608e23SJason Liu #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 9323608e23SJason Liu #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 9423608e23SJason Liu #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 9523608e23SJason Liu #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 9623608e23SJason Liu #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 9723608e23SJason Liu 9823608e23SJason Liu #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 9923608e23SJason Liu #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 10023608e23SJason Liu #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 10123608e23SJason Liu #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 10223608e23SJason Liu #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 10323608e23SJason Liu #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 10423608e23SJason Liu #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 10523608e23SJason Liu #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 10623608e23SJason Liu #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 10723608e23SJason Liu #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 10823608e23SJason Liu #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 10923608e23SJason Liu #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 11023608e23SJason Liu #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 11123608e23SJason Liu #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 11223608e23SJason Liu #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 11323608e23SJason Liu #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 11423608e23SJason Liu #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 11523608e23SJason Liu #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 1163f467529SWolfgang Grandegger #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 1173f467529SWolfgang Grandegger #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 1183f467529SWolfgang Grandegger #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 11923608e23SJason Liu #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 12023608e23SJason Liu #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 12123608e23SJason Liu #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 12223608e23SJason Liu #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 12323608e23SJason Liu #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 12423608e23SJason Liu #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 12523608e23SJason Liu #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 12623608e23SJason Liu #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 12723608e23SJason Liu #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 12823608e23SJason Liu #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 12923608e23SJason Liu 13023608e23SJason Liu #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 13123608e23SJason Liu #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 13223608e23SJason Liu #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 13323608e23SJason Liu #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 13423608e23SJason Liu #define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 13523608e23SJason Liu #define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 13623608e23SJason Liu #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 13723608e23SJason Liu #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 13823608e23SJason Liu #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 13923608e23SJason Liu #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 14023608e23SJason Liu #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 14123608e23SJason Liu #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 14223608e23SJason Liu #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 14323608e23SJason Liu #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 14423608e23SJason Liu #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 14523608e23SJason Liu #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 14623608e23SJason Liu #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 14723608e23SJason Liu #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 14823608e23SJason Liu #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 14923608e23SJason Liu #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 15023608e23SJason Liu #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 15123608e23SJason Liu #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 15223608e23SJason Liu #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 15323608e23SJason Liu #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 15423608e23SJason Liu #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 15523608e23SJason Liu #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 15623608e23SJason Liu #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 15723608e23SJason Liu #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 15823608e23SJason Liu #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 15923608e23SJason Liu #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 16023608e23SJason Liu #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 16123608e23SJason Liu #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 16223608e23SJason Liu #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 16323608e23SJason Liu #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 16423608e23SJason Liu #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 16523608e23SJason Liu #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 16623608e23SJason Liu 16723608e23SJason Liu #define CHIP_REV_1_0 0x10 16823608e23SJason Liu #define IRAM_SIZE 0x00040000 16923608e23SJason Liu #define IMX_IIM_BASE OCOTP_BASE_ADDR 17028774cbaSTroy Kisky #define FEC_QUIRK_ENET_MAC 17123608e23SJason Liu 1724b3a30e9SEric Nelson #define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31)) 1734b3a30e9SEric Nelson #define GPIO_TO_PORT(number) (((number)/32)+1) 1744b3a30e9SEric Nelson #define GPIO_TO_INDEX(number) ((number)&31) 1754b3a30e9SEric Nelson 17623608e23SJason Liu #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 17723608e23SJason Liu #include <asm/types.h> 17823608e23SJason Liu 179be252b65SFabio Estevam extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 18023608e23SJason Liu 18123608e23SJason Liu /* System Reset Controller (SRC) */ 18223608e23SJason Liu struct src { 18323608e23SJason Liu u32 scr; 18423608e23SJason Liu u32 sbmr1; 18523608e23SJason Liu u32 srsr; 18623608e23SJason Liu u32 reserved1[2]; 18723608e23SJason Liu u32 sisr; 18823608e23SJason Liu u32 simr; 18923608e23SJason Liu u32 sbmr2; 19023608e23SJason Liu u32 gpr1; 19123608e23SJason Liu u32 gpr2; 19223608e23SJason Liu u32 gpr3; 19323608e23SJason Liu u32 gpr4; 19423608e23SJason Liu u32 gpr5; 19523608e23SJason Liu u32 gpr6; 19623608e23SJason Liu u32 gpr7; 19723608e23SJason Liu u32 gpr8; 19823608e23SJason Liu u32 gpr9; 19923608e23SJason Liu u32 gpr10; 20023608e23SJason Liu }; 20123608e23SJason Liu 202d5c37c9cSEric Nelson /* ECSPI registers */ 203d5c37c9cSEric Nelson struct cspi_regs { 204d5c37c9cSEric Nelson u32 rxdata; 205d5c37c9cSEric Nelson u32 txdata; 206d5c37c9cSEric Nelson u32 ctrl; 207d5c37c9cSEric Nelson u32 cfg; 208d5c37c9cSEric Nelson u32 intr; 209d5c37c9cSEric Nelson u32 dma; 210d5c37c9cSEric Nelson u32 stat; 211d5c37c9cSEric Nelson u32 period; 212d5c37c9cSEric Nelson }; 213d5c37c9cSEric Nelson 214d5c37c9cSEric Nelson /* 215d5c37c9cSEric Nelson * CSPI register definitions 216d5c37c9cSEric Nelson */ 217d5c37c9cSEric Nelson #define MXC_ECSPI 218d5c37c9cSEric Nelson #define MXC_CSPICTRL_EN (1 << 0) 219d5c37c9cSEric Nelson #define MXC_CSPICTRL_MODE (1 << 1) 220d5c37c9cSEric Nelson #define MXC_CSPICTRL_XCH (1 << 2) 221d5c37c9cSEric Nelson #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 222d5c37c9cSEric Nelson #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 223d5c37c9cSEric Nelson #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 224d5c37c9cSEric Nelson #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 225d5c37c9cSEric Nelson #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 226d5c37c9cSEric Nelson #define MXC_CSPICTRL_MAXBITS 0xfff 227d5c37c9cSEric Nelson #define MXC_CSPICTRL_TC (1 << 7) 228d5c37c9cSEric Nelson #define MXC_CSPICTRL_RXOVF (1 << 6) 229d5c37c9cSEric Nelson #define MXC_CSPIPERIOD_32KHZ (1 << 15) 230d5c37c9cSEric Nelson #define MAX_SPI_BYTES 32 231d5c37c9cSEric Nelson 232d5c37c9cSEric Nelson /* Bit position inside CTRL register to be associated with SS */ 233d5c37c9cSEric Nelson #define MXC_CSPICTRL_CHAN 18 234d5c37c9cSEric Nelson 235d5c37c9cSEric Nelson /* Bit position inside CON register to be associated with SS */ 236d5c37c9cSEric Nelson #define MXC_CSPICON_POL 4 237d5c37c9cSEric Nelson #define MXC_CSPICON_PHA 0 238d5c37c9cSEric Nelson #define MXC_CSPICON_SSPOL 12 239d5c37c9cSEric Nelson #define MXC_SPI_BASE_ADDRESSES \ 240d5c37c9cSEric Nelson ECSPI1_BASE_ADDR, \ 241d5c37c9cSEric Nelson ECSPI2_BASE_ADDR, \ 242d5c37c9cSEric Nelson ECSPI3_BASE_ADDR, \ 243d5c37c9cSEric Nelson ECSPI4_BASE_ADDR, \ 244d5c37c9cSEric Nelson ECSPI5_BASE_ADDR 245d5c37c9cSEric Nelson 24623608e23SJason Liu struct iim_regs { 24723608e23SJason Liu u32 ctrl; 24823608e23SJason Liu u32 ctrl_set; 24923608e23SJason Liu u32 ctrl_clr; 25023608e23SJason Liu u32 ctrl_tog; 25123608e23SJason Liu u32 timing; 25223608e23SJason Liu u32 rsvd0[3]; 25323608e23SJason Liu u32 data; 25423608e23SJason Liu u32 rsvd1[3]; 25523608e23SJason Liu u32 read_ctrl; 25623608e23SJason Liu u32 rsvd2[3]; 25723608e23SJason Liu u32 fuse_data; 25823608e23SJason Liu u32 rsvd3[3]; 25923608e23SJason Liu u32 sticky; 26023608e23SJason Liu u32 rsvd4[3]; 26123608e23SJason Liu u32 scs; 26223608e23SJason Liu u32 scs_set; 26323608e23SJason Liu u32 scs_clr; 26423608e23SJason Liu u32 scs_tog; 26523608e23SJason Liu u32 crc_addr; 26623608e23SJason Liu u32 rsvd5[3]; 26723608e23SJason Liu u32 crc_value; 26823608e23SJason Liu u32 rsvd6[3]; 26923608e23SJason Liu u32 version; 270bd2e27c0SJason Liu u32 rsvd7[0xdb]; 27123608e23SJason Liu 27223608e23SJason Liu struct fuse_bank { 27323608e23SJason Liu u32 fuse_regs[0x20]; 27423608e23SJason Liu } bank[15]; 27523608e23SJason Liu }; 27623608e23SJason Liu 27723608e23SJason Liu struct fuse_bank4_regs { 27823608e23SJason Liu u32 sjc_resp_low; 27923608e23SJason Liu u32 rsvd0[3]; 28023608e23SJason Liu u32 sjc_resp_high; 28123608e23SJason Liu u32 rsvd1[3]; 28223608e23SJason Liu u32 mac_addr_low; 28323608e23SJason Liu u32 rsvd2[3]; 28423608e23SJason Liu u32 mac_addr_high; 28523608e23SJason Liu u32 rsvd3[0x13]; 28623608e23SJason Liu }; 28723608e23SJason Liu 288f2f77458SJason Liu struct aipstz_regs { 289f2f77458SJason Liu u32 mprot0; 290f2f77458SJason Liu u32 mprot1; 291f2f77458SJason Liu u32 rsvd[0xe]; 292f2f77458SJason Liu u32 opacr0; 293f2f77458SJason Liu u32 opacr1; 294f2f77458SJason Liu u32 opacr2; 295f2f77458SJason Liu u32 opacr3; 296f2f77458SJason Liu u32 opacr4; 297f2f77458SJason Liu }; 298f2f77458SJason Liu 299a7683867SFabio Estevam struct anatop_regs { 300a7683867SFabio Estevam u32 pll_sys; /* 0x000 */ 301a7683867SFabio Estevam u32 pll_sys_set; /* 0x004 */ 302a7683867SFabio Estevam u32 pll_sys_clr; /* 0x008 */ 303a7683867SFabio Estevam u32 pll_sys_tog; /* 0x00c */ 304a7683867SFabio Estevam u32 usb1_pll_480_ctrl; /* 0x010 */ 305a7683867SFabio Estevam u32 usb1_pll_480_ctrl_set; /* 0x014 */ 306a7683867SFabio Estevam u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 307a7683867SFabio Estevam u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 308a7683867SFabio Estevam u32 usb2_pll_480_ctrl; /* 0x020 */ 309a7683867SFabio Estevam u32 usb2_pll_480_ctrl_set; /* 0x024 */ 310a7683867SFabio Estevam u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 311a7683867SFabio Estevam u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 312a7683867SFabio Estevam u32 pll_528; /* 0x030 */ 313a7683867SFabio Estevam u32 pll_528_set; /* 0x034 */ 314a7683867SFabio Estevam u32 pll_528_clr; /* 0x038 */ 315a7683867SFabio Estevam u32 pll_528_tog; /* 0x03c */ 316a7683867SFabio Estevam u32 pll_528_ss; /* 0x040 */ 317a7683867SFabio Estevam u32 rsvd0[3]; 318a7683867SFabio Estevam u32 pll_528_num; /* 0x050 */ 319a7683867SFabio Estevam u32 rsvd1[3]; 320a7683867SFabio Estevam u32 pll_528_denom; /* 0x060 */ 321a7683867SFabio Estevam u32 rsvd2[3]; 322a7683867SFabio Estevam u32 pll_audio; /* 0x070 */ 323a7683867SFabio Estevam u32 pll_audio_set; /* 0x074 */ 324a7683867SFabio Estevam u32 pll_audio_clr; /* 0x078 */ 325a7683867SFabio Estevam u32 pll_audio_tog; /* 0x07c */ 326a7683867SFabio Estevam u32 pll_audio_num; /* 0x080 */ 327a7683867SFabio Estevam u32 rsvd3[3]; 328a7683867SFabio Estevam u32 pll_audio_denom; /* 0x090 */ 329a7683867SFabio Estevam u32 rsvd4[3]; 330a7683867SFabio Estevam u32 pll_video; /* 0x0a0 */ 331a7683867SFabio Estevam u32 pll_video_set; /* 0x0a4 */ 332a7683867SFabio Estevam u32 pll_video_clr; /* 0x0a8 */ 333a7683867SFabio Estevam u32 pll_video_tog; /* 0x0ac */ 334a7683867SFabio Estevam u32 pll_video_num; /* 0x0b0 */ 335a7683867SFabio Estevam u32 rsvd5[3]; 336a7683867SFabio Estevam u32 pll_video_denom; /* 0x0c0 */ 337a7683867SFabio Estevam u32 rsvd6[3]; 338a7683867SFabio Estevam u32 pll_mlb; /* 0x0d0 */ 339a7683867SFabio Estevam u32 pll_mlb_set; /* 0x0d4 */ 340a7683867SFabio Estevam u32 pll_mlb_clr; /* 0x0d8 */ 341a7683867SFabio Estevam u32 pll_mlb_tog; /* 0x0dc */ 342a7683867SFabio Estevam u32 pll_enet; /* 0x0e0 */ 343a7683867SFabio Estevam u32 pll_enet_set; /* 0x0e4 */ 344a7683867SFabio Estevam u32 pll_enet_clr; /* 0x0e8 */ 345a7683867SFabio Estevam u32 pll_enet_tog; /* 0x0ec */ 346a7683867SFabio Estevam u32 pfd_480; /* 0x0f0 */ 347a7683867SFabio Estevam u32 pfd_480_set; /* 0x0f4 */ 348a7683867SFabio Estevam u32 pfd_480_clr; /* 0x0f8 */ 349a7683867SFabio Estevam u32 pfd_480_tog; /* 0x0fc */ 350a7683867SFabio Estevam u32 pfd_528; /* 0x100 */ 351a7683867SFabio Estevam u32 pfd_528_set; /* 0x104 */ 352a7683867SFabio Estevam u32 pfd_528_clr; /* 0x108 */ 353a7683867SFabio Estevam u32 pfd_528_tog; /* 0x10c */ 354a7683867SFabio Estevam u32 reg_1p1; /* 0x110 */ 355a7683867SFabio Estevam u32 reg_1p1_set; /* 0x114 */ 356a7683867SFabio Estevam u32 reg_1p1_clr; /* 0x118 */ 357a7683867SFabio Estevam u32 reg_1p1_tog; /* 0x11c */ 358a7683867SFabio Estevam u32 reg_3p0; /* 0x120 */ 359a7683867SFabio Estevam u32 reg_3p0_set; /* 0x124 */ 360a7683867SFabio Estevam u32 reg_3p0_clr; /* 0x128 */ 361a7683867SFabio Estevam u32 reg_3p0_tog; /* 0x12c */ 362a7683867SFabio Estevam u32 reg_2p5; /* 0x130 */ 363a7683867SFabio Estevam u32 reg_2p5_set; /* 0x134 */ 364a7683867SFabio Estevam u32 reg_2p5_clr; /* 0x138 */ 365a7683867SFabio Estevam u32 reg_2p5_tog; /* 0x13c */ 366a7683867SFabio Estevam u32 reg_core; /* 0x140 */ 367a7683867SFabio Estevam u32 reg_core_set; /* 0x144 */ 368a7683867SFabio Estevam u32 reg_core_clr; /* 0x148 */ 369a7683867SFabio Estevam u32 reg_core_tog; /* 0x14c */ 370a7683867SFabio Estevam u32 ana_misc0; /* 0x150 */ 371a7683867SFabio Estevam u32 ana_misc0_set; /* 0x154 */ 372a7683867SFabio Estevam u32 ana_misc0_clr; /* 0x158 */ 373a7683867SFabio Estevam u32 ana_misc0_tog; /* 0x15c */ 374a7683867SFabio Estevam u32 ana_misc1; /* 0x160 */ 375a7683867SFabio Estevam u32 ana_misc1_set; /* 0x164 */ 376a7683867SFabio Estevam u32 ana_misc1_clr; /* 0x168 */ 377a7683867SFabio Estevam u32 ana_misc1_tog; /* 0x16c */ 378a7683867SFabio Estevam u32 ana_misc2; /* 0x170 */ 379a7683867SFabio Estevam u32 ana_misc2_set; /* 0x174 */ 380a7683867SFabio Estevam u32 ana_misc2_clr; /* 0x178 */ 381a7683867SFabio Estevam u32 ana_misc2_tog; /* 0x17c */ 382a7683867SFabio Estevam u32 tempsense0; /* 0x180 */ 383a7683867SFabio Estevam u32 tempsense0_set; /* 0x184 */ 384a7683867SFabio Estevam u32 tempsense0_clr; /* 0x188 */ 385a7683867SFabio Estevam u32 tempsense0_tog; /* 0x18c */ 386a7683867SFabio Estevam u32 tempsense1; /* 0x190 */ 387a7683867SFabio Estevam u32 tempsense1_set; /* 0x194 */ 388a7683867SFabio Estevam u32 tempsense1_clr; /* 0x198 */ 389a7683867SFabio Estevam u32 tempsense1_tog; /* 0x19c */ 390a7683867SFabio Estevam u32 usb1_vbus_detect; /* 0x1a0 */ 391a7683867SFabio Estevam u32 usb1_vbus_detect_set; /* 0x1a4 */ 392a7683867SFabio Estevam u32 usb1_vbus_detect_clr; /* 0x1a8 */ 393a7683867SFabio Estevam u32 usb1_vbus_detect_tog; /* 0x1ac */ 394a7683867SFabio Estevam u32 usb1_chrg_detect; /* 0x1b0 */ 395a7683867SFabio Estevam u32 usb1_chrg_detect_set; /* 0x1b4 */ 396a7683867SFabio Estevam u32 usb1_chrg_detect_clr; /* 0x1b8 */ 397a7683867SFabio Estevam u32 usb1_chrg_detect_tog; /* 0x1bc */ 398a7683867SFabio Estevam u32 usb1_vbus_det_stat; /* 0x1c0 */ 399a7683867SFabio Estevam u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 400a7683867SFabio Estevam u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 401a7683867SFabio Estevam u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 402a7683867SFabio Estevam u32 usb1_chrg_det_stat; /* 0x1d0 */ 403a7683867SFabio Estevam u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 404a7683867SFabio Estevam u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 405a7683867SFabio Estevam u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 406a7683867SFabio Estevam u32 usb1_loopback; /* 0x1e0 */ 407a7683867SFabio Estevam u32 usb1_loopback_set; /* 0x1e4 */ 408a7683867SFabio Estevam u32 usb1_loopback_clr; /* 0x1e8 */ 409a7683867SFabio Estevam u32 usb1_loopback_tog; /* 0x1ec */ 410a7683867SFabio Estevam u32 usb1_misc; /* 0x1f0 */ 411a7683867SFabio Estevam u32 usb1_misc_set; /* 0x1f4 */ 412a7683867SFabio Estevam u32 usb1_misc_clr; /* 0x1f8 */ 413a7683867SFabio Estevam u32 usb1_misc_tog; /* 0x1fc */ 414a7683867SFabio Estevam u32 usb2_vbus_detect; /* 0x200 */ 415a7683867SFabio Estevam u32 usb2_vbus_detect_set; /* 0x204 */ 416a7683867SFabio Estevam u32 usb2_vbus_detect_clr; /* 0x208 */ 417a7683867SFabio Estevam u32 usb2_vbus_detect_tog; /* 0x20c */ 418a7683867SFabio Estevam u32 usb2_chrg_detect; /* 0x210 */ 419a7683867SFabio Estevam u32 usb2_chrg_detect_set; /* 0x214 */ 420a7683867SFabio Estevam u32 usb2_chrg_detect_clr; /* 0x218 */ 421a7683867SFabio Estevam u32 usb2_chrg_detect_tog; /* 0x21c */ 422a7683867SFabio Estevam u32 usb2_vbus_det_stat; /* 0x220 */ 423a7683867SFabio Estevam u32 usb2_vbus_det_stat_set; /* 0x224 */ 424a7683867SFabio Estevam u32 usb2_vbus_det_stat_clr; /* 0x228 */ 425a7683867SFabio Estevam u32 usb2_vbus_det_stat_tog; /* 0x22c */ 426a7683867SFabio Estevam u32 usb2_chrg_det_stat; /* 0x230 */ 427a7683867SFabio Estevam u32 usb2_chrg_det_stat_set; /* 0x234 */ 428a7683867SFabio Estevam u32 usb2_chrg_det_stat_clr; /* 0x238 */ 429a7683867SFabio Estevam u32 usb2_chrg_det_stat_tog; /* 0x23c */ 430a7683867SFabio Estevam u32 usb2_loopback; /* 0x240 */ 431a7683867SFabio Estevam u32 usb2_loopback_set; /* 0x244 */ 432a7683867SFabio Estevam u32 usb2_loopback_clr; /* 0x248 */ 433a7683867SFabio Estevam u32 usb2_loopback_tog; /* 0x24c */ 434a7683867SFabio Estevam u32 usb2_misc; /* 0x250 */ 435a7683867SFabio Estevam u32 usb2_misc_set; /* 0x254 */ 436a7683867SFabio Estevam u32 usb2_misc_clr; /* 0x258 */ 437a7683867SFabio Estevam u32 usb2_misc_tog; /* 0x25c */ 438a7683867SFabio Estevam u32 digprog; /* 0x260 */ 439a7683867SFabio Estevam }; 440a7683867SFabio Estevam 44123608e23SJason Liu #endif /* __ASSEMBLER__*/ 44223608e23SJason Liu #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 443