123608e23SJason Liu /* 223608e23SJason Liu * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 323608e23SJason Liu * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 523608e23SJason Liu */ 623608e23SJason Liu 723608e23SJason Liu #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 823608e23SJason Liu #define __ASM_ARCH_MX6_IMX_REGS_H__ 923608e23SJason Liu 108e99ecd7SBenoît Thébaudeau #define ARCH_MXC 118e99ecd7SBenoît Thébaudeau 12d73d5aeeSPeng Fan #ifdef CONFIG_MX6UL 13d73d5aeeSPeng Fan #define CONFIG_SYS_CACHELINE_SIZE 64 14d73d5aeeSPeng Fan #else 15c415919dSEric Nelson #define CONFIG_SYS_CACHELINE_SIZE 32 16d73d5aeeSPeng Fan #endif 17c415919dSEric Nelson 1823608e23SJason Liu #define ROMCP_ARB_BASE_ADDR 0x00000000 1923608e23SJason Liu #define ROMCP_ARB_END_ADDR 0x000FFFFF 2025b4aa14SFabio Estevam 2125b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 2225b4aa14SFabio Estevam #define GPU_2D_ARB_BASE_ADDR 0x02200000 2325b4aa14SFabio Estevam #define GPU_2D_ARB_END_ADDR 0x02203FFF 2425b4aa14SFabio Estevam #define OPENVG_ARB_BASE_ADDR 0x02204000 2525b4aa14SFabio Estevam #define OPENVG_ARB_END_ADDR 0x02207FFF 26bc32fc69SPeng Fan #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 2705d54b82SFabio Estevam #define CAAM_ARB_BASE_ADDR 0x00100000 2805d54b82SFabio Estevam #define CAAM_ARB_END_ADDR 0x00107FFF 2905d54b82SFabio Estevam #define GPU_ARB_BASE_ADDR 0x01800000 3005d54b82SFabio Estevam #define GPU_ARB_END_ADDR 0x01803FFF 3105d54b82SFabio Estevam #define APBH_DMA_ARB_BASE_ADDR 0x01804000 3205d54b82SFabio Estevam #define APBH_DMA_ARB_END_ADDR 0x0180BFFF 3305d54b82SFabio Estevam #define M4_BOOTROM_BASE_ADDR 0x007F8000 3405d54b82SFabio Estevam 3525b4aa14SFabio Estevam #else 3623608e23SJason Liu #define CAAM_ARB_BASE_ADDR 0x00100000 3723608e23SJason Liu #define CAAM_ARB_END_ADDR 0x00103FFF 3823608e23SJason Liu #define APBH_DMA_ARB_BASE_ADDR 0x00110000 3923608e23SJason Liu #define APBH_DMA_ARB_END_ADDR 0x00117FFF 4023608e23SJason Liu #define HDMI_ARB_BASE_ADDR 0x00120000 4123608e23SJason Liu #define HDMI_ARB_END_ADDR 0x00128FFF 4223608e23SJason Liu #define GPU_3D_ARB_BASE_ADDR 0x00130000 4323608e23SJason Liu #define GPU_3D_ARB_END_ADDR 0x00133FFF 4423608e23SJason Liu #define GPU_2D_ARB_BASE_ADDR 0x00134000 4523608e23SJason Liu #define GPU_2D_ARB_END_ADDR 0x00137FFF 4623608e23SJason Liu #define DTCP_ARB_BASE_ADDR 0x00138000 4723608e23SJason Liu #define DTCP_ARB_END_ADDR 0x0013BFFF 4825b4aa14SFabio Estevam #endif /* CONFIG_MX6SL */ 4999193e30SStefan Roese 5099193e30SStefan Roese #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 5199193e30SStefan Roese #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 5299193e30SStefan Roese #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 5399193e30SStefan Roese 5423608e23SJason Liu /* GPV - PL301 configuration ports */ 55bc32fc69SPeng Fan #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 5625b4aa14SFabio Estevam #define GPV2_BASE_ADDR 0x00D00000 5725b4aa14SFabio Estevam #else 5823608e23SJason Liu #define GPV2_BASE_ADDR 0x00200000 5925b4aa14SFabio Estevam #endif 6025b4aa14SFabio Estevam 61bc32fc69SPeng Fan #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 6205d54b82SFabio Estevam #define GPV3_BASE_ADDR 0x00E00000 6305d54b82SFabio Estevam #define GPV4_BASE_ADDR 0x00F00000 6405d54b82SFabio Estevam #define GPV5_BASE_ADDR 0x01000000 6505d54b82SFabio Estevam #define GPV6_BASE_ADDR 0x01100000 6605d54b82SFabio Estevam #define PCIE_ARB_BASE_ADDR 0x08000000 6705d54b82SFabio Estevam #define PCIE_ARB_END_ADDR 0x08FFFFFF 6805d54b82SFabio Estevam 6905d54b82SFabio Estevam #else 7023608e23SJason Liu #define GPV3_BASE_ADDR 0x00300000 7123608e23SJason Liu #define GPV4_BASE_ADDR 0x00800000 7205d54b82SFabio Estevam #define PCIE_ARB_BASE_ADDR 0x01000000 7305d54b82SFabio Estevam #define PCIE_ARB_END_ADDR 0x01FFFFFF 7405d54b82SFabio Estevam #endif 7505d54b82SFabio Estevam 7623608e23SJason Liu #define IRAM_BASE_ADDR 0x00900000 7723608e23SJason Liu #define SCU_BASE_ADDR 0x00A00000 7823608e23SJason Liu #define IC_INTERFACES_BASE_ADDR 0x00A00100 7923608e23SJason Liu #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 8023608e23SJason Liu #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 8123608e23SJason Liu #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 826d73c234SFabio Estevam #define L2_PL310_BASE 0x00A02000 8323608e23SJason Liu #define GPV0_BASE_ADDR 0x00B00000 8423608e23SJason Liu #define GPV1_BASE_ADDR 0x00C00000 8523608e23SJason Liu 8623608e23SJason Liu #define AIPS1_ARB_BASE_ADDR 0x02000000 8723608e23SJason Liu #define AIPS1_ARB_END_ADDR 0x020FFFFF 8823608e23SJason Liu #define AIPS2_ARB_BASE_ADDR 0x02100000 8923608e23SJason Liu #define AIPS2_ARB_END_ADDR 0x021FFFFF 90bc32fc69SPeng Fan /* AIPS3 only on i.MX6SX */ 91e8cdeefcSYe.Li #define AIPS3_ARB_BASE_ADDR 0x02200000 92e8cdeefcSYe.Li #define AIPS3_ARB_END_ADDR 0x022FFFFF 93bc32fc69SPeng Fan #ifdef CONFIG_MX6SX 9405d54b82SFabio Estevam #define WEIM_ARB_BASE_ADDR 0x50000000 9505d54b82SFabio Estevam #define WEIM_ARB_END_ADDR 0x57FFFFFF 96b93ab2eeSPeng Fan #define QSPI0_AMBA_BASE 0x60000000 97b93ab2eeSPeng Fan #define QSPI0_AMBA_END 0x6FFFFFFF 98b93ab2eeSPeng Fan #define QSPI1_AMBA_BASE 0x70000000 99b93ab2eeSPeng Fan #define QSPI1_AMBA_END 0x7FFFFFFF 100bc32fc69SPeng Fan #elif defined(CONFIG_MX6UL) 101bc32fc69SPeng Fan #define WEIM_ARB_BASE_ADDR 0x50000000 102bc32fc69SPeng Fan #define WEIM_ARB_END_ADDR 0x57FFFFFF 103bc32fc69SPeng Fan #define QSPI0_AMBA_BASE 0x60000000 104bc32fc69SPeng Fan #define QSPI0_AMBA_END 0x6FFFFFFF 10505d54b82SFabio Estevam #else 10623608e23SJason Liu #define SATA_ARB_BASE_ADDR 0x02200000 10723608e23SJason Liu #define SATA_ARB_END_ADDR 0x02203FFF 10823608e23SJason Liu #define OPENVG_ARB_BASE_ADDR 0x02204000 10923608e23SJason Liu #define OPENVG_ARB_END_ADDR 0x02207FFF 11023608e23SJason Liu #define HSI_ARB_BASE_ADDR 0x02208000 11123608e23SJason Liu #define HSI_ARB_END_ADDR 0x0220BFFF 11223608e23SJason Liu #define IPU1_ARB_BASE_ADDR 0x02400000 11323608e23SJason Liu #define IPU1_ARB_END_ADDR 0x027FFFFF 11423608e23SJason Liu #define IPU2_ARB_BASE_ADDR 0x02800000 11523608e23SJason Liu #define IPU2_ARB_END_ADDR 0x02BFFFFF 11623608e23SJason Liu #define WEIM_ARB_BASE_ADDR 0x08000000 11723608e23SJason Liu #define WEIM_ARB_END_ADDR 0x0FFFFFFF 11805d54b82SFabio Estevam #endif 11923608e23SJason Liu 120bc32fc69SPeng Fan #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 12125b4aa14SFabio Estevam #define MMDC0_ARB_BASE_ADDR 0x80000000 12225b4aa14SFabio Estevam #define MMDC0_ARB_END_ADDR 0xFFFFFFFF 12325b4aa14SFabio Estevam #define MMDC1_ARB_BASE_ADDR 0xC0000000 12425b4aa14SFabio Estevam #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 12525b4aa14SFabio Estevam #else 12623608e23SJason Liu #define MMDC0_ARB_BASE_ADDR 0x10000000 12723608e23SJason Liu #define MMDC0_ARB_END_ADDR 0x7FFFFFFF 12823608e23SJason Liu #define MMDC1_ARB_BASE_ADDR 0x80000000 12923608e23SJason Liu #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 13025b4aa14SFabio Estevam #endif 13123608e23SJason Liu 13205d54b82SFabio Estevam #ifndef CONFIG_MX6SX 13305d4df1dSFabio Estevam #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR 13405d4df1dSFabio Estevam #define IPU_SOC_OFFSET 0x00200000 13505d54b82SFabio Estevam #endif 13605d4df1dSFabio Estevam 13723608e23SJason Liu /* Defines for Blocks connected via AIPS (SkyBlue) */ 13823608e23SJason Liu #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 13923608e23SJason Liu #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 14050a082a8SAdrian Alonso #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR 14123608e23SJason Liu #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 14223608e23SJason Liu #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 14350a082a8SAdrian Alonso #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR 14423608e23SJason Liu 14523608e23SJason Liu #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 14623608e23SJason Liu #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 14723608e23SJason Liu #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 14823608e23SJason Liu #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 14923608e23SJason Liu #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 15025b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 15125b4aa14SFabio Estevam #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 15225b4aa14SFabio Estevam #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) 15325b4aa14SFabio Estevam #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 15425b4aa14SFabio Estevam #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 15525b4aa14SFabio Estevam #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 15625b4aa14SFabio Estevam #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 15725b4aa14SFabio Estevam #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 15825b4aa14SFabio Estevam #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) 15925b4aa14SFabio Estevam #else 16005d54b82SFabio Estevam #ifndef CONFIG_MX6SX 16123608e23SJason Liu #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 16205d54b82SFabio Estevam #endif 16323608e23SJason Liu #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 16423608e23SJason Liu #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 165*51560f0bSStefan Roese #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) 16623608e23SJason Liu #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 16723608e23SJason Liu #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 16823608e23SJason Liu #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 16923608e23SJason Liu #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 17025b4aa14SFabio Estevam #endif 17125b4aa14SFabio Estevam 17205d54b82SFabio Estevam #ifndef CONFIG_MX6SX 17323608e23SJason Liu #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 17423608e23SJason Liu #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 17505d54b82SFabio Estevam #endif 17623608e23SJason Liu #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 17723608e23SJason Liu 17823608e23SJason Liu #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 17923608e23SJason Liu #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 18023608e23SJason Liu #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 18123608e23SJason Liu #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 18223608e23SJason Liu #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 18323608e23SJason Liu #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 18423608e23SJason Liu #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 18523608e23SJason Liu #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 18623608e23SJason Liu #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 18723608e23SJason Liu #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 18823608e23SJason Liu #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 18923608e23SJason Liu #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 19023608e23SJason Liu #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 19123608e23SJason Liu #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 19223608e23SJason Liu #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 19323608e23SJason Liu #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 19423608e23SJason Liu #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 19523608e23SJason Liu #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 1963f467529SWolfgang Grandegger #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 1973f467529SWolfgang Grandegger #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 1983f467529SWolfgang Grandegger #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 19923608e23SJason Liu #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 20023608e23SJason Liu #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 20123608e23SJason Liu #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 20223608e23SJason Liu #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 20323608e23SJason Liu #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 20423608e23SJason Liu #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 20523608e23SJason Liu #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 20625b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 20725b4aa14SFabio Estevam #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 20825b4aa14SFabio Estevam #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 20925b4aa14SFabio Estevam #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 21005d54b82SFabio Estevam #elif CONFIG_MX6SX 21105d54b82SFabio Estevam #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 21205d54b82SFabio Estevam #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 21305d54b82SFabio Estevam #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) 21405d54b82SFabio Estevam #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 21505d54b82SFabio Estevam #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 21605d54b82SFabio Estevam #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) 21725b4aa14SFabio Estevam #else 21823608e23SJason Liu #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 21923608e23SJason Liu #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 22023608e23SJason Liu #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 22125b4aa14SFabio Estevam #endif 22223608e23SJason Liu 22323608e23SJason Liu #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 22423608e23SJason Liu #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 22550a082a8SAdrian Alonso #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) 22650a082a8SAdrian Alonso #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) 22723608e23SJason Liu #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 22823608e23SJason Liu #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 2290200020bSRaul Cardenas 2300200020bSRaul Cardenas #define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR 2310200020bSRaul Cardenas #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000) 2320200020bSRaul Cardenas 2335546ad07SYe.Li #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 2345546ad07SYe.Li #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 23525b4aa14SFabio Estevam 23623608e23SJason Liu #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 23725b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 23825b4aa14SFabio Estevam #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 23925b4aa14SFabio Estevam #else 24023608e23SJason Liu #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 24125b4aa14SFabio Estevam #endif 24225b4aa14SFabio Estevam 24323608e23SJason Liu #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 24423608e23SJason Liu #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 24523608e23SJason Liu #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 24623608e23SJason Liu #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 24723608e23SJason Liu #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 24823608e23SJason Liu #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 24923608e23SJason Liu #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 25023608e23SJason Liu #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 25123608e23SJason Liu #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 252bc32fc69SPeng Fan /* i.MX6SL */ 25325b4aa14SFabio Estevam #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 254bc32fc69SPeng Fan #ifdef CONFIG_MX6UL 255bc32fc69SPeng Fan #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 25625b4aa14SFabio Estevam #else 257bc32fc69SPeng Fan /* i.MX6SX */ 258bc32fc69SPeng Fan #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 25925b4aa14SFabio Estevam #endif 260bc32fc69SPeng Fan /* i.MX6DQ/SDL */ 261bc32fc69SPeng Fan #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 26225b4aa14SFabio Estevam 26323608e23SJason Liu #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 26423608e23SJason Liu #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 26523608e23SJason Liu #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 26623608e23SJason Liu #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 26723608e23SJason Liu #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 268b1ce1fb5SPeng Fan #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 26905d54b82SFabio Estevam #ifdef CONFIG_MX6SX 27005d54b82SFabio Estevam #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 27105d54b82SFabio Estevam #else 27223608e23SJason Liu #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 27305d54b82SFabio Estevam #endif 27423608e23SJason Liu #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 275bc32fc69SPeng Fan #ifdef CONFIG_MX6UL 276bc32fc69SPeng Fan #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 277bc32fc69SPeng Fan #elif defined(CONFIG_MX6SX) 27805d54b82SFabio Estevam #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 27923608e23SJason Liu #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 28005d54b82SFabio Estevam #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 281b93ab2eeSPeng Fan #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 282b93ab2eeSPeng Fan #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 28305d54b82SFabio Estevam #else 284bc32fc69SPeng Fan #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 28523608e23SJason Liu #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 28623608e23SJason Liu #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 28723608e23SJason Liu #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 28805d54b82SFabio Estevam #endif 289bc32fc69SPeng Fan #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 29023608e23SJason Liu #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 29123608e23SJason Liu #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 29223608e23SJason Liu #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 29323608e23SJason Liu #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 29421a26940SHeiko Schocher #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 29523608e23SJason Liu #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 29623608e23SJason Liu #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 29723608e23SJason Liu 29805d54b82SFabio Estevam #ifdef CONFIG_MX6SX 29905d54b82SFabio Estevam #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) 30005d54b82SFabio Estevam #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) 30105d54b82SFabio Estevam #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) 30205d54b82SFabio Estevam #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) 30305d54b82SFabio Estevam #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) 30405d54b82SFabio Estevam #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) 30505d54b82SFabio Estevam #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) 30605d54b82SFabio Estevam #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) 30705d54b82SFabio Estevam #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) 30805d54b82SFabio Estevam #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) 30905d54b82SFabio Estevam #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) 31005d54b82SFabio Estevam #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) 31105d54b82SFabio Estevam #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) 31205d54b82SFabio Estevam #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) 31305d54b82SFabio Estevam #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) 31405d54b82SFabio Estevam #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) 31505d54b82SFabio Estevam #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) 31605d54b82SFabio Estevam #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) 31705d54b82SFabio Estevam #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) 31805d54b82SFabio Estevam #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) 31905d54b82SFabio Estevam #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) 32005d54b82SFabio Estevam #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) 32105d54b82SFabio Estevam #endif 322b1ce1fb5SPeng Fan /* Only for i.MX6SX */ 323b1ce1fb5SPeng Fan #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) 324b1ce1fb5SPeng Fan #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) 325bc32fc69SPeng Fan #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) 326bc32fc69SPeng Fan 327bc32fc69SPeng Fan #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 32823608e23SJason Liu #define IRAM_SIZE 0x00040000 32905d54b82SFabio Estevam #else 33005d54b82SFabio Estevam #define IRAM_SIZE 0x00020000 33105d54b82SFabio Estevam #endif 33228774cbaSTroy Kisky #define FEC_QUIRK_ENET_MAC 33323608e23SJason Liu 334b1ce1fb5SPeng Fan #include <asm/imx-common/regs-lcdif.h> 33523608e23SJason Liu #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 33623608e23SJason Liu #include <asm/types.h> 33723608e23SJason Liu 338b1ce1fb5SPeng Fan /* only for i.MX6SX/UL */ 3390c890879SPeng Fan #define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \ 3400c890879SPeng Fan MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) 3410c890879SPeng Fan #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ 3420c890879SPeng Fan MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR) 343b1ce1fb5SPeng Fan 344b1ce1fb5SPeng Fan 345be252b65SFabio Estevam extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 34623608e23SJason Liu 347a76df709SGabriel Huau #define SRC_SCR_CORE_1_RESET_OFFSET 14 348a76df709SGabriel Huau #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET) 349a76df709SGabriel Huau #define SRC_SCR_CORE_2_RESET_OFFSET 15 350a76df709SGabriel Huau #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET) 351a76df709SGabriel Huau #define SRC_SCR_CORE_3_RESET_OFFSET 16 352a76df709SGabriel Huau #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET) 353a76df709SGabriel Huau #define SRC_SCR_CORE_1_ENABLE_OFFSET 22 354a76df709SGabriel Huau #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET) 355a76df709SGabriel Huau #define SRC_SCR_CORE_2_ENABLE_OFFSET 23 356a76df709SGabriel Huau #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET) 357a76df709SGabriel Huau #define SRC_SCR_CORE_3_ENABLE_OFFSET 24 358a76df709SGabriel Huau #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) 359a76df709SGabriel Huau 360613e0106SPeng Fan struct rdc_regs { 361613e0106SPeng Fan u32 vir; /* Version information */ 362613e0106SPeng Fan u32 reserved1[8]; 363613e0106SPeng Fan u32 stat; /* Status */ 364613e0106SPeng Fan u32 intctrl; /* Interrupt and Control */ 365613e0106SPeng Fan u32 intstat; /* Interrupt Status */ 366613e0106SPeng Fan u32 reserved2[116]; 367613e0106SPeng Fan u32 mda[32]; /* Master Domain Assignment */ 368613e0106SPeng Fan u32 reserved3[96]; 369613e0106SPeng Fan u32 pdap[104]; /* Peripheral Domain Access Permissions */ 370613e0106SPeng Fan u32 reserved4[88]; 371613e0106SPeng Fan struct { 372613e0106SPeng Fan u32 mrsa; /* Memory Region Start Address */ 373613e0106SPeng Fan u32 mrea; /* Memory Region End Address */ 374613e0106SPeng Fan u32 mrc; /* Memory Region Control */ 375613e0106SPeng Fan u32 mrvs; /* Memory Region Violation Status */ 376613e0106SPeng Fan } mem_region[55]; 377613e0106SPeng Fan }; 378613e0106SPeng Fan 379613e0106SPeng Fan struct rdc_sema_regs { 380613e0106SPeng Fan u8 gate[64]; /* Gate */ 381613e0106SPeng Fan u16 rstgt; /* Reset Gate */ 382613e0106SPeng Fan }; 383613e0106SPeng Fan 384573960acSFabio Estevam /* WEIM registers */ 385573960acSFabio Estevam struct weim { 386573960acSFabio Estevam u32 cs0gcr1; 387573960acSFabio Estevam u32 cs0gcr2; 388573960acSFabio Estevam u32 cs0rcr1; 389573960acSFabio Estevam u32 cs0rcr2; 390573960acSFabio Estevam u32 cs0wcr1; 391573960acSFabio Estevam u32 cs0wcr2; 392573960acSFabio Estevam 393573960acSFabio Estevam u32 cs1gcr1; 394573960acSFabio Estevam u32 cs1gcr2; 395573960acSFabio Estevam u32 cs1rcr1; 396573960acSFabio Estevam u32 cs1rcr2; 397573960acSFabio Estevam u32 cs1wcr1; 398573960acSFabio Estevam u32 cs1wcr2; 399573960acSFabio Estevam 400573960acSFabio Estevam u32 cs2gcr1; 401573960acSFabio Estevam u32 cs2gcr2; 402573960acSFabio Estevam u32 cs2rcr1; 403573960acSFabio Estevam u32 cs2rcr2; 404573960acSFabio Estevam u32 cs2wcr1; 405573960acSFabio Estevam u32 cs2wcr2; 406573960acSFabio Estevam 407573960acSFabio Estevam u32 cs3gcr1; 408573960acSFabio Estevam u32 cs3gcr2; 409573960acSFabio Estevam u32 cs3rcr1; 410573960acSFabio Estevam u32 cs3rcr2; 411573960acSFabio Estevam u32 cs3wcr1; 412573960acSFabio Estevam u32 cs3wcr2; 413573960acSFabio Estevam 414573960acSFabio Estevam u32 unused[12]; 415573960acSFabio Estevam 416573960acSFabio Estevam u32 wcr; 417573960acSFabio Estevam u32 wiar; 418573960acSFabio Estevam u32 ear; 419573960acSFabio Estevam }; 420573960acSFabio Estevam 42123608e23SJason Liu /* System Reset Controller (SRC) */ 42223608e23SJason Liu struct src { 42323608e23SJason Liu u32 scr; 42423608e23SJason Liu u32 sbmr1; 42523608e23SJason Liu u32 srsr; 42623608e23SJason Liu u32 reserved1[2]; 42723608e23SJason Liu u32 sisr; 42823608e23SJason Liu u32 simr; 42923608e23SJason Liu u32 sbmr2; 43023608e23SJason Liu u32 gpr1; 43123608e23SJason Liu u32 gpr2; 43223608e23SJason Liu u32 gpr3; 43323608e23SJason Liu u32 gpr4; 43423608e23SJason Liu u32 gpr5; 43523608e23SJason Liu u32 gpr6; 43623608e23SJason Liu u32 gpr7; 43723608e23SJason Liu u32 gpr8; 43823608e23SJason Liu u32 gpr9; 43923608e23SJason Liu u32 gpr10; 44023608e23SJason Liu }; 44123608e23SJason Liu 4420623d375SPeng Fan #define SRC_SCR_M4_ENABLE_OFFSET 22 4430623d375SPeng Fan #define SRC_SCR_M4_ENABLE_MASK (1 << 22) 4440623d375SPeng Fan #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4 4450623d375SPeng Fan #define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4) 4460623d375SPeng Fan 4473a217731SFabio Estevam /* GPR1 bitfields */ 448d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) 449d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) 450d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) 451d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) 452d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) 453d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_DPI_OFF BIT(24) 454d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) 4553a217731SFabio Estevam #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 4563a217731SFabio Estevam #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) 457d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) 458d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) 459d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) 460d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) 461d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16) 462d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_USB_EXP_MODE BIT(15) 463d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_INT BIT(14) 4644a4d3a7dSHeiko Schocher #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 4654a4d3a7dSHeiko Schocher #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) 466d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_GINT BIT(12) 467d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10) 468d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10) 469d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10) 470d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) 471d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ACT_CS3 BIT(9) 472d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7) 473d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ACT_CS2 BIT(6) 474d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4) 475d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ACT_CS1 BIT(3) 476d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS0_OFFSET (1) 477d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1) 478d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ACT_CS0 BIT(0) 4793a217731SFabio Estevam 480a83e1b7bSEric Nelson /* GPR3 bitfields */ 481a83e1b7bSEric Nelson #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 482a83e1b7bSEric Nelson #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) 483a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 484a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) 485a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 486a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) 487a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 488a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) 489a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 490a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) 491a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 492a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) 493a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 494a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) 495a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 496a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) 497a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 498a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) 499a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 500a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) 501a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 502a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) 503a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 504a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) 505a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 506a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) 507a83e1b7bSEric Nelson #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 508a83e1b7bSEric Nelson #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) 509a83e1b7bSEric Nelson 510a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 511a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 512a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 513a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 514a83e1b7bSEric Nelson 515a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 516a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) 517a83e1b7bSEric Nelson 518a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 519a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) 520a83e1b7bSEric Nelson 521a83e1b7bSEric Nelson #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 522a83e1b7bSEric Nelson #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) 523a83e1b7bSEric Nelson 524a83e1b7bSEric Nelson #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 525a83e1b7bSEric Nelson #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) 526a83e1b7bSEric Nelson 527d62f2f8cSHeiko Schocher /* gpr12 bitfields */ 528d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27) 529d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26) 530d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25) 531d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24) 532d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12) 533d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10) 534d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) 535a83e1b7bSEric Nelson 536de710a14SEric Nelson struct iomuxc { 537bc32fc69SPeng Fan #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) 538aeadf065SFabio Estevam u8 reserved[0x4000]; 539aeadf065SFabio Estevam #endif 540de710a14SEric Nelson u32 gpr[14]; 541de710a14SEric Nelson }; 542de710a14SEric Nelson 543ac17dcf6SFabio Estevam struct gpc { 544ac17dcf6SFabio Estevam u32 cntr; 545ac17dcf6SFabio Estevam u32 pgr; 546ac17dcf6SFabio Estevam u32 imr1; 547ac17dcf6SFabio Estevam u32 imr2; 548ac17dcf6SFabio Estevam u32 imr3; 549ac17dcf6SFabio Estevam u32 imr4; 550ac17dcf6SFabio Estevam u32 isr1; 551ac17dcf6SFabio Estevam u32 isr2; 552ac17dcf6SFabio Estevam u32 isr3; 553ac17dcf6SFabio Estevam u32 isr4; 554ac17dcf6SFabio Estevam }; 555ac17dcf6SFabio Estevam 556de710a14SEric Nelson #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 557de710a14SEric Nelson #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) 558de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 559de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) 560de710a14SEric Nelson 561de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 562de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 563de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 564de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 565de710a14SEric Nelson #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 566de710a14SEric Nelson #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 567de710a14SEric Nelson 568de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 569de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 570de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 571de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 572de710a14SEric Nelson 573de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 574de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 575de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 576de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 577de710a14SEric Nelson 578de710a14SEric Nelson #define IOMUXC_GPR2_BITMAP_SPWG 0 579de710a14SEric Nelson #define IOMUXC_GPR2_BITMAP_JEIDA 1 580de710a14SEric Nelson 581de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 582de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 583de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 584de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 585de710a14SEric Nelson 586de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_18 0 587de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_24 1 588de710a14SEric Nelson 589de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 590de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 591de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 592de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 593de710a14SEric Nelson 594de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 595de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 596de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 597de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 598de710a14SEric Nelson 599de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 600de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 601de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 602de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 603de710a14SEric Nelson 604de710a14SEric Nelson #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 605de710a14SEric Nelson #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) 606de710a14SEric Nelson 607de710a14SEric Nelson #define IOMUXC_GPR2_MODE_DISABLED 0 608de710a14SEric Nelson #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 6097aa1e8bbSPierre Aubert #define IOMUXC_GPR2_MODE_ENABLED_DI1 3 610de710a14SEric Nelson 611de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 612de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 613de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 614de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 615de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 616de710a14SEric Nelson 617de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 618de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 619de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 620de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 621de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 622de710a14SEric Nelson 623d5c37c9cSEric Nelson /* ECSPI registers */ 624d5c37c9cSEric Nelson struct cspi_regs { 625d5c37c9cSEric Nelson u32 rxdata; 626d5c37c9cSEric Nelson u32 txdata; 627d5c37c9cSEric Nelson u32 ctrl; 628d5c37c9cSEric Nelson u32 cfg; 629d5c37c9cSEric Nelson u32 intr; 630d5c37c9cSEric Nelson u32 dma; 631d5c37c9cSEric Nelson u32 stat; 632d5c37c9cSEric Nelson u32 period; 633d5c37c9cSEric Nelson }; 634d5c37c9cSEric Nelson 635d5c37c9cSEric Nelson /* 636d5c37c9cSEric Nelson * CSPI register definitions 637d5c37c9cSEric Nelson */ 638d5c37c9cSEric Nelson #define MXC_ECSPI 639d5c37c9cSEric Nelson #define MXC_CSPICTRL_EN (1 << 0) 640d5c37c9cSEric Nelson #define MXC_CSPICTRL_MODE (1 << 1) 641d5c37c9cSEric Nelson #define MXC_CSPICTRL_XCH (1 << 2) 6420f1411bcSFabio Estevam #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 643d5c37c9cSEric Nelson #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 644d5c37c9cSEric Nelson #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 645d5c37c9cSEric Nelson #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 646d5c37c9cSEric Nelson #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 647d5c37c9cSEric Nelson #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 648d5c37c9cSEric Nelson #define MXC_CSPICTRL_MAXBITS 0xfff 649d5c37c9cSEric Nelson #define MXC_CSPICTRL_TC (1 << 7) 650d5c37c9cSEric Nelson #define MXC_CSPICTRL_RXOVF (1 << 6) 651d5c37c9cSEric Nelson #define MXC_CSPIPERIOD_32KHZ (1 << 15) 652d5c37c9cSEric Nelson #define MAX_SPI_BYTES 32 653a0ae0091SHeiko Schocher #define SPI_MAX_NUM 4 654d5c37c9cSEric Nelson 655d5c37c9cSEric Nelson /* Bit position inside CTRL register to be associated with SS */ 656d5c37c9cSEric Nelson #define MXC_CSPICTRL_CHAN 18 657d5c37c9cSEric Nelson 658d5c37c9cSEric Nelson /* Bit position inside CON register to be associated with SS */ 659d7cbcc76SMarkus Niebel #define MXC_CSPICON_PHA 0 /* SCLK phase control */ 660d7cbcc76SMarkus Niebel #define MXC_CSPICON_POL 4 /* SCLK polarity */ 661d7cbcc76SMarkus Niebel #define MXC_CSPICON_SSPOL 12 /* SS polarity */ 662d7cbcc76SMarkus Niebel #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 663bc32fc69SPeng Fan #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) 66425b4aa14SFabio Estevam #define MXC_SPI_BASE_ADDRESSES \ 66525b4aa14SFabio Estevam ECSPI1_BASE_ADDR, \ 66625b4aa14SFabio Estevam ECSPI2_BASE_ADDR, \ 66725b4aa14SFabio Estevam ECSPI3_BASE_ADDR, \ 66825b4aa14SFabio Estevam ECSPI4_BASE_ADDR 66925b4aa14SFabio Estevam #else 670d5c37c9cSEric Nelson #define MXC_SPI_BASE_ADDRESSES \ 671d5c37c9cSEric Nelson ECSPI1_BASE_ADDR, \ 672d5c37c9cSEric Nelson ECSPI2_BASE_ADDR, \ 673d5c37c9cSEric Nelson ECSPI3_BASE_ADDR, \ 674d5c37c9cSEric Nelson ECSPI4_BASE_ADDR, \ 675d5c37c9cSEric Nelson ECSPI5_BASE_ADDR 67625b4aa14SFabio Estevam #endif 677d5c37c9cSEric Nelson 6788f3ff11cSBenoît Thébaudeau struct ocotp_regs { 67923608e23SJason Liu u32 ctrl; 68023608e23SJason Liu u32 ctrl_set; 68123608e23SJason Liu u32 ctrl_clr; 68223608e23SJason Liu u32 ctrl_tog; 68323608e23SJason Liu u32 timing; 68423608e23SJason Liu u32 rsvd0[3]; 68523608e23SJason Liu u32 data; 68623608e23SJason Liu u32 rsvd1[3]; 68723608e23SJason Liu u32 read_ctrl; 68823608e23SJason Liu u32 rsvd2[3]; 6898f3ff11cSBenoît Thébaudeau u32 read_fuse_data; 69023608e23SJason Liu u32 rsvd3[3]; 6918f3ff11cSBenoît Thébaudeau u32 sw_sticky; 69223608e23SJason Liu u32 rsvd4[3]; 69323608e23SJason Liu u32 scs; 69423608e23SJason Liu u32 scs_set; 69523608e23SJason Liu u32 scs_clr; 69623608e23SJason Liu u32 scs_tog; 69723608e23SJason Liu u32 crc_addr; 69823608e23SJason Liu u32 rsvd5[3]; 69923608e23SJason Liu u32 crc_value; 70023608e23SJason Liu u32 rsvd6[3]; 70123608e23SJason Liu u32 version; 702bd2e27c0SJason Liu u32 rsvd7[0xdb]; 70323608e23SJason Liu 7047296a023SPeng Fan /* fuse banks */ 70523608e23SJason Liu struct fuse_bank { 70623608e23SJason Liu u32 fuse_regs[0x20]; 7077296a023SPeng Fan } bank[0]; 70823608e23SJason Liu }; 70923608e23SJason Liu 7106adbd302SBenoît Thébaudeau struct fuse_bank0_regs { 7116adbd302SBenoît Thébaudeau u32 lock; 7126adbd302SBenoît Thébaudeau u32 rsvd0[3]; 7136adbd302SBenoît Thébaudeau u32 uid_low; 7146adbd302SBenoît Thébaudeau u32 rsvd1[3]; 7156adbd302SBenoît Thébaudeau u32 uid_high; 716b83c709eSStefano Babic u32 rsvd2[3]; 7171730af1bSPeng Fan u32 cfg2; 7181730af1bSPeng Fan u32 rsvd3[3]; 7191730af1bSPeng Fan u32 cfg3; 7201730af1bSPeng Fan u32 rsvd4[3]; 7211730af1bSPeng Fan u32 cfg4; 7221730af1bSPeng Fan u32 rsvd5[3]; 723b83c709eSStefano Babic u32 cfg5; 724b83c709eSStefano Babic u32 rsvd6[3]; 7251730af1bSPeng Fan u32 cfg6; 7261730af1bSPeng Fan u32 rsvd7[3]; 7276adbd302SBenoît Thébaudeau }; 7286adbd302SBenoît Thébaudeau 729d43e0ab4STim Harvey struct fuse_bank1_regs { 730d43e0ab4STim Harvey u32 mem0; 731d43e0ab4STim Harvey u32 rsvd0[3]; 732d43e0ab4STim Harvey u32 mem1; 733d43e0ab4STim Harvey u32 rsvd1[3]; 734d43e0ab4STim Harvey u32 mem2; 735d43e0ab4STim Harvey u32 rsvd2[3]; 736d43e0ab4STim Harvey u32 mem3; 737d43e0ab4STim Harvey u32 rsvd3[3]; 738d43e0ab4STim Harvey u32 mem4; 739d43e0ab4STim Harvey u32 rsvd4[3]; 740d43e0ab4STim Harvey u32 ana0; 741d43e0ab4STim Harvey u32 rsvd5[3]; 742d43e0ab4STim Harvey u32 ana1; 743d43e0ab4STim Harvey u32 rsvd6[3]; 744d43e0ab4STim Harvey u32 ana2; 745d43e0ab4STim Harvey u32 rsvd7[3]; 746d43e0ab4STim Harvey }; 747d43e0ab4STim Harvey 74805d54b82SFabio Estevam struct fuse_bank4_regs { 74905d54b82SFabio Estevam u32 sjc_resp_low; 75005d54b82SFabio Estevam u32 rsvd0[3]; 75105d54b82SFabio Estevam u32 sjc_resp_high; 75205d54b82SFabio Estevam u32 rsvd1[3]; 753d4d1dd67SYe Li u32 mac_addr0; 75405d54b82SFabio Estevam u32 rsvd2[3]; 755d4d1dd67SYe Li u32 mac_addr1; 75605d54b82SFabio Estevam u32 rsvd3[3]; 757d4d1dd67SYe Li u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/ 75805d54b82SFabio Estevam u32 rsvd4[7]; 75905d54b82SFabio Estevam u32 gp1; 760bc32fc69SPeng Fan u32 rsvd5[3]; 761bc32fc69SPeng Fan u32 gp2; 762bc32fc69SPeng Fan u32 rsvd6[3]; 76305d54b82SFabio Estevam }; 76423608e23SJason Liu 765f2f77458SJason Liu struct aipstz_regs { 766f2f77458SJason Liu u32 mprot0; 767f2f77458SJason Liu u32 mprot1; 768f2f77458SJason Liu u32 rsvd[0xe]; 769f2f77458SJason Liu u32 opacr0; 770f2f77458SJason Liu u32 opacr1; 771f2f77458SJason Liu u32 opacr2; 772f2f77458SJason Liu u32 opacr3; 773f2f77458SJason Liu u32 opacr4; 774f2f77458SJason Liu }; 775f2f77458SJason Liu 776a7683867SFabio Estevam struct anatop_regs { 777a7683867SFabio Estevam u32 pll_sys; /* 0x000 */ 778a7683867SFabio Estevam u32 pll_sys_set; /* 0x004 */ 779a7683867SFabio Estevam u32 pll_sys_clr; /* 0x008 */ 780a7683867SFabio Estevam u32 pll_sys_tog; /* 0x00c */ 781a7683867SFabio Estevam u32 usb1_pll_480_ctrl; /* 0x010 */ 782a7683867SFabio Estevam u32 usb1_pll_480_ctrl_set; /* 0x014 */ 783a7683867SFabio Estevam u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 784a7683867SFabio Estevam u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 785a7683867SFabio Estevam u32 usb2_pll_480_ctrl; /* 0x020 */ 786a7683867SFabio Estevam u32 usb2_pll_480_ctrl_set; /* 0x024 */ 787a7683867SFabio Estevam u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 788a7683867SFabio Estevam u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 789a7683867SFabio Estevam u32 pll_528; /* 0x030 */ 790a7683867SFabio Estevam u32 pll_528_set; /* 0x034 */ 791a7683867SFabio Estevam u32 pll_528_clr; /* 0x038 */ 792a7683867SFabio Estevam u32 pll_528_tog; /* 0x03c */ 793a7683867SFabio Estevam u32 pll_528_ss; /* 0x040 */ 794a7683867SFabio Estevam u32 rsvd0[3]; 795a7683867SFabio Estevam u32 pll_528_num; /* 0x050 */ 796a7683867SFabio Estevam u32 rsvd1[3]; 797a7683867SFabio Estevam u32 pll_528_denom; /* 0x060 */ 798a7683867SFabio Estevam u32 rsvd2[3]; 799a7683867SFabio Estevam u32 pll_audio; /* 0x070 */ 800a7683867SFabio Estevam u32 pll_audio_set; /* 0x074 */ 801a7683867SFabio Estevam u32 pll_audio_clr; /* 0x078 */ 802a7683867SFabio Estevam u32 pll_audio_tog; /* 0x07c */ 803a7683867SFabio Estevam u32 pll_audio_num; /* 0x080 */ 804a7683867SFabio Estevam u32 rsvd3[3]; 805a7683867SFabio Estevam u32 pll_audio_denom; /* 0x090 */ 806a7683867SFabio Estevam u32 rsvd4[3]; 807a7683867SFabio Estevam u32 pll_video; /* 0x0a0 */ 808a7683867SFabio Estevam u32 pll_video_set; /* 0x0a4 */ 809a7683867SFabio Estevam u32 pll_video_clr; /* 0x0a8 */ 810a7683867SFabio Estevam u32 pll_video_tog; /* 0x0ac */ 811a7683867SFabio Estevam u32 pll_video_num; /* 0x0b0 */ 812a7683867SFabio Estevam u32 rsvd5[3]; 813a7683867SFabio Estevam u32 pll_video_denom; /* 0x0c0 */ 814a7683867SFabio Estevam u32 rsvd6[3]; 815a7683867SFabio Estevam u32 pll_mlb; /* 0x0d0 */ 816a7683867SFabio Estevam u32 pll_mlb_set; /* 0x0d4 */ 817a7683867SFabio Estevam u32 pll_mlb_clr; /* 0x0d8 */ 818a7683867SFabio Estevam u32 pll_mlb_tog; /* 0x0dc */ 819a7683867SFabio Estevam u32 pll_enet; /* 0x0e0 */ 820a7683867SFabio Estevam u32 pll_enet_set; /* 0x0e4 */ 821a7683867SFabio Estevam u32 pll_enet_clr; /* 0x0e8 */ 822a7683867SFabio Estevam u32 pll_enet_tog; /* 0x0ec */ 823a7683867SFabio Estevam u32 pfd_480; /* 0x0f0 */ 824a7683867SFabio Estevam u32 pfd_480_set; /* 0x0f4 */ 825a7683867SFabio Estevam u32 pfd_480_clr; /* 0x0f8 */ 826a7683867SFabio Estevam u32 pfd_480_tog; /* 0x0fc */ 827a7683867SFabio Estevam u32 pfd_528; /* 0x100 */ 828a7683867SFabio Estevam u32 pfd_528_set; /* 0x104 */ 829a7683867SFabio Estevam u32 pfd_528_clr; /* 0x108 */ 830a7683867SFabio Estevam u32 pfd_528_tog; /* 0x10c */ 831a7683867SFabio Estevam u32 reg_1p1; /* 0x110 */ 832a7683867SFabio Estevam u32 reg_1p1_set; /* 0x114 */ 833a7683867SFabio Estevam u32 reg_1p1_clr; /* 0x118 */ 834a7683867SFabio Estevam u32 reg_1p1_tog; /* 0x11c */ 835a7683867SFabio Estevam u32 reg_3p0; /* 0x120 */ 836a7683867SFabio Estevam u32 reg_3p0_set; /* 0x124 */ 837a7683867SFabio Estevam u32 reg_3p0_clr; /* 0x128 */ 838a7683867SFabio Estevam u32 reg_3p0_tog; /* 0x12c */ 839a7683867SFabio Estevam u32 reg_2p5; /* 0x130 */ 840a7683867SFabio Estevam u32 reg_2p5_set; /* 0x134 */ 841a7683867SFabio Estevam u32 reg_2p5_clr; /* 0x138 */ 842a7683867SFabio Estevam u32 reg_2p5_tog; /* 0x13c */ 843a7683867SFabio Estevam u32 reg_core; /* 0x140 */ 844a7683867SFabio Estevam u32 reg_core_set; /* 0x144 */ 845a7683867SFabio Estevam u32 reg_core_clr; /* 0x148 */ 846a7683867SFabio Estevam u32 reg_core_tog; /* 0x14c */ 847a7683867SFabio Estevam u32 ana_misc0; /* 0x150 */ 848a7683867SFabio Estevam u32 ana_misc0_set; /* 0x154 */ 849a7683867SFabio Estevam u32 ana_misc0_clr; /* 0x158 */ 850a7683867SFabio Estevam u32 ana_misc0_tog; /* 0x15c */ 851a7683867SFabio Estevam u32 ana_misc1; /* 0x160 */ 852a7683867SFabio Estevam u32 ana_misc1_set; /* 0x164 */ 853a7683867SFabio Estevam u32 ana_misc1_clr; /* 0x168 */ 854a7683867SFabio Estevam u32 ana_misc1_tog; /* 0x16c */ 855a7683867SFabio Estevam u32 ana_misc2; /* 0x170 */ 856a7683867SFabio Estevam u32 ana_misc2_set; /* 0x174 */ 857a7683867SFabio Estevam u32 ana_misc2_clr; /* 0x178 */ 858a7683867SFabio Estevam u32 ana_misc2_tog; /* 0x17c */ 859a7683867SFabio Estevam u32 tempsense0; /* 0x180 */ 860a7683867SFabio Estevam u32 tempsense0_set; /* 0x184 */ 861a7683867SFabio Estevam u32 tempsense0_clr; /* 0x188 */ 862a7683867SFabio Estevam u32 tempsense0_tog; /* 0x18c */ 863a7683867SFabio Estevam u32 tempsense1; /* 0x190 */ 864a7683867SFabio Estevam u32 tempsense1_set; /* 0x194 */ 865a7683867SFabio Estevam u32 tempsense1_clr; /* 0x198 */ 866a7683867SFabio Estevam u32 tempsense1_tog; /* 0x19c */ 867a7683867SFabio Estevam u32 usb1_vbus_detect; /* 0x1a0 */ 868a7683867SFabio Estevam u32 usb1_vbus_detect_set; /* 0x1a4 */ 869a7683867SFabio Estevam u32 usb1_vbus_detect_clr; /* 0x1a8 */ 870a7683867SFabio Estevam u32 usb1_vbus_detect_tog; /* 0x1ac */ 871a7683867SFabio Estevam u32 usb1_chrg_detect; /* 0x1b0 */ 872a7683867SFabio Estevam u32 usb1_chrg_detect_set; /* 0x1b4 */ 873a7683867SFabio Estevam u32 usb1_chrg_detect_clr; /* 0x1b8 */ 874a7683867SFabio Estevam u32 usb1_chrg_detect_tog; /* 0x1bc */ 875a7683867SFabio Estevam u32 usb1_vbus_det_stat; /* 0x1c0 */ 876a7683867SFabio Estevam u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 877a7683867SFabio Estevam u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 878a7683867SFabio Estevam u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 879a7683867SFabio Estevam u32 usb1_chrg_det_stat; /* 0x1d0 */ 880a7683867SFabio Estevam u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 881a7683867SFabio Estevam u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 882a7683867SFabio Estevam u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 883a7683867SFabio Estevam u32 usb1_loopback; /* 0x1e0 */ 884a7683867SFabio Estevam u32 usb1_loopback_set; /* 0x1e4 */ 885a7683867SFabio Estevam u32 usb1_loopback_clr; /* 0x1e8 */ 886a7683867SFabio Estevam u32 usb1_loopback_tog; /* 0x1ec */ 887a7683867SFabio Estevam u32 usb1_misc; /* 0x1f0 */ 888a7683867SFabio Estevam u32 usb1_misc_set; /* 0x1f4 */ 889a7683867SFabio Estevam u32 usb1_misc_clr; /* 0x1f8 */ 890a7683867SFabio Estevam u32 usb1_misc_tog; /* 0x1fc */ 891a7683867SFabio Estevam u32 usb2_vbus_detect; /* 0x200 */ 892a7683867SFabio Estevam u32 usb2_vbus_detect_set; /* 0x204 */ 893a7683867SFabio Estevam u32 usb2_vbus_detect_clr; /* 0x208 */ 894a7683867SFabio Estevam u32 usb2_vbus_detect_tog; /* 0x20c */ 895a7683867SFabio Estevam u32 usb2_chrg_detect; /* 0x210 */ 896a7683867SFabio Estevam u32 usb2_chrg_detect_set; /* 0x214 */ 897a7683867SFabio Estevam u32 usb2_chrg_detect_clr; /* 0x218 */ 898a7683867SFabio Estevam u32 usb2_chrg_detect_tog; /* 0x21c */ 899a7683867SFabio Estevam u32 usb2_vbus_det_stat; /* 0x220 */ 900a7683867SFabio Estevam u32 usb2_vbus_det_stat_set; /* 0x224 */ 901a7683867SFabio Estevam u32 usb2_vbus_det_stat_clr; /* 0x228 */ 902a7683867SFabio Estevam u32 usb2_vbus_det_stat_tog; /* 0x22c */ 903a7683867SFabio Estevam u32 usb2_chrg_det_stat; /* 0x230 */ 904a7683867SFabio Estevam u32 usb2_chrg_det_stat_set; /* 0x234 */ 905a7683867SFabio Estevam u32 usb2_chrg_det_stat_clr; /* 0x238 */ 906a7683867SFabio Estevam u32 usb2_chrg_det_stat_tog; /* 0x23c */ 907a7683867SFabio Estevam u32 usb2_loopback; /* 0x240 */ 908a7683867SFabio Estevam u32 usb2_loopback_set; /* 0x244 */ 909a7683867SFabio Estevam u32 usb2_loopback_clr; /* 0x248 */ 910a7683867SFabio Estevam u32 usb2_loopback_tog; /* 0x24c */ 911a7683867SFabio Estevam u32 usb2_misc; /* 0x250 */ 912a7683867SFabio Estevam u32 usb2_misc_set; /* 0x254 */ 913a7683867SFabio Estevam u32 usb2_misc_clr; /* 0x258 */ 914a7683867SFabio Estevam u32 usb2_misc_tog; /* 0x25c */ 915a7683867SFabio Estevam u32 digprog; /* 0x260 */ 91620332a06STroy Kisky u32 reserved1[7]; 91720332a06STroy Kisky u32 digprog_sololite; /* 0x280 */ 918a7683867SFabio Estevam }; 919a7683867SFabio Estevam 9203fc4176dSEric Nelson #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) 9213fc4176dSEric Nelson #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) 9223fc4176dSEric Nelson #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) 9233fc4176dSEric Nelson #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) 9243fc4176dSEric Nelson #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) 9253fc4176dSEric Nelson #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) 926e66ad6e7SEric Nelson 92776c91e66SFabio Estevam struct wdog_regs { 92876c91e66SFabio Estevam u16 wcr; /* Control */ 92976c91e66SFabio Estevam u16 wsr; /* Service */ 93076c91e66SFabio Estevam u16 wrsr; /* Reset Status */ 93176c91e66SFabio Estevam u16 wicr; /* Interrupt Control */ 93276c91e66SFabio Estevam u16 wmcr; /* Miscellaneous Control */ 93376c91e66SFabio Estevam }; 93476c91e66SFabio Estevam 935aafe4020SHeiko Schocher #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) 936aafe4020SHeiko Schocher #define PWMCR_DOZEEN (1 << 24) 937aafe4020SHeiko Schocher #define PWMCR_WAITEN (1 << 23) 938aafe4020SHeiko Schocher #define PWMCR_DBGEN (1 << 22) 939aafe4020SHeiko Schocher #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) 940aafe4020SHeiko Schocher #define PWMCR_CLKSRC_IPG (1 << 16) 941aafe4020SHeiko Schocher #define PWMCR_EN (1 << 0) 942aafe4020SHeiko Schocher 943aafe4020SHeiko Schocher struct pwm_regs { 944aafe4020SHeiko Schocher u32 cr; 945aafe4020SHeiko Schocher u32 sr; 946aafe4020SHeiko Schocher u32 ir; 947aafe4020SHeiko Schocher u32 sar; 948aafe4020SHeiko Schocher u32 pr; 949aafe4020SHeiko Schocher u32 cnr; 950aafe4020SHeiko Schocher }; 95123608e23SJason Liu #endif /* __ASSEMBLER__*/ 95223608e23SJason Liu #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 953