123608e23SJason Liu /* 223608e23SJason Liu * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 323608e23SJason Liu * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 523608e23SJason Liu */ 623608e23SJason Liu 723608e23SJason Liu #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 823608e23SJason Liu #define __ASM_ARCH_MX6_IMX_REGS_H__ 923608e23SJason Liu 108e99ecd7SBenoît Thébaudeau #define ARCH_MXC 118e99ecd7SBenoît Thébaudeau 12c415919dSEric Nelson #define CONFIG_SYS_CACHELINE_SIZE 32 13c415919dSEric Nelson 1423608e23SJason Liu #define ROMCP_ARB_BASE_ADDR 0x00000000 1523608e23SJason Liu #define ROMCP_ARB_END_ADDR 0x000FFFFF 1625b4aa14SFabio Estevam 1725b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 1825b4aa14SFabio Estevam #define GPU_2D_ARB_BASE_ADDR 0x02200000 1925b4aa14SFabio Estevam #define GPU_2D_ARB_END_ADDR 0x02203FFF 2025b4aa14SFabio Estevam #define OPENVG_ARB_BASE_ADDR 0x02204000 2125b4aa14SFabio Estevam #define OPENVG_ARB_END_ADDR 0x02207FFF 2225b4aa14SFabio Estevam #else 2323608e23SJason Liu #define CAAM_ARB_BASE_ADDR 0x00100000 2423608e23SJason Liu #define CAAM_ARB_END_ADDR 0x00103FFF 2523608e23SJason Liu #define APBH_DMA_ARB_BASE_ADDR 0x00110000 2623608e23SJason Liu #define APBH_DMA_ARB_END_ADDR 0x00117FFF 2723608e23SJason Liu #define HDMI_ARB_BASE_ADDR 0x00120000 2823608e23SJason Liu #define HDMI_ARB_END_ADDR 0x00128FFF 2923608e23SJason Liu #define GPU_3D_ARB_BASE_ADDR 0x00130000 3023608e23SJason Liu #define GPU_3D_ARB_END_ADDR 0x00133FFF 3123608e23SJason Liu #define GPU_2D_ARB_BASE_ADDR 0x00134000 3223608e23SJason Liu #define GPU_2D_ARB_END_ADDR 0x00137FFF 3323608e23SJason Liu #define DTCP_ARB_BASE_ADDR 0x00138000 3423608e23SJason Liu #define DTCP_ARB_END_ADDR 0x0013BFFF 3525b4aa14SFabio Estevam #endif /* CONFIG_MX6SL */ 3699193e30SStefan Roese 3799193e30SStefan Roese #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 3899193e30SStefan Roese #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 3999193e30SStefan Roese #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 4099193e30SStefan Roese 4123608e23SJason Liu /* GPV - PL301 configuration ports */ 4225b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 4325b4aa14SFabio Estevam #define GPV2_BASE_ADDR 0x00D00000 4425b4aa14SFabio Estevam #else 4523608e23SJason Liu #define GPV2_BASE_ADDR 0x00200000 4625b4aa14SFabio Estevam #endif 4725b4aa14SFabio Estevam 4823608e23SJason Liu #define GPV3_BASE_ADDR 0x00300000 4923608e23SJason Liu #define GPV4_BASE_ADDR 0x00800000 5023608e23SJason Liu #define IRAM_BASE_ADDR 0x00900000 5123608e23SJason Liu #define SCU_BASE_ADDR 0x00A00000 5223608e23SJason Liu #define IC_INTERFACES_BASE_ADDR 0x00A00100 5323608e23SJason Liu #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 5423608e23SJason Liu #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 5523608e23SJason Liu #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 5623608e23SJason Liu #define GPV0_BASE_ADDR 0x00B00000 5723608e23SJason Liu #define GPV1_BASE_ADDR 0x00C00000 5823608e23SJason Liu #define PCIE_ARB_BASE_ADDR 0x01000000 5923608e23SJason Liu #define PCIE_ARB_END_ADDR 0x01FFFFFF 6023608e23SJason Liu 6123608e23SJason Liu #define AIPS1_ARB_BASE_ADDR 0x02000000 6223608e23SJason Liu #define AIPS1_ARB_END_ADDR 0x020FFFFF 6323608e23SJason Liu #define AIPS2_ARB_BASE_ADDR 0x02100000 6423608e23SJason Liu #define AIPS2_ARB_END_ADDR 0x021FFFFF 6523608e23SJason Liu #define SATA_ARB_BASE_ADDR 0x02200000 6623608e23SJason Liu #define SATA_ARB_END_ADDR 0x02203FFF 6723608e23SJason Liu #define OPENVG_ARB_BASE_ADDR 0x02204000 6823608e23SJason Liu #define OPENVG_ARB_END_ADDR 0x02207FFF 6923608e23SJason Liu #define HSI_ARB_BASE_ADDR 0x02208000 7023608e23SJason Liu #define HSI_ARB_END_ADDR 0x0220BFFF 7123608e23SJason Liu #define IPU1_ARB_BASE_ADDR 0x02400000 7223608e23SJason Liu #define IPU1_ARB_END_ADDR 0x027FFFFF 7323608e23SJason Liu #define IPU2_ARB_BASE_ADDR 0x02800000 7423608e23SJason Liu #define IPU2_ARB_END_ADDR 0x02BFFFFF 7523608e23SJason Liu #define WEIM_ARB_BASE_ADDR 0x08000000 7623608e23SJason Liu #define WEIM_ARB_END_ADDR 0x0FFFFFFF 7723608e23SJason Liu 7825b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 7925b4aa14SFabio Estevam #define MMDC0_ARB_BASE_ADDR 0x80000000 8025b4aa14SFabio Estevam #define MMDC0_ARB_END_ADDR 0xFFFFFFFF 8125b4aa14SFabio Estevam #define MMDC1_ARB_BASE_ADDR 0xC0000000 8225b4aa14SFabio Estevam #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 8325b4aa14SFabio Estevam #else 8423608e23SJason Liu #define MMDC0_ARB_BASE_ADDR 0x10000000 8523608e23SJason Liu #define MMDC0_ARB_END_ADDR 0x7FFFFFFF 8623608e23SJason Liu #define MMDC1_ARB_BASE_ADDR 0x80000000 8723608e23SJason Liu #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 8825b4aa14SFabio Estevam #endif 8923608e23SJason Liu 9005d4df1dSFabio Estevam #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR 9105d4df1dSFabio Estevam #define IPU_SOC_OFFSET 0x00200000 9205d4df1dSFabio Estevam 9323608e23SJason Liu /* Defines for Blocks connected via AIPS (SkyBlue) */ 9423608e23SJason Liu #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 9523608e23SJason Liu #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 9623608e23SJason Liu #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 9723608e23SJason Liu #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 9823608e23SJason Liu 9923608e23SJason Liu #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 10023608e23SJason Liu #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 10123608e23SJason Liu #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 10223608e23SJason Liu #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 10323608e23SJason Liu #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 10425b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 10525b4aa14SFabio Estevam #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 10625b4aa14SFabio Estevam #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) 10725b4aa14SFabio Estevam #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 10825b4aa14SFabio Estevam #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 10925b4aa14SFabio Estevam #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 11025b4aa14SFabio Estevam #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 11125b4aa14SFabio Estevam #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 11225b4aa14SFabio Estevam #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) 11325b4aa14SFabio Estevam #else 11423608e23SJason Liu #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 11523608e23SJason Liu #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 11623608e23SJason Liu #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 11723608e23SJason Liu #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 11823608e23SJason Liu #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 11923608e23SJason Liu #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 12023608e23SJason Liu #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 12125b4aa14SFabio Estevam #endif 12225b4aa14SFabio Estevam 12323608e23SJason Liu #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 12423608e23SJason Liu #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 12523608e23SJason Liu #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 12623608e23SJason Liu 12723608e23SJason Liu #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 12823608e23SJason Liu #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 12923608e23SJason Liu #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 13023608e23SJason Liu #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 13123608e23SJason Liu #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 13223608e23SJason Liu #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 13323608e23SJason Liu #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 13423608e23SJason Liu #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 13523608e23SJason Liu #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 13623608e23SJason Liu #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 13723608e23SJason Liu #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 13823608e23SJason Liu #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 13923608e23SJason Liu #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 14023608e23SJason Liu #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 14123608e23SJason Liu #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 14223608e23SJason Liu #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 14323608e23SJason Liu #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 14423608e23SJason Liu #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 1453f467529SWolfgang Grandegger #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 1463f467529SWolfgang Grandegger #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 1473f467529SWolfgang Grandegger #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 14823608e23SJason Liu #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 14923608e23SJason Liu #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 15023608e23SJason Liu #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 15123608e23SJason Liu #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 15223608e23SJason Liu #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 15323608e23SJason Liu #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 15423608e23SJason Liu #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 15525b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 15625b4aa14SFabio Estevam #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 15725b4aa14SFabio Estevam #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 15825b4aa14SFabio Estevam #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 15925b4aa14SFabio Estevam #else 16023608e23SJason Liu #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 16123608e23SJason Liu #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 16223608e23SJason Liu #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 16325b4aa14SFabio Estevam #endif 16423608e23SJason Liu 16523608e23SJason Liu #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 16623608e23SJason Liu #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 16723608e23SJason Liu #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 16823608e23SJason Liu #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 16925b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 17025b4aa14SFabio Estevam #define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 17125b4aa14SFabio Estevam #define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 17225b4aa14SFabio Estevam #else 17323608e23SJason Liu #define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 17423608e23SJason Liu #define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 17525b4aa14SFabio Estevam #endif 17625b4aa14SFabio Estevam 17723608e23SJason Liu #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 17825b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 17925b4aa14SFabio Estevam #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 18025b4aa14SFabio Estevam #else 18123608e23SJason Liu #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 18225b4aa14SFabio Estevam #endif 18325b4aa14SFabio Estevam 18423608e23SJason Liu #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 18523608e23SJason Liu #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 18623608e23SJason Liu #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 18723608e23SJason Liu #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 18823608e23SJason Liu #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 18923608e23SJason Liu #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 19023608e23SJason Liu #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 19123608e23SJason Liu #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 19223608e23SJason Liu #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 19325b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 19425b4aa14SFabio Estevam #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 19525b4aa14SFabio Estevam #else 19623608e23SJason Liu #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 19725b4aa14SFabio Estevam #endif 19825b4aa14SFabio Estevam 19923608e23SJason Liu #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 20023608e23SJason Liu #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 20123608e23SJason Liu #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 20223608e23SJason Liu #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 20323608e23SJason Liu #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 20423608e23SJason Liu #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 20523608e23SJason Liu #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 20623608e23SJason Liu #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 20723608e23SJason Liu #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 20823608e23SJason Liu #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 20923608e23SJason Liu #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 21023608e23SJason Liu #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 21123608e23SJason Liu #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 21223608e23SJason Liu #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 21323608e23SJason Liu #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 21423608e23SJason Liu #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 21523608e23SJason Liu #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 21623608e23SJason Liu #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 21723608e23SJason Liu 21823608e23SJason Liu #define CHIP_REV_1_0 0x10 21923608e23SJason Liu #define IRAM_SIZE 0x00040000 22028774cbaSTroy Kisky #define FEC_QUIRK_ENET_MAC 22123608e23SJason Liu 22223608e23SJason Liu #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 22323608e23SJason Liu #include <asm/types.h> 22423608e23SJason Liu 225be252b65SFabio Estevam extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 22623608e23SJason Liu 22723608e23SJason Liu /* System Reset Controller (SRC) */ 22823608e23SJason Liu struct src { 22923608e23SJason Liu u32 scr; 23023608e23SJason Liu u32 sbmr1; 23123608e23SJason Liu u32 srsr; 23223608e23SJason Liu u32 reserved1[2]; 23323608e23SJason Liu u32 sisr; 23423608e23SJason Liu u32 simr; 23523608e23SJason Liu u32 sbmr2; 23623608e23SJason Liu u32 gpr1; 23723608e23SJason Liu u32 gpr2; 23823608e23SJason Liu u32 gpr3; 23923608e23SJason Liu u32 gpr4; 24023608e23SJason Liu u32 gpr5; 24123608e23SJason Liu u32 gpr6; 24223608e23SJason Liu u32 gpr7; 24323608e23SJason Liu u32 gpr8; 24423608e23SJason Liu u32 gpr9; 24523608e23SJason Liu u32 gpr10; 24623608e23SJason Liu }; 24723608e23SJason Liu 248a83e1b7bSEric Nelson /* GPR3 bitfields */ 249a83e1b7bSEric Nelson #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 250a83e1b7bSEric Nelson #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) 251a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 252a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) 253a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 254a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) 255a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 256a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) 257a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 258a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) 259a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 260a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) 261a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 262a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) 263a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 264a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) 265a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 266a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) 267a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 268a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) 269a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 270a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) 271a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 272a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) 273a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 274a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) 275a83e1b7bSEric Nelson #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 276a83e1b7bSEric Nelson #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) 277a83e1b7bSEric Nelson 278a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 279a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 280a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 281a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 282a83e1b7bSEric Nelson 283a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 284a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) 285a83e1b7bSEric Nelson 286a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 287a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) 288a83e1b7bSEric Nelson 289a83e1b7bSEric Nelson #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 290a83e1b7bSEric Nelson #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) 291a83e1b7bSEric Nelson 292a83e1b7bSEric Nelson #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 293a83e1b7bSEric Nelson #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) 294a83e1b7bSEric Nelson 295a83e1b7bSEric Nelson 296de710a14SEric Nelson struct iomuxc { 297de710a14SEric Nelson u32 gpr[14]; 298de710a14SEric Nelson u32 omux[5]; 299de710a14SEric Nelson /* mux and pad registers */ 300de710a14SEric Nelson }; 301de710a14SEric Nelson 302de710a14SEric Nelson #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 303de710a14SEric Nelson #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) 304de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 305de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) 306de710a14SEric Nelson 307de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 308de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 309de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 310de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 311de710a14SEric Nelson #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 312de710a14SEric Nelson #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 313de710a14SEric Nelson 314de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 315de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 316de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 317de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 318de710a14SEric Nelson 319de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 320de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 321de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 322de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 323de710a14SEric Nelson 324de710a14SEric Nelson #define IOMUXC_GPR2_BITMAP_SPWG 0 325de710a14SEric Nelson #define IOMUXC_GPR2_BITMAP_JEIDA 1 326de710a14SEric Nelson 327de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 328de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 329de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 330de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 331de710a14SEric Nelson 332de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_18 0 333de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_24 1 334de710a14SEric Nelson 335de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 336de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 337de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 338de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 339de710a14SEric Nelson 340de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 341de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 342de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 343de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 344de710a14SEric Nelson 345de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 346de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 347de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 348de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 349de710a14SEric Nelson 350de710a14SEric Nelson #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 351de710a14SEric Nelson #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) 352de710a14SEric Nelson 353de710a14SEric Nelson #define IOMUXC_GPR2_MODE_DISABLED 0 354de710a14SEric Nelson #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 3557aa1e8bbSPierre Aubert #define IOMUXC_GPR2_MODE_ENABLED_DI1 3 356de710a14SEric Nelson 357de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 358de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 359de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 360de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 361de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 362de710a14SEric Nelson 363de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 364de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 365de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 366de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 367de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 368de710a14SEric Nelson 369d5c37c9cSEric Nelson /* ECSPI registers */ 370d5c37c9cSEric Nelson struct cspi_regs { 371d5c37c9cSEric Nelson u32 rxdata; 372d5c37c9cSEric Nelson u32 txdata; 373d5c37c9cSEric Nelson u32 ctrl; 374d5c37c9cSEric Nelson u32 cfg; 375d5c37c9cSEric Nelson u32 intr; 376d5c37c9cSEric Nelson u32 dma; 377d5c37c9cSEric Nelson u32 stat; 378d5c37c9cSEric Nelson u32 period; 379d5c37c9cSEric Nelson }; 380d5c37c9cSEric Nelson 381d5c37c9cSEric Nelson /* 382d5c37c9cSEric Nelson * CSPI register definitions 383d5c37c9cSEric Nelson */ 384d5c37c9cSEric Nelson #define MXC_ECSPI 385d5c37c9cSEric Nelson #define MXC_CSPICTRL_EN (1 << 0) 386d5c37c9cSEric Nelson #define MXC_CSPICTRL_MODE (1 << 1) 387d5c37c9cSEric Nelson #define MXC_CSPICTRL_XCH (1 << 2) 3880f1411bcSFabio Estevam #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 389d5c37c9cSEric Nelson #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 390d5c37c9cSEric Nelson #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 391d5c37c9cSEric Nelson #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 392d5c37c9cSEric Nelson #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 393d5c37c9cSEric Nelson #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 394d5c37c9cSEric Nelson #define MXC_CSPICTRL_MAXBITS 0xfff 395d5c37c9cSEric Nelson #define MXC_CSPICTRL_TC (1 << 7) 396d5c37c9cSEric Nelson #define MXC_CSPICTRL_RXOVF (1 << 6) 397d5c37c9cSEric Nelson #define MXC_CSPIPERIOD_32KHZ (1 << 15) 398d5c37c9cSEric Nelson #define MAX_SPI_BYTES 32 399d5c37c9cSEric Nelson 400d5c37c9cSEric Nelson /* Bit position inside CTRL register to be associated with SS */ 401d5c37c9cSEric Nelson #define MXC_CSPICTRL_CHAN 18 402d5c37c9cSEric Nelson 403d5c37c9cSEric Nelson /* Bit position inside CON register to be associated with SS */ 404d5c37c9cSEric Nelson #define MXC_CSPICON_POL 4 405d5c37c9cSEric Nelson #define MXC_CSPICON_PHA 0 406d5c37c9cSEric Nelson #define MXC_CSPICON_SSPOL 12 40725b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 40825b4aa14SFabio Estevam #define MXC_SPI_BASE_ADDRESSES \ 40925b4aa14SFabio Estevam ECSPI1_BASE_ADDR, \ 41025b4aa14SFabio Estevam ECSPI2_BASE_ADDR, \ 41125b4aa14SFabio Estevam ECSPI3_BASE_ADDR, \ 41225b4aa14SFabio Estevam ECSPI4_BASE_ADDR 41325b4aa14SFabio Estevam #else 414d5c37c9cSEric Nelson #define MXC_SPI_BASE_ADDRESSES \ 415d5c37c9cSEric Nelson ECSPI1_BASE_ADDR, \ 416d5c37c9cSEric Nelson ECSPI2_BASE_ADDR, \ 417d5c37c9cSEric Nelson ECSPI3_BASE_ADDR, \ 418d5c37c9cSEric Nelson ECSPI4_BASE_ADDR, \ 419d5c37c9cSEric Nelson ECSPI5_BASE_ADDR 42025b4aa14SFabio Estevam #endif 421d5c37c9cSEric Nelson 4228f3ff11cSBenoît Thébaudeau struct ocotp_regs { 42323608e23SJason Liu u32 ctrl; 42423608e23SJason Liu u32 ctrl_set; 42523608e23SJason Liu u32 ctrl_clr; 42623608e23SJason Liu u32 ctrl_tog; 42723608e23SJason Liu u32 timing; 42823608e23SJason Liu u32 rsvd0[3]; 42923608e23SJason Liu u32 data; 43023608e23SJason Liu u32 rsvd1[3]; 43123608e23SJason Liu u32 read_ctrl; 43223608e23SJason Liu u32 rsvd2[3]; 4338f3ff11cSBenoît Thébaudeau u32 read_fuse_data; 43423608e23SJason Liu u32 rsvd3[3]; 4358f3ff11cSBenoît Thébaudeau u32 sw_sticky; 43623608e23SJason Liu u32 rsvd4[3]; 43723608e23SJason Liu u32 scs; 43823608e23SJason Liu u32 scs_set; 43923608e23SJason Liu u32 scs_clr; 44023608e23SJason Liu u32 scs_tog; 44123608e23SJason Liu u32 crc_addr; 44223608e23SJason Liu u32 rsvd5[3]; 44323608e23SJason Liu u32 crc_value; 44423608e23SJason Liu u32 rsvd6[3]; 44523608e23SJason Liu u32 version; 446bd2e27c0SJason Liu u32 rsvd7[0xdb]; 44723608e23SJason Liu 44823608e23SJason Liu struct fuse_bank { 44923608e23SJason Liu u32 fuse_regs[0x20]; 4508f3ff11cSBenoît Thébaudeau } bank[16]; 45123608e23SJason Liu }; 45223608e23SJason Liu 4536adbd302SBenoît Thébaudeau struct fuse_bank0_regs { 4546adbd302SBenoît Thébaudeau u32 lock; 4556adbd302SBenoît Thébaudeau u32 rsvd0[3]; 4566adbd302SBenoît Thébaudeau u32 uid_low; 4576adbd302SBenoît Thébaudeau u32 rsvd1[3]; 4586adbd302SBenoît Thébaudeau u32 uid_high; 4596adbd302SBenoît Thébaudeau u32 rsvd2[0x17]; 4606adbd302SBenoît Thébaudeau }; 4616adbd302SBenoît Thébaudeau 46223608e23SJason Liu struct fuse_bank4_regs { 46323608e23SJason Liu u32 sjc_resp_low; 46423608e23SJason Liu u32 rsvd0[3]; 46523608e23SJason Liu u32 sjc_resp_high; 46623608e23SJason Liu u32 rsvd1[3]; 46723608e23SJason Liu u32 mac_addr_low; 46823608e23SJason Liu u32 rsvd2[3]; 46923608e23SJason Liu u32 mac_addr_high; 4708f3ff11cSBenoît Thébaudeau u32 rsvd3[0xb]; 4718f3ff11cSBenoît Thébaudeau u32 gp1; 4726adbd302SBenoît Thébaudeau u32 rsvd4[3]; 4736adbd302SBenoît Thébaudeau u32 gp2; 4746adbd302SBenoît Thébaudeau u32 rsvd5[3]; 47523608e23SJason Liu }; 47623608e23SJason Liu 477f2f77458SJason Liu struct aipstz_regs { 478f2f77458SJason Liu u32 mprot0; 479f2f77458SJason Liu u32 mprot1; 480f2f77458SJason Liu u32 rsvd[0xe]; 481f2f77458SJason Liu u32 opacr0; 482f2f77458SJason Liu u32 opacr1; 483f2f77458SJason Liu u32 opacr2; 484f2f77458SJason Liu u32 opacr3; 485f2f77458SJason Liu u32 opacr4; 486f2f77458SJason Liu }; 487f2f77458SJason Liu 488a7683867SFabio Estevam struct anatop_regs { 489a7683867SFabio Estevam u32 pll_sys; /* 0x000 */ 490a7683867SFabio Estevam u32 pll_sys_set; /* 0x004 */ 491a7683867SFabio Estevam u32 pll_sys_clr; /* 0x008 */ 492a7683867SFabio Estevam u32 pll_sys_tog; /* 0x00c */ 493a7683867SFabio Estevam u32 usb1_pll_480_ctrl; /* 0x010 */ 494a7683867SFabio Estevam u32 usb1_pll_480_ctrl_set; /* 0x014 */ 495a7683867SFabio Estevam u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 496a7683867SFabio Estevam u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 497a7683867SFabio Estevam u32 usb2_pll_480_ctrl; /* 0x020 */ 498a7683867SFabio Estevam u32 usb2_pll_480_ctrl_set; /* 0x024 */ 499a7683867SFabio Estevam u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 500a7683867SFabio Estevam u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 501a7683867SFabio Estevam u32 pll_528; /* 0x030 */ 502a7683867SFabio Estevam u32 pll_528_set; /* 0x034 */ 503a7683867SFabio Estevam u32 pll_528_clr; /* 0x038 */ 504a7683867SFabio Estevam u32 pll_528_tog; /* 0x03c */ 505a7683867SFabio Estevam u32 pll_528_ss; /* 0x040 */ 506a7683867SFabio Estevam u32 rsvd0[3]; 507a7683867SFabio Estevam u32 pll_528_num; /* 0x050 */ 508a7683867SFabio Estevam u32 rsvd1[3]; 509a7683867SFabio Estevam u32 pll_528_denom; /* 0x060 */ 510a7683867SFabio Estevam u32 rsvd2[3]; 511a7683867SFabio Estevam u32 pll_audio; /* 0x070 */ 512a7683867SFabio Estevam u32 pll_audio_set; /* 0x074 */ 513a7683867SFabio Estevam u32 pll_audio_clr; /* 0x078 */ 514a7683867SFabio Estevam u32 pll_audio_tog; /* 0x07c */ 515a7683867SFabio Estevam u32 pll_audio_num; /* 0x080 */ 516a7683867SFabio Estevam u32 rsvd3[3]; 517a7683867SFabio Estevam u32 pll_audio_denom; /* 0x090 */ 518a7683867SFabio Estevam u32 rsvd4[3]; 519a7683867SFabio Estevam u32 pll_video; /* 0x0a0 */ 520a7683867SFabio Estevam u32 pll_video_set; /* 0x0a4 */ 521a7683867SFabio Estevam u32 pll_video_clr; /* 0x0a8 */ 522a7683867SFabio Estevam u32 pll_video_tog; /* 0x0ac */ 523a7683867SFabio Estevam u32 pll_video_num; /* 0x0b0 */ 524a7683867SFabio Estevam u32 rsvd5[3]; 525a7683867SFabio Estevam u32 pll_video_denom; /* 0x0c0 */ 526a7683867SFabio Estevam u32 rsvd6[3]; 527a7683867SFabio Estevam u32 pll_mlb; /* 0x0d0 */ 528a7683867SFabio Estevam u32 pll_mlb_set; /* 0x0d4 */ 529a7683867SFabio Estevam u32 pll_mlb_clr; /* 0x0d8 */ 530a7683867SFabio Estevam u32 pll_mlb_tog; /* 0x0dc */ 531a7683867SFabio Estevam u32 pll_enet; /* 0x0e0 */ 532a7683867SFabio Estevam u32 pll_enet_set; /* 0x0e4 */ 533a7683867SFabio Estevam u32 pll_enet_clr; /* 0x0e8 */ 534a7683867SFabio Estevam u32 pll_enet_tog; /* 0x0ec */ 535a7683867SFabio Estevam u32 pfd_480; /* 0x0f0 */ 536a7683867SFabio Estevam u32 pfd_480_set; /* 0x0f4 */ 537a7683867SFabio Estevam u32 pfd_480_clr; /* 0x0f8 */ 538a7683867SFabio Estevam u32 pfd_480_tog; /* 0x0fc */ 539a7683867SFabio Estevam u32 pfd_528; /* 0x100 */ 540a7683867SFabio Estevam u32 pfd_528_set; /* 0x104 */ 541a7683867SFabio Estevam u32 pfd_528_clr; /* 0x108 */ 542a7683867SFabio Estevam u32 pfd_528_tog; /* 0x10c */ 543a7683867SFabio Estevam u32 reg_1p1; /* 0x110 */ 544a7683867SFabio Estevam u32 reg_1p1_set; /* 0x114 */ 545a7683867SFabio Estevam u32 reg_1p1_clr; /* 0x118 */ 546a7683867SFabio Estevam u32 reg_1p1_tog; /* 0x11c */ 547a7683867SFabio Estevam u32 reg_3p0; /* 0x120 */ 548a7683867SFabio Estevam u32 reg_3p0_set; /* 0x124 */ 549a7683867SFabio Estevam u32 reg_3p0_clr; /* 0x128 */ 550a7683867SFabio Estevam u32 reg_3p0_tog; /* 0x12c */ 551a7683867SFabio Estevam u32 reg_2p5; /* 0x130 */ 552a7683867SFabio Estevam u32 reg_2p5_set; /* 0x134 */ 553a7683867SFabio Estevam u32 reg_2p5_clr; /* 0x138 */ 554a7683867SFabio Estevam u32 reg_2p5_tog; /* 0x13c */ 555a7683867SFabio Estevam u32 reg_core; /* 0x140 */ 556a7683867SFabio Estevam u32 reg_core_set; /* 0x144 */ 557a7683867SFabio Estevam u32 reg_core_clr; /* 0x148 */ 558a7683867SFabio Estevam u32 reg_core_tog; /* 0x14c */ 559a7683867SFabio Estevam u32 ana_misc0; /* 0x150 */ 560a7683867SFabio Estevam u32 ana_misc0_set; /* 0x154 */ 561a7683867SFabio Estevam u32 ana_misc0_clr; /* 0x158 */ 562a7683867SFabio Estevam u32 ana_misc0_tog; /* 0x15c */ 563a7683867SFabio Estevam u32 ana_misc1; /* 0x160 */ 564a7683867SFabio Estevam u32 ana_misc1_set; /* 0x164 */ 565a7683867SFabio Estevam u32 ana_misc1_clr; /* 0x168 */ 566a7683867SFabio Estevam u32 ana_misc1_tog; /* 0x16c */ 567a7683867SFabio Estevam u32 ana_misc2; /* 0x170 */ 568a7683867SFabio Estevam u32 ana_misc2_set; /* 0x174 */ 569a7683867SFabio Estevam u32 ana_misc2_clr; /* 0x178 */ 570a7683867SFabio Estevam u32 ana_misc2_tog; /* 0x17c */ 571a7683867SFabio Estevam u32 tempsense0; /* 0x180 */ 572a7683867SFabio Estevam u32 tempsense0_set; /* 0x184 */ 573a7683867SFabio Estevam u32 tempsense0_clr; /* 0x188 */ 574a7683867SFabio Estevam u32 tempsense0_tog; /* 0x18c */ 575a7683867SFabio Estevam u32 tempsense1; /* 0x190 */ 576a7683867SFabio Estevam u32 tempsense1_set; /* 0x194 */ 577a7683867SFabio Estevam u32 tempsense1_clr; /* 0x198 */ 578a7683867SFabio Estevam u32 tempsense1_tog; /* 0x19c */ 579a7683867SFabio Estevam u32 usb1_vbus_detect; /* 0x1a0 */ 580a7683867SFabio Estevam u32 usb1_vbus_detect_set; /* 0x1a4 */ 581a7683867SFabio Estevam u32 usb1_vbus_detect_clr; /* 0x1a8 */ 582a7683867SFabio Estevam u32 usb1_vbus_detect_tog; /* 0x1ac */ 583a7683867SFabio Estevam u32 usb1_chrg_detect; /* 0x1b0 */ 584a7683867SFabio Estevam u32 usb1_chrg_detect_set; /* 0x1b4 */ 585a7683867SFabio Estevam u32 usb1_chrg_detect_clr; /* 0x1b8 */ 586a7683867SFabio Estevam u32 usb1_chrg_detect_tog; /* 0x1bc */ 587a7683867SFabio Estevam u32 usb1_vbus_det_stat; /* 0x1c0 */ 588a7683867SFabio Estevam u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 589a7683867SFabio Estevam u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 590a7683867SFabio Estevam u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 591a7683867SFabio Estevam u32 usb1_chrg_det_stat; /* 0x1d0 */ 592a7683867SFabio Estevam u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 593a7683867SFabio Estevam u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 594a7683867SFabio Estevam u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 595a7683867SFabio Estevam u32 usb1_loopback; /* 0x1e0 */ 596a7683867SFabio Estevam u32 usb1_loopback_set; /* 0x1e4 */ 597a7683867SFabio Estevam u32 usb1_loopback_clr; /* 0x1e8 */ 598a7683867SFabio Estevam u32 usb1_loopback_tog; /* 0x1ec */ 599a7683867SFabio Estevam u32 usb1_misc; /* 0x1f0 */ 600a7683867SFabio Estevam u32 usb1_misc_set; /* 0x1f4 */ 601a7683867SFabio Estevam u32 usb1_misc_clr; /* 0x1f8 */ 602a7683867SFabio Estevam u32 usb1_misc_tog; /* 0x1fc */ 603a7683867SFabio Estevam u32 usb2_vbus_detect; /* 0x200 */ 604a7683867SFabio Estevam u32 usb2_vbus_detect_set; /* 0x204 */ 605a7683867SFabio Estevam u32 usb2_vbus_detect_clr; /* 0x208 */ 606a7683867SFabio Estevam u32 usb2_vbus_detect_tog; /* 0x20c */ 607a7683867SFabio Estevam u32 usb2_chrg_detect; /* 0x210 */ 608a7683867SFabio Estevam u32 usb2_chrg_detect_set; /* 0x214 */ 609a7683867SFabio Estevam u32 usb2_chrg_detect_clr; /* 0x218 */ 610a7683867SFabio Estevam u32 usb2_chrg_detect_tog; /* 0x21c */ 611a7683867SFabio Estevam u32 usb2_vbus_det_stat; /* 0x220 */ 612a7683867SFabio Estevam u32 usb2_vbus_det_stat_set; /* 0x224 */ 613a7683867SFabio Estevam u32 usb2_vbus_det_stat_clr; /* 0x228 */ 614a7683867SFabio Estevam u32 usb2_vbus_det_stat_tog; /* 0x22c */ 615a7683867SFabio Estevam u32 usb2_chrg_det_stat; /* 0x230 */ 616a7683867SFabio Estevam u32 usb2_chrg_det_stat_set; /* 0x234 */ 617a7683867SFabio Estevam u32 usb2_chrg_det_stat_clr; /* 0x238 */ 618a7683867SFabio Estevam u32 usb2_chrg_det_stat_tog; /* 0x23c */ 619a7683867SFabio Estevam u32 usb2_loopback; /* 0x240 */ 620a7683867SFabio Estevam u32 usb2_loopback_set; /* 0x244 */ 621a7683867SFabio Estevam u32 usb2_loopback_clr; /* 0x248 */ 622a7683867SFabio Estevam u32 usb2_loopback_tog; /* 0x24c */ 623a7683867SFabio Estevam u32 usb2_misc; /* 0x250 */ 624a7683867SFabio Estevam u32 usb2_misc_set; /* 0x254 */ 625a7683867SFabio Estevam u32 usb2_misc_clr; /* 0x258 */ 626a7683867SFabio Estevam u32 usb2_misc_tog; /* 0x25c */ 627a7683867SFabio Estevam u32 digprog; /* 0x260 */ 62820332a06STroy Kisky u32 reserved1[7]; 62920332a06STroy Kisky u32 digprog_sololite; /* 0x280 */ 630a7683867SFabio Estevam }; 631a7683867SFabio Estevam 632e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 633e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT) 634e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6 635e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT) 636e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7 637e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT) 638e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8 639e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT) 640e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14 641e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT) 642e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15 643e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT) 644e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16 645e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT) 646e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22 647e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT) 648e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23 649e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT) 650e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24 651e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT) 652e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30 653e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT) 654e66ad6e7SEric Nelson #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31 655e66ad6e7SEric Nelson 65664e7cdb5SEric Nelson struct iomuxc_base_regs { 65764e7cdb5SEric Nelson u32 gpr[14]; /* 0x000 */ 65864e7cdb5SEric Nelson u32 obsrv[5]; /* 0x038 */ 65964e7cdb5SEric Nelson u32 swmux_ctl[197]; /* 0x04c */ 66064e7cdb5SEric Nelson u32 swpad_ctl[250]; /* 0x360 */ 66164e7cdb5SEric Nelson u32 swgrp[26]; /* 0x748 */ 66264e7cdb5SEric Nelson u32 daisy[104]; /* 0x7b0..94c */ 66364e7cdb5SEric Nelson }; 66464e7cdb5SEric Nelson 66576c91e66SFabio Estevam struct wdog_regs { 66676c91e66SFabio Estevam u16 wcr; /* Control */ 66776c91e66SFabio Estevam u16 wsr; /* Service */ 66876c91e66SFabio Estevam u16 wrsr; /* Reset Status */ 66976c91e66SFabio Estevam u16 wicr; /* Interrupt Control */ 67076c91e66SFabio Estevam u16 wmcr; /* Miscellaneous Control */ 67176c91e66SFabio Estevam }; 67276c91e66SFabio Estevam 67323608e23SJason Liu #endif /* __ASSEMBLER__*/ 67423608e23SJason Liu #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 675