1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 9 10 #define CCM_CCOSR 0x020c4060 11 #define CCM_CCGR0 0x020C4068 12 #define CCM_CCGR1 0x020C406c 13 #define CCM_CCGR2 0x020C4070 14 #define CCM_CCGR3 0x020C4074 15 #define CCM_CCGR4 0x020C4078 16 #define CCM_CCGR5 0x020C407c 17 #define CCM_CCGR6 0x020C4080 18 19 #define PMU_MISC2 0x020C8170 20 21 #ifndef __ASSEMBLY__ 22 struct mxc_ccm_reg { 23 u32 ccr; /* 0x0000 */ 24 u32 ccdr; 25 u32 csr; 26 u32 ccsr; 27 u32 cacrr; /* 0x0010*/ 28 u32 cbcdr; 29 u32 cbcmr; 30 u32 cscmr1; 31 u32 cscmr2; /* 0x0020 */ 32 u32 cscdr1; 33 u32 cs1cdr; 34 u32 cs2cdr; 35 u32 cdcdr; /* 0x0030 */ 36 u32 chsccdr; 37 u32 cscdr2; 38 u32 cscdr3; 39 u32 cscdr4; /* 0x0040 */ 40 u32 resv0; 41 u32 cdhipr; 42 u32 cdcr; 43 u32 ctor; /* 0x0050 */ 44 u32 clpcr; 45 u32 cisr; 46 u32 cimr; 47 u32 ccosr; /* 0x0060 */ 48 u32 cgpr; 49 u32 CCGR0; 50 u32 CCGR1; 51 u32 CCGR2; /* 0x0070 */ 52 u32 CCGR3; 53 u32 CCGR4; 54 u32 CCGR5; 55 u32 CCGR6; /* 0x0080 */ 56 u32 CCGR7; 57 u32 cmeor; 58 u32 resv[0xfdd]; 59 u32 analog_pll_sys; /* 0x4000 */ 60 u32 analog_pll_sys_set; 61 u32 analog_pll_sys_clr; 62 u32 analog_pll_sys_tog; 63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ 64 u32 analog_usb1_pll_480_ctrl_set; 65 u32 analog_usb1_pll_480_ctrl_clr; 66 u32 analog_usb1_pll_480_ctrl_tog; 67 u32 analog_reserved0[4]; 68 u32 analog_pll_528; /* 0x4030 */ 69 u32 analog_pll_528_set; 70 u32 analog_pll_528_clr; 71 u32 analog_pll_528_tog; 72 u32 analog_pll_528_ss; /* 0x4040 */ 73 u32 analog_reserved1[3]; 74 u32 analog_pll_528_num; /* 0x4050 */ 75 u32 analog_reserved2[3]; 76 u32 analog_pll_528_denom; /* 0x4060 */ 77 u32 analog_reserved3[3]; 78 u32 analog_pll_audio; /* 0x4070 */ 79 u32 analog_pll_audio_set; 80 u32 analog_pll_audio_clr; 81 u32 analog_pll_audio_tog; 82 u32 analog_pll_audio_num; /* 0x4080*/ 83 u32 analog_reserved4[3]; 84 u32 analog_pll_audio_denom; /* 0x4090 */ 85 u32 analog_reserved5[3]; 86 u32 analog_pll_video; /* 0x40a0 */ 87 u32 analog_pll_video_set; 88 u32 analog_pll_video_clr; 89 u32 analog_pll_video_tog; 90 u32 analog_pll_video_num; /* 0x40b0 */ 91 u32 analog_reserved6[3]; 92 u32 analog_pll_video_denom; /* 0x40c0 */ 93 u32 analog_reserved7[7]; 94 u32 analog_pll_enet; /* 0x40e0 */ 95 u32 analog_pll_enet_set; 96 u32 analog_pll_enet_clr; 97 u32 analog_pll_enet_tog; 98 u32 analog_pfd_480; /* 0x40f0 */ 99 u32 analog_pfd_480_set; 100 u32 analog_pfd_480_clr; 101 u32 analog_pfd_480_tog; 102 u32 analog_pfd_528; /* 0x4100 */ 103 u32 analog_pfd_528_set; 104 u32 analog_pfd_528_clr; 105 u32 analog_pfd_528_tog; 106 }; 107 #endif 108 109 /* Define the bits in register CCR */ 110 #define MXC_CCM_CCR_RBC_EN (1 << 27) 111 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) 112 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 113 /* CCR_WB does not exist on i.MX6SX/UL */ 114 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 115 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) 116 #define MXC_CCM_CCR_COSC_EN (1 << 12) 117 #ifdef CONFIG_MX6SX 118 #define MXC_CCM_CCR_OSCNT_MASK 0x7F 119 #else 120 #define MXC_CCM_CCR_OSCNT_MASK 0xFF 121 #endif 122 #define MXC_CCM_CCR_OSCNT_OFFSET 0 123 124 /* Define the bits in register CCDR */ 125 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) 126 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) 127 /* Exists on i.MX6QP */ 128 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) 129 130 /* Define the bits in register CSR */ 131 #define MXC_CCM_CSR_COSC_READY (1 << 5) 132 #define MXC_CCM_CSR_REF_EN_B (1 << 0) 133 134 /* Define the bits in register CCSR */ 135 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) 136 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) 137 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) 138 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) 139 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) 140 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) 141 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) 142 #define MXC_CCM_CCSR_STEP_SEL (1 << 8) 143 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 144 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 145 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 146 147 /* Define the bits in register CACRR */ 148 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 149 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 150 151 /* Define the bits in register CBCDR */ 152 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) 153 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 154 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26) 155 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) 156 /* MMDC_CH0 not exists on i.MX6SX */ 157 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) 158 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 159 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) 160 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 161 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 162 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 163 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 164 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 165 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) 166 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) 167 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) 168 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 169 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) 170 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 171 172 /* Define the bits in register CBCMR */ 173 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) 174 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 175 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) 176 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 177 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) 178 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 179 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) 180 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 181 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) 182 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) 183 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 184 #ifndef CONFIG_MX6SX 185 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) 186 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 187 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 188 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 189 #endif 190 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) 191 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 192 #ifndef CONFIG_MX6SX 193 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) 194 #endif 195 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) 196 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) 197 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 198 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) 199 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 200 /* Exists on i.MX6QP */ 201 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) 202 203 /* Define the bits in register CSCMR1 */ 204 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) 205 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 206 /* QSPI1 exist on i.MX6SX/UL */ 207 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26) 208 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 209 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) 210 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 211 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) 212 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 213 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */ 214 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) 215 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 216 /* CSCMR1_GPMI/BCH exist on i.MX6UL */ 217 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19) 218 #define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18) 219 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) 220 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) 221 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) 222 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) 223 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) 224 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 225 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 226 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 227 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) 228 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 229 /* QSPI1 exist on i.MX6SX/UL */ 230 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) 231 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 232 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ 233 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) 234 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 235 236 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F 237 238 /* Define the bits in register CSCMR2 */ 239 #ifdef CONFIG_MX6SX 240 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21) 241 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 242 #endif 243 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) 244 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 245 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) 246 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) 247 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */ 248 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) 249 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 250 251 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) 252 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 253 254 /* Define the bits in register CSCDR1 */ 255 #ifndef CONFIG_MX6SX 256 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) 257 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 258 #endif 259 /* CSCDR1_GPMI/BCH exist on i.MX6UL */ 260 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22) 261 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22 262 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19) 263 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19 264 265 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) 266 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 267 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) 268 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 269 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) 270 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 271 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) 272 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 273 #ifndef CONFIG_MX6SX 274 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 275 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 276 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 277 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 278 #endif 279 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F 280 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 281 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */ 282 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) 283 284 /* Define the bits in register CS1CDR */ 285 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) 286 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 287 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22) 288 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 289 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) 290 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 291 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) 292 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 293 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 294 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 295 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F 296 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 297 298 /* Define the bits in register CS2CDR */ 299 /* QSPI2 on i.MX6SX */ 300 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21) 301 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 302 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) 303 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18) 304 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 305 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) 306 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15) 307 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 308 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) 309 310 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) 311 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 312 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) 313 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) 314 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 315 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) 316 317 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15) 318 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15 319 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) 320 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16) 321 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16 322 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) 323 324 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ 325 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 326 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ 327 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) 328 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ 329 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 330 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ 331 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) 332 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ 333 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 334 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ 335 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) 336 337 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) 338 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 339 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) 340 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 341 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 342 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 343 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F 344 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 345 346 /* Define the bits in register CDCDR */ 347 #ifndef CONFIG_MX6SX 348 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) 349 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 350 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) 351 #endif 352 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 353 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 354 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22) 355 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 356 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) 357 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 358 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) 359 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 360 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) 361 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 362 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) 363 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 364 365 /* Define the bits in register CHSCCDR */ 366 #ifdef CONFIG_MX6SX 367 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15) 368 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 369 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12) 370 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 371 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9) 372 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 373 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6) 374 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 375 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3) 376 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 377 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7) 378 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 379 #else 380 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 381 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 382 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) 383 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 384 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) 385 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 386 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 387 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 388 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) 389 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 390 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) 391 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 392 #endif 393 394 #define CHSCCDR_CLK_SEL_LDB_DI0 3 395 #define CHSCCDR_PODF_DIVIDE_BY_3 2 396 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 397 398 /* Define the bits in register CSCDR2 */ 399 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) 400 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 401 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ 402 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) 403 404 /* All IPU2_DI1 are LCDIF1 on MX6SX */ 405 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 406 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 407 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) 408 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 409 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) 410 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 411 /* All IPU2_DI0 are LCDIF2 on MX6SX */ 412 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 413 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 414 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) 415 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 416 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 417 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 418 419 /* Define the bits in register CSCDR3 */ 420 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) 421 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 422 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) 423 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 424 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) 425 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 426 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) 427 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 428 429 /* Define the bits in register CDHIPR */ 430 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 431 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 432 #ifndef CONFIG_MX6SX 433 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) 434 #endif 435 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) 436 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) 437 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) 438 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 439 440 /* Define the bits in register CLPCR */ 441 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) 442 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) 443 #ifndef CONFIG_MX6SX 444 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) 445 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) 446 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) 447 #endif 448 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) 449 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) 450 #ifndef CONFIG_MX6SX 451 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) 452 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) 453 #endif 454 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) 455 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) 456 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 457 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 458 #define MXC_CCM_CLPCR_VSTBY (1 << 8) 459 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) 460 #define MXC_CCM_CLPCR_SBYOS (1 << 6) 461 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) 462 #ifndef CONFIG_MX6SX 463 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 464 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 465 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) 466 #endif 467 #define MXC_CCM_CLPCR_LPM_MASK 0x3 468 #define MXC_CCM_CLPCR_LPM_OFFSET 0 469 470 /* Define the bits in register CISR */ 471 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) 472 #ifndef CONFIG_MX6SX 473 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) 474 #endif 475 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) 476 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) 477 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) 478 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) 479 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) 480 #define MXC_CCM_CISR_COSC_READY (1 << 6) 481 #define MXC_CCM_CISR_LRF_PLL 1 482 483 /* Define the bits in register CIMR */ 484 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) 485 #ifndef CONFIG_MX6SX 486 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) 487 #endif 488 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) 489 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) 490 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) 491 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) 492 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) 493 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) 494 #define MXC_CCM_CIMR_MASK_LRF_PLL 1 495 496 /* Define the bits in register CCOSR */ 497 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) 498 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 499 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 500 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 501 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 502 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) 503 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 504 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 505 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 506 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF 507 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 508 509 /* Define the bits in registers CGPR */ 510 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) 511 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 512 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) 513 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 514 515 /* Define the bits in registers CCGRx */ 516 #define MXC_CCM_CCGR_CG_MASK 3 517 518 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 519 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) 520 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 521 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) 522 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 523 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) 524 #define MXC_CCM_CCGR0_ASRC_OFFSET 6 525 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) 526 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 527 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) 528 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 529 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) 530 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 531 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) 532 #define MXC_CCM_CCGR0_CAN1_OFFSET 14 533 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) 534 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 535 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) 536 #define MXC_CCM_CCGR0_CAN2_OFFSET 18 537 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) 538 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 539 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) 540 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 541 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) 542 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24 543 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) 544 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 545 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) 546 #ifdef CONFIG_MX6SX 547 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30 548 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET) 549 #else 550 #define MXC_CCM_CCGR0_DTCP_OFFSET 28 551 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) 552 #endif 553 554 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 555 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) 556 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 557 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) 558 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 559 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) 560 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 561 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) 562 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 563 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) 564 /* CCGR1_ENET does not exist on i.MX6SX/UL */ 565 #define MXC_CCM_CCGR1_ENET_OFFSET 10 566 #define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET) 567 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 568 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) 569 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 570 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) 571 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 572 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) 573 #ifdef CONFIG_MX6SX 574 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18 575 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET) 576 #endif 577 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 578 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) 579 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 580 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) 581 #ifndef CONFIG_MX6SX 582 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 583 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) 584 #endif 585 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 586 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) 587 #ifdef CONFIG_MX6SX 588 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28 589 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET) 590 #define MXC_CCM_CCGR1_CANFD_OFFSET 30 591 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) 592 #endif 593 594 #ifndef CONFIG_MX6SX 595 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 596 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) 597 #else 598 #define MXC_CCM_CCGR2_CSI_OFFSET 2 599 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) 600 #endif 601 #ifndef CONFIG_MX6SX 602 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 603 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) 604 #endif 605 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 606 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) 607 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 608 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) 609 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 610 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) 611 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8 612 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET) 613 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 614 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) 615 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 616 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) 617 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 618 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) 619 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 620 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) 621 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 622 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) 623 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 624 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) 625 #ifdef CONFIG_MX6SX 626 #define MXC_CCM_CCGR2_LCD_OFFSET 28 627 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) 628 #define MXC_CCM_CCGR2_PXP_OFFSET 30 629 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) 630 #else 631 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 632 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) 633 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 634 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) 635 #endif 636 637 /* Exist on i.MX6SX */ 638 #define MXC_CCM_CCGR3_M4_OFFSET 2 639 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) 640 #define MXC_CCM_CCGR3_ENET_OFFSET 4 641 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) 642 #define MXC_CCM_CCGR3_QSPI_OFFSET 14 643 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) 644 645 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 646 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) 647 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 648 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) 649 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 650 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) 651 652 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 653 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) 654 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 655 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) 656 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 657 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) 658 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 659 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) 660 661 /* QSPI1 exists on i.MX6SX/UL */ 662 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14 663 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) 664 665 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 666 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) 667 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 668 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) 669 670 /* A7_CLKDIV/WDOG1 on i.MX6UL */ 671 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16 672 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET) 673 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18 674 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET) 675 676 #define MXC_CCM_CCGR3_MLB_OFFSET 18 677 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) 678 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 679 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) 680 #ifndef CONFIG_MX6SX 681 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 682 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) 683 #endif 684 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 685 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) 686 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 687 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) 688 /* AXI on i.MX6UL */ 689 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 690 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET) 691 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 692 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) 693 694 /* GPIO4 on i.MX6UL */ 695 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30 696 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET) 697 698 #ifndef CONFIG_MX6SX 699 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 700 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) 701 #endif 702 703 #define MXC_CCM_CCGR4_PCIE_OFFSET 0 704 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) 705 /* QSPI2 on i.MX6SX */ 706 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 707 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) 708 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 709 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) 710 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 711 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) 712 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 713 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) 714 #define MXC_CCM_CCGR4_PWM1_OFFSET 16 715 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) 716 #define MXC_CCM_CCGR4_PWM2_OFFSET 18 717 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) 718 #define MXC_CCM_CCGR4_PWM3_OFFSET 20 719 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) 720 #define MXC_CCM_CCGR4_PWM4_OFFSET 22 721 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) 722 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 723 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) 724 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 725 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) 726 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 727 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) 728 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 729 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) 730 731 #define MXC_CCM_CCGR5_ROM_OFFSET 0 732 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) 733 #ifndef CONFIG_MX6SX 734 #define MXC_CCM_CCGR5_SATA_OFFSET 4 735 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) 736 #endif 737 #define MXC_CCM_CCGR5_SDMA_OFFSET 6 738 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) 739 #define MXC_CCM_CCGR5_SPBA_OFFSET 12 740 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) 741 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14 742 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) 743 #define MXC_CCM_CCGR5_SSI1_OFFSET 18 744 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) 745 #define MXC_CCM_CCGR5_SSI2_OFFSET 20 746 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) 747 #define MXC_CCM_CCGR5_SSI3_OFFSET 22 748 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) 749 #define MXC_CCM_CCGR5_UART_OFFSET 24 750 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) 751 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 752 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) 753 #ifdef CONFIG_MX6SX 754 #define MXC_CCM_CCGR5_SAI1_OFFSET 20 755 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET) 756 #define MXC_CCM_CCGR5_SAI2_OFFSET 30 757 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) 758 #endif 759 760 /* PRG_CLK0 exists on i.MX6QP */ 761 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24) 762 763 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 764 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) 765 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2 766 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) 767 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 768 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) 769 /* GPMI/BCH on i.MX6UL */ 770 #define MXC_CCM_CCGR6_BCH_OFFSET 6 771 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET) 772 #define MXC_CCM_CCGR6_GPMI_OFFSET 8 773 #define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET) 774 775 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 776 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) 777 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 778 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) 779 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 780 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) 781 /* The following *CCGR6* exist only i.MX6SX */ 782 #define MXC_CCM_CCGR6_PWM8_OFFSET 16 783 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) 784 #define MXC_CCM_CCGR6_VADC_OFFSET 20 785 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) 786 #define MXC_CCM_CCGR6_GIS_OFFSET 22 787 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) 788 #define MXC_CCM_CCGR6_I2C4_OFFSET 24 789 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) 790 #define MXC_CCM_CCGR6_PWM5_OFFSET 26 791 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) 792 #define MXC_CCM_CCGR6_PWM6_OFFSET 28 793 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) 794 #define MXC_CCM_CCGR6_PWM7_OFFSET 30 795 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) 796 /* The two does not exist on i.MX6SX */ 797 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 798 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) 799 800 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 801 #define BP_ANADIG_PLL_SYS_RSVD0 20 802 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 803 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ 804 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) 805 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 806 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 807 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 808 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 809 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 810 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 811 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ 812 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) 813 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 814 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 815 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 816 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 817 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 818 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 819 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 820 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 821 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 822 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 823 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 824 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0 825 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F 826 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ 827 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) 828 829 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 830 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 831 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 832 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ 833 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) 834 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 835 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 836 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 837 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ 838 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) 839 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 840 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 841 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 842 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 843 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 844 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 845 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 846 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 847 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 848 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 849 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 850 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 851 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 852 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 853 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C 854 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ 855 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) 856 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 857 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 858 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ 859 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) 860 861 #define BM_ANADIG_PLL_528_LOCK 0x80000000 862 #define BP_ANADIG_PLL_528_RSVD1 19 863 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 864 #define BF_ANADIG_PLL_528_RSVD1(v) \ 865 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) 866 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 867 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 868 #define BM_ANADIG_PLL_528_BYPASS 0x00010000 869 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 870 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 871 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ 872 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) 873 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 874 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 875 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 876 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 877 #define BM_ANADIG_PLL_528_ENABLE 0x00002000 878 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 879 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 880 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 881 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200 882 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 883 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080 884 #define BP_ANADIG_PLL_528_RSVD0 1 885 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E 886 #define BF_ANADIG_PLL_528_RSVD0(v) \ 887 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) 888 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 889 890 #define BP_ANADIG_PLL_528_SS_STOP 16 891 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 892 #define BF_ANADIG_PLL_528_SS_STOP(v) \ 893 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) 894 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 895 #define BP_ANADIG_PLL_528_SS_STEP 0 896 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF 897 #define BF_ANADIG_PLL_528_SS_STEP(v) \ 898 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) 899 900 #define BP_ANADIG_PLL_528_NUM_RSVD0 30 901 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 902 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ 903 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) 904 #define BP_ANADIG_PLL_528_NUM_A 0 905 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF 906 #define BF_ANADIG_PLL_528_NUM_A(v) \ 907 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) 908 909 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30 910 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 911 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ 912 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) 913 #define BP_ANADIG_PLL_528_DENOM_B 0 914 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF 915 #define BF_ANADIG_PLL_528_DENOM_B(v) \ 916 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) 917 918 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 919 #define BP_ANADIG_PLL_AUDIO_RSVD0 22 920 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 921 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ 922 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) 923 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 924 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 925 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 926 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ 927 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) 928 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 929 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 930 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 931 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 932 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 933 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ 934 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) 935 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 936 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 937 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 938 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 939 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 940 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 941 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 942 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 943 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 944 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 945 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 946 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 947 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F 948 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ 949 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) 950 951 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 952 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 953 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ 954 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) 955 #define BP_ANADIG_PLL_AUDIO_NUM_A 0 956 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF 957 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ 958 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) 959 960 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 961 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 962 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ 963 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) 964 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 965 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF 966 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ 967 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) 968 969 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 970 #define BP_ANADIG_PLL_VIDEO_RSVD0 22 971 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 972 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ 973 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) 974 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 975 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 976 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000 977 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ 978 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) 979 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 980 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 981 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 982 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 983 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 984 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ 985 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) 986 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 987 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 988 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 989 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 990 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 991 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 992 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 993 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 994 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 995 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 996 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 997 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 998 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F 999 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ 1000 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) 1001 1002 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 1003 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 1004 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ 1005 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) 1006 #define BP_ANADIG_PLL_VIDEO_NUM_A 0 1007 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF 1008 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ 1009 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) 1010 1011 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 1012 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 1013 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ 1014 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) 1015 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 1016 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF 1017 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ 1018 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) 1019 1020 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000 1021 #define BP_ANADIG_PLL_ENET_RSVD1 21 1022 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 1023 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ 1024 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) 1025 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000 1026 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 1027 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 1028 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 1029 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 1030 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 1031 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 1032 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 1033 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ 1034 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) 1035 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 1036 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 1037 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 1038 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 1039 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 1040 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 1041 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 1042 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 1043 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 1044 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 1045 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 1046 #define BP_ANADIG_PLL_ENET_RSVD0 2 1047 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C 1048 #define BF_ANADIG_PLL_ENET_RSVD0(v) \ 1049 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) 1050 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 1051 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 1052 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ 1053 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) 1054 1055 /* ENET2 for i.MX6SX/UL */ 1056 #define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 1057 #define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C 1058 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ 1059 (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) 1060 1061 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 1062 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 1063 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 1064 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 1065 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ 1066 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) 1067 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 1068 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 1069 #define BP_ANADIG_PFD_480_PFD2_FRAC 16 1070 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 1071 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ 1072 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) 1073 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 1074 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 1075 #define BP_ANADIG_PFD_480_PFD1_FRAC 8 1076 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 1077 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ 1078 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) 1079 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 1080 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 1081 #define BP_ANADIG_PFD_480_PFD0_FRAC 0 1082 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F 1083 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ 1084 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) 1085 1086 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 1087 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 1088 #define BP_ANADIG_PFD_528_PFD3_FRAC 24 1089 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 1090 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ 1091 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) 1092 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 1093 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 1094 #define BP_ANADIG_PFD_528_PFD2_FRAC 16 1095 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 1096 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ 1097 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) 1098 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 1099 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 1100 #define BP_ANADIG_PFD_528_PFD1_FRAC 8 1101 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 1102 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ 1103 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) 1104 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 1105 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 1106 #define BP_ANADIG_PFD_528_PFD0_FRAC 0 1107 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F 1108 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ 1109 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) 1110 1111 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 1112 1113 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ 1114