1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 9 10 #define CCM_CCOSR 0x020c4060 11 #define CCM_CCGR0 0x020C4068 12 #define CCM_CCGR1 0x020C406c 13 #define CCM_CCGR2 0x020C4070 14 #define CCM_CCGR3 0x020C4074 15 #define CCM_CCGR4 0x020C4078 16 #define CCM_CCGR5 0x020C407c 17 #define CCM_CCGR6 0x020C4080 18 19 #define PMU_MISC2 0x020C8170 20 21 #ifndef __ASSEMBLY__ 22 struct mxc_ccm_reg { 23 u32 ccr; /* 0x0000 */ 24 u32 ccdr; 25 u32 csr; 26 u32 ccsr; 27 u32 cacrr; /* 0x0010*/ 28 u32 cbcdr; 29 u32 cbcmr; 30 u32 cscmr1; 31 u32 cscmr2; /* 0x0020 */ 32 u32 cscdr1; 33 u32 cs1cdr; 34 u32 cs2cdr; 35 u32 cdcdr; /* 0x0030 */ 36 u32 chsccdr; 37 u32 cscdr2; 38 u32 cscdr3; 39 u32 cscdr4; /* 0x0040 */ 40 u32 resv0; 41 u32 cdhipr; 42 u32 cdcr; 43 u32 ctor; /* 0x0050 */ 44 u32 clpcr; 45 u32 cisr; 46 u32 cimr; 47 u32 ccosr; /* 0x0060 */ 48 u32 cgpr; 49 u32 CCGR0; 50 u32 CCGR1; 51 u32 CCGR2; /* 0x0070 */ 52 u32 CCGR3; 53 u32 CCGR4; 54 u32 CCGR5; 55 u32 CCGR6; /* 0x0080 */ 56 u32 CCGR7; 57 u32 cmeor; 58 u32 resv[0xfdd]; 59 u32 analog_pll_sys; /* 0x4000 */ 60 u32 analog_pll_sys_set; 61 u32 analog_pll_sys_clr; 62 u32 analog_pll_sys_tog; 63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ 64 u32 analog_usb1_pll_480_ctrl_set; 65 u32 analog_usb1_pll_480_ctrl_clr; 66 u32 analog_usb1_pll_480_ctrl_tog; 67 u32 analog_reserved0[4]; 68 u32 analog_pll_528; /* 0x4030 */ 69 u32 analog_pll_528_set; 70 u32 analog_pll_528_clr; 71 u32 analog_pll_528_tog; 72 u32 analog_pll_528_ss; /* 0x4040 */ 73 u32 analog_reserved1[3]; 74 u32 analog_pll_528_num; /* 0x4050 */ 75 u32 analog_reserved2[3]; 76 u32 analog_pll_528_denom; /* 0x4060 */ 77 u32 analog_reserved3[3]; 78 u32 analog_pll_audio; /* 0x4070 */ 79 u32 analog_pll_audio_set; 80 u32 analog_pll_audio_clr; 81 u32 analog_pll_audio_tog; 82 u32 analog_pll_audio_num; /* 0x4080*/ 83 u32 analog_reserved4[3]; 84 u32 analog_pll_audio_denom; /* 0x4090 */ 85 u32 analog_reserved5[3]; 86 u32 analog_pll_video; /* 0x40a0 */ 87 u32 analog_pll_video_set; 88 u32 analog_pll_video_clr; 89 u32 analog_pll_video_tog; 90 u32 analog_pll_video_num; /* 0x40b0 */ 91 u32 analog_reserved6[3]; 92 u32 analog_pll_video_denom; /* 0x40c0 */ 93 u32 analog_reserved7[7]; 94 u32 analog_pll_enet; /* 0x40e0 */ 95 u32 analog_pll_enet_set; 96 u32 analog_pll_enet_clr; 97 u32 analog_pll_enet_tog; 98 u32 analog_pfd_480; /* 0x40f0 */ 99 u32 analog_pfd_480_set; 100 u32 analog_pfd_480_clr; 101 u32 analog_pfd_480_tog; 102 u32 analog_pfd_528; /* 0x4100 */ 103 u32 analog_pfd_528_set; 104 u32 analog_pfd_528_clr; 105 u32 analog_pfd_528_tog; 106 }; 107 #endif 108 109 /* Define the bits in register CCR */ 110 #define MXC_CCM_CCR_RBC_EN (1 << 27) 111 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) 112 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 113 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 114 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) 115 #define MXC_CCM_CCR_COSC_EN (1 << 12) 116 #ifdef CONFIG_MX6SX 117 #define MXC_CCM_CCR_OSCNT_MASK 0x7F 118 #else 119 #define MXC_CCM_CCR_OSCNT_MASK 0xFF 120 #endif 121 #define MXC_CCM_CCR_OSCNT_OFFSET 0 122 123 /* Define the bits in register CCDR */ 124 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) 125 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) 126 127 /* Define the bits in register CSR */ 128 #define MXC_CCM_CSR_COSC_READY (1 << 5) 129 #define MXC_CCM_CSR_REF_EN_B (1 << 0) 130 131 /* Define the bits in register CCSR */ 132 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) 133 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) 134 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) 135 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) 136 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) 137 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) 138 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) 139 #define MXC_CCM_CCSR_STEP_SEL (1 << 8) 140 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 141 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 142 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 143 144 /* Define the bits in register CACRR */ 145 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 146 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 147 148 /* Define the bits in register CBCDR */ 149 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) 150 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 151 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) 152 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) 153 #ifndef CONFIG_MX6SX 154 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) 155 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 156 #endif 157 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) 158 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 159 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 160 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 161 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 162 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 163 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) 164 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) 165 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) 166 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 167 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) 168 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 169 170 /* Define the bits in register CBCMR */ 171 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) 172 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 173 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) 174 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 175 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) 176 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 177 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) 178 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 179 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) 180 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) 181 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 182 #ifndef CONFIG_MX6SX 183 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) 184 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 185 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 186 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 187 #endif 188 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) 189 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 190 #ifndef CONFIG_MX6SX 191 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) 192 #endif 193 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) 194 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) 195 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 196 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) 197 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 198 #ifndef CONFIG_MX6SX 199 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) 200 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) 201 #endif 202 203 /* Define the bits in register CSCMR1 */ 204 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) 205 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 206 #ifdef CONFIG_MX6SX 207 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26) 208 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 209 #else 210 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) 211 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 212 #endif 213 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) 214 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 215 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */ 216 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) 217 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 218 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) 219 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) 220 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) 221 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) 222 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) 223 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 224 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 225 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 226 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) 227 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 228 #ifdef CONFIG_MX6SX 229 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) 230 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 231 #endif 232 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) 233 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) 234 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 235 #endif 236 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F 237 238 /* Define the bits in register CSCMR2 */ 239 #ifdef CONFIG_MX6SX 240 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21) 241 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 242 #endif 243 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) 244 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 245 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) 246 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) 247 #ifdef CONFIG_MX6SX 248 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) 249 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 250 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) 251 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 252 #else 253 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) 254 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 255 #endif 256 257 /* Define the bits in register CSCDR1 */ 258 #ifndef CONFIG_MX6SX 259 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) 260 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 261 #endif 262 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) 263 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 264 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) 265 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 266 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) 267 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 268 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) 269 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 270 #ifndef CONFIG_MX6SX 271 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 272 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 273 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 274 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 275 #endif 276 #ifdef CONFIG_MX6SL 277 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F 278 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) 279 #else 280 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F 281 #ifdef CONFIG_MX6SX 282 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) 283 #endif 284 #endif 285 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 286 287 /* Define the bits in register CS1CDR */ 288 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) 289 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 290 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22) 291 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 292 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) 293 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 294 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) 295 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 296 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 297 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 298 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F 299 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 300 301 /* Define the bits in register CS2CDR */ 302 #ifdef CONFIG_MX6SX 303 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21) 304 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 305 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) 306 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18) 307 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 308 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) 309 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15) 310 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 311 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) 312 #else 313 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) 314 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 315 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) 316 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) 317 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 318 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) 319 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) 320 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 321 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16) 322 #endif 323 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) 324 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 325 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) 326 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 327 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 328 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 329 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F 330 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 331 332 /* Define the bits in register CDCDR */ 333 #ifndef CONFIG_MX6SX 334 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) 335 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 336 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) 337 #endif 338 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 339 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 340 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22) 341 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 342 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) 343 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 344 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) 345 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 346 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) 347 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 348 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) 349 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 350 351 /* Define the bits in register CHSCCDR */ 352 #ifdef CONFIG_MX6SX 353 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15) 354 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 355 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12) 356 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 357 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9) 358 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 359 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6) 360 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 361 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3) 362 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 363 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7) 364 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 365 #else 366 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 367 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 368 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) 369 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 370 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) 371 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 372 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 373 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 374 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) 375 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 376 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) 377 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 378 #endif 379 380 #define CHSCCDR_CLK_SEL_LDB_DI0 3 381 #define CHSCCDR_PODF_DIVIDE_BY_3 2 382 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 383 384 /* Define the bits in register CSCDR2 */ 385 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) 386 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 387 /* All IPU2_DI1 are LCDIF1 on MX6SX */ 388 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 389 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 390 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) 391 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 392 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) 393 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 394 /* All IPU2_DI0 are LCDIF2 on MX6SX */ 395 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 396 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 397 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) 398 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 399 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 400 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 401 402 /* Define the bits in register CSCDR3 */ 403 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) 404 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 405 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) 406 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 407 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) 408 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 409 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) 410 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 411 412 /* Define the bits in register CDHIPR */ 413 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 414 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 415 #ifndef CONFIG_MX6SX 416 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) 417 #endif 418 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) 419 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) 420 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) 421 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 422 423 /* Define the bits in register CLPCR */ 424 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) 425 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) 426 #ifndef CONFIG_MX6SX 427 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) 428 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) 429 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) 430 #endif 431 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) 432 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) 433 #ifndef CONFIG_MX6SX 434 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) 435 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) 436 #endif 437 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) 438 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) 439 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 440 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 441 #define MXC_CCM_CLPCR_VSTBY (1 << 8) 442 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) 443 #define MXC_CCM_CLPCR_SBYOS (1 << 6) 444 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) 445 #ifndef CONFIG_MX6SX 446 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 447 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 448 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) 449 #endif 450 #define MXC_CCM_CLPCR_LPM_MASK 0x3 451 #define MXC_CCM_CLPCR_LPM_OFFSET 0 452 453 /* Define the bits in register CISR */ 454 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) 455 #ifndef CONFIG_MX6SX 456 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) 457 #endif 458 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) 459 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) 460 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) 461 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) 462 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) 463 #define MXC_CCM_CISR_COSC_READY (1 << 6) 464 #define MXC_CCM_CISR_LRF_PLL 1 465 466 /* Define the bits in register CIMR */ 467 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) 468 #ifndef CONFIG_MX6SX 469 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) 470 #endif 471 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) 472 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) 473 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) 474 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) 475 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) 476 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) 477 #define MXC_CCM_CIMR_MASK_LRF_PLL 1 478 479 /* Define the bits in register CCOSR */ 480 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) 481 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 482 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 483 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 484 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 485 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) 486 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 487 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 488 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 489 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF 490 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 491 492 /* Define the bits in registers CGPR */ 493 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) 494 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 495 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) 496 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 497 498 /* Define the bits in registers CCGRx */ 499 #define MXC_CCM_CCGR_CG_MASK 3 500 501 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 502 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) 503 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 504 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) 505 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 506 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) 507 #define MXC_CCM_CCGR0_ASRC_OFFSET 6 508 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) 509 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 510 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) 511 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 512 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) 513 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 514 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) 515 #define MXC_CCM_CCGR0_CAN1_OFFSET 14 516 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) 517 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 518 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) 519 #define MXC_CCM_CCGR0_CAN2_OFFSET 18 520 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) 521 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 522 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) 523 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 524 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) 525 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24 526 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) 527 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 528 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) 529 #ifdef CONFIG_MX6SX 530 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30 531 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET) 532 #else 533 #define MXC_CCM_CCGR0_DTCP_OFFSET 28 534 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) 535 #endif 536 537 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 538 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) 539 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 540 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) 541 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 542 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) 543 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 544 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) 545 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 546 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) 547 #ifndef CONFIG_MX6SX 548 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 549 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) 550 #endif 551 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 552 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) 553 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 554 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) 555 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 556 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) 557 #ifdef CONFIG_MX6SX 558 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18 559 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET) 560 #endif 561 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 562 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) 563 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 564 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) 565 #ifndef CONFIG_MX6SX 566 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 567 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) 568 #endif 569 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 570 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) 571 #ifdef CONFIG_MX6SX 572 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28 573 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET) 574 #define MXC_CCM_CCGR1_CANFD_OFFSET 30 575 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) 576 #endif 577 578 #ifndef CONFIG_MX6SX 579 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 580 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) 581 #else 582 #define MXC_CCM_CCGR2_CSI_OFFSET 2 583 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) 584 #endif 585 #ifndef CONFIG_MX6SX 586 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 587 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) 588 #endif 589 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 590 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) 591 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 592 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) 593 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 594 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) 595 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 596 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) 597 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 598 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) 599 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 600 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) 601 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 602 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) 603 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 604 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) 605 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 606 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) 607 #ifdef CONFIG_MX6SX 608 #define MXC_CCM_CCGR2_LCD_OFFSET 28 609 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) 610 #define MXC_CCM_CCGR2_PXP_OFFSET 30 611 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) 612 #else 613 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 614 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) 615 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 616 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) 617 #endif 618 619 #ifdef CONFIG_MX6SX 620 #define MXC_CCM_CCGR3_M4_OFFSET 2 621 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) 622 #define MXC_CCM_CCGR3_ENET_OFFSET 4 623 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) 624 #define MXC_CCM_CCGR3_QSPI_OFFSET 14 625 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) 626 #else 627 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 628 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) 629 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 630 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) 631 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 632 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) 633 #endif 634 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 635 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) 636 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 637 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) 638 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 639 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) 640 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 641 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) 642 #ifdef CONFIG_MX6SX 643 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14 644 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) 645 #else 646 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 647 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) 648 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 649 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) 650 #endif 651 #define MXC_CCM_CCGR3_MLB_OFFSET 18 652 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) 653 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 654 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) 655 #ifndef CONFIG_MX6SX 656 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 657 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) 658 #endif 659 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 660 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) 661 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 662 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) 663 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 664 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) 665 #ifndef CONFIG_MX6SX 666 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 667 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) 668 #endif 669 670 #define MXC_CCM_CCGR4_PCIE_OFFSET 0 671 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) 672 #ifdef CONFIG_MX6SX 673 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 674 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) 675 #else 676 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 677 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) 678 #endif 679 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 680 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) 681 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 682 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) 683 #define MXC_CCM_CCGR4_PWM1_OFFSET 16 684 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) 685 #define MXC_CCM_CCGR4_PWM2_OFFSET 18 686 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) 687 #define MXC_CCM_CCGR4_PWM3_OFFSET 20 688 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) 689 #define MXC_CCM_CCGR4_PWM4_OFFSET 22 690 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) 691 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 692 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) 693 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 694 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) 695 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 696 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) 697 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 698 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) 699 700 #define MXC_CCM_CCGR5_ROM_OFFSET 0 701 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) 702 #ifndef CONFIG_MX6SX 703 #define MXC_CCM_CCGR5_SATA_OFFSET 4 704 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) 705 #endif 706 #define MXC_CCM_CCGR5_SDMA_OFFSET 6 707 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) 708 #define MXC_CCM_CCGR5_SPBA_OFFSET 12 709 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) 710 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14 711 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) 712 #define MXC_CCM_CCGR5_SSI1_OFFSET 18 713 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) 714 #define MXC_CCM_CCGR5_SSI2_OFFSET 20 715 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) 716 #define MXC_CCM_CCGR5_SSI3_OFFSET 22 717 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) 718 #define MXC_CCM_CCGR5_UART_OFFSET 24 719 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) 720 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 721 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) 722 #ifdef CONFIG_MX6SX 723 #define MXC_CCM_CCGR5_SAI1_OFFSET 20 724 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET) 725 #define MXC_CCM_CCGR5_SAI2_OFFSET 30 726 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) 727 #endif 728 729 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 730 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) 731 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2 732 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) 733 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 734 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) 735 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 736 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) 737 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 738 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) 739 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 740 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) 741 #ifdef CONFIG_MX6SX 742 #define MXC_CCM_CCGR6_PWM8_OFFSET 16 743 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) 744 #define MXC_CCM_CCGR6_VADC_OFFSET 20 745 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) 746 #define MXC_CCM_CCGR6_GIS_OFFSET 22 747 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) 748 #define MXC_CCM_CCGR6_I2C4_OFFSET 24 749 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) 750 #define MXC_CCM_CCGR6_PWM5_OFFSET 26 751 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) 752 #define MXC_CCM_CCGR6_PWM6_OFFSET 28 753 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) 754 #define MXC_CCM_CCGR6_PWM7_OFFSET 30 755 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) 756 #else 757 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 758 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) 759 #endif 760 761 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 762 #define BP_ANADIG_PLL_SYS_RSVD0 20 763 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 764 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ 765 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) 766 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 767 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 768 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 769 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 770 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 771 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 772 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ 773 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) 774 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 775 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 776 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 777 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 778 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 779 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 780 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 781 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 782 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 783 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 784 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 785 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0 786 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F 787 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ 788 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) 789 790 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 791 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 792 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 793 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ 794 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) 795 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 796 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 797 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 798 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ 799 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) 800 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 801 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 802 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 803 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 804 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 805 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 806 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 807 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 808 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 809 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 810 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 811 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 812 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 813 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 814 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C 815 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ 816 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) 817 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 818 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 819 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ 820 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) 821 822 #define BM_ANADIG_PLL_528_LOCK 0x80000000 823 #define BP_ANADIG_PLL_528_RSVD1 19 824 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 825 #define BF_ANADIG_PLL_528_RSVD1(v) \ 826 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) 827 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 828 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 829 #define BM_ANADIG_PLL_528_BYPASS 0x00010000 830 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 831 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 832 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ 833 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) 834 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 835 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 836 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 837 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 838 #define BM_ANADIG_PLL_528_ENABLE 0x00002000 839 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 840 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 841 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 842 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200 843 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 844 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080 845 #define BP_ANADIG_PLL_528_RSVD0 1 846 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E 847 #define BF_ANADIG_PLL_528_RSVD0(v) \ 848 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) 849 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 850 851 #define BP_ANADIG_PLL_528_SS_STOP 16 852 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 853 #define BF_ANADIG_PLL_528_SS_STOP(v) \ 854 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) 855 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 856 #define BP_ANADIG_PLL_528_SS_STEP 0 857 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF 858 #define BF_ANADIG_PLL_528_SS_STEP(v) \ 859 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) 860 861 #define BP_ANADIG_PLL_528_NUM_RSVD0 30 862 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 863 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ 864 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) 865 #define BP_ANADIG_PLL_528_NUM_A 0 866 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF 867 #define BF_ANADIG_PLL_528_NUM_A(v) \ 868 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) 869 870 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30 871 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 872 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ 873 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) 874 #define BP_ANADIG_PLL_528_DENOM_B 0 875 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF 876 #define BF_ANADIG_PLL_528_DENOM_B(v) \ 877 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) 878 879 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 880 #define BP_ANADIG_PLL_AUDIO_RSVD0 22 881 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 882 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ 883 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) 884 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 885 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 886 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 887 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ 888 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) 889 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 890 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 891 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 892 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 893 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 894 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ 895 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) 896 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 897 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 898 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 899 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 900 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 901 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 902 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 903 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 904 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 905 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 906 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 907 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 908 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F 909 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ 910 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) 911 912 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 913 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 914 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ 915 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) 916 #define BP_ANADIG_PLL_AUDIO_NUM_A 0 917 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF 918 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ 919 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) 920 921 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 922 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 923 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ 924 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) 925 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 926 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF 927 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ 928 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) 929 930 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 931 #define BP_ANADIG_PLL_VIDEO_RSVD0 22 932 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 933 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ 934 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) 935 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 936 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 937 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000 938 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ 939 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) 940 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 941 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 942 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 943 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 944 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 945 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ 946 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) 947 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 948 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 949 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 950 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 951 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 952 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 953 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 954 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 955 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 956 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 957 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 958 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 959 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F 960 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ 961 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) 962 963 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 964 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 965 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ 966 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) 967 #define BP_ANADIG_PLL_VIDEO_NUM_A 0 968 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF 969 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ 970 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) 971 972 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 973 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 974 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ 975 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) 976 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 977 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF 978 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ 979 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) 980 981 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000 982 #define BP_ANADIG_PLL_ENET_RSVD1 21 983 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 984 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ 985 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) 986 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000 987 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 988 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 989 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 990 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 991 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 992 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 993 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 994 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ 995 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) 996 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 997 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 998 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 999 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 1000 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 1001 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 1002 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 1003 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 1004 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 1005 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 1006 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 1007 #define BP_ANADIG_PLL_ENET_RSVD0 2 1008 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C 1009 #define BF_ANADIG_PLL_ENET_RSVD0(v) \ 1010 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) 1011 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 1012 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 1013 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ 1014 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) 1015 1016 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 1017 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 1018 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 1019 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 1020 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ 1021 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) 1022 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 1023 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 1024 #define BP_ANADIG_PFD_480_PFD2_FRAC 16 1025 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 1026 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ 1027 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) 1028 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 1029 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 1030 #define BP_ANADIG_PFD_480_PFD1_FRAC 8 1031 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 1032 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ 1033 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) 1034 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 1035 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 1036 #define BP_ANADIG_PFD_480_PFD0_FRAC 0 1037 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F 1038 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ 1039 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) 1040 1041 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 1042 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 1043 #define BP_ANADIG_PFD_528_PFD3_FRAC 24 1044 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 1045 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ 1046 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) 1047 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 1048 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 1049 #define BP_ANADIG_PFD_528_PFD2_FRAC 16 1050 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 1051 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ 1052 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) 1053 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 1054 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 1055 #define BP_ANADIG_PFD_528_PFD1_FRAC 8 1056 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 1057 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ 1058 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) 1059 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 1060 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 1061 #define BP_ANADIG_PFD_528_PFD0_FRAC 0 1062 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F 1063 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ 1064 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) 1065 1066 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 1067 1068 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ 1069