1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 */ 19 20 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 21 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 22 23 #define CCM_CCOSR 0x020c4060 24 #define CCM_CCGR0 0x020C4068 25 #define CCM_CCGR1 0x020C406c 26 #define CCM_CCGR2 0x020C4070 27 #define CCM_CCGR3 0x020C4074 28 #define CCM_CCGR4 0x020C4078 29 #define CCM_CCGR5 0x020C407c 30 #define CCM_CCGR6 0x020C4080 31 32 #define PMU_MISC2 0x020C8170 33 34 #ifndef __ASSEMBLY__ 35 struct mxc_ccm_reg { 36 u32 ccr; /* 0x0000 */ 37 u32 ccdr; 38 u32 csr; 39 u32 ccsr; 40 u32 cacrr; /* 0x0010*/ 41 u32 cbcdr; 42 u32 cbcmr; 43 u32 cscmr1; 44 u32 cscmr2; /* 0x0020 */ 45 u32 cscdr1; 46 u32 cs1cdr; 47 u32 cs2cdr; 48 u32 cdcdr; /* 0x0030 */ 49 u32 chsccdr; 50 u32 cscdr2; 51 u32 cscdr3; 52 u32 cscdr4; /* 0x0040 */ 53 u32 resv0; 54 u32 cdhipr; 55 u32 cdcr; 56 u32 ctor; /* 0x0050 */ 57 u32 clpcr; 58 u32 cisr; 59 u32 cimr; 60 u32 ccosr; /* 0x0060 */ 61 u32 cgpr; 62 u32 CCGR0; 63 u32 CCGR1; 64 u32 CCGR2; /* 0x0070 */ 65 u32 CCGR3; 66 u32 CCGR4; 67 u32 CCGR5; 68 u32 CCGR6; /* 0x0080 */ 69 u32 CCGR7; 70 u32 cmeor; 71 u32 resv[0xfdd]; 72 u32 analog_pll_sys; /* 0x4000 */ 73 u32 analog_pll_sys_set; 74 u32 analog_pll_sys_clr; 75 u32 analog_pll_sys_tog; 76 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ 77 u32 analog_usb1_pll_480_ctrl_set; 78 u32 analog_usb1_pll_480_ctrl_clr; 79 u32 analog_usb1_pll_480_ctrl_tog; 80 u32 analog_reserved0[4]; 81 u32 analog_pll_528; /* 0x4030 */ 82 u32 analog_pll_528_set; 83 u32 analog_pll_528_clr; 84 u32 analog_pll_528_tog; 85 u32 analog_pll_528_ss; /* 0x4040 */ 86 u32 analog_reserved1[3]; 87 u32 analog_pll_528_num; /* 0x4050 */ 88 u32 analog_reserved2[3]; 89 u32 analog_pll_528_denom; /* 0x4060 */ 90 u32 analog_reserved3[3]; 91 u32 analog_pll_audio; /* 0x4070 */ 92 u32 analog_pll_audio_set; 93 u32 analog_pll_audio_clr; 94 u32 analog_pll_audio_tog; 95 u32 analog_pll_audio_num; /* 0x4080*/ 96 u32 analog_reserved4[3]; 97 u32 analog_pll_audio_denom; /* 0x4090 */ 98 u32 analog_reserved5[3]; 99 u32 analog_pll_video; /* 0x40a0 */ 100 u32 analog_pll_video_set; 101 u32 analog_pll_video_clr; 102 u32 analog_pll_video_tog; 103 u32 analog_pll_video_num; /* 0x40b0 */ 104 u32 analog_reserved6[3]; 105 u32 analog_pll_vedio_denon; /* 0x40c0 */ 106 u32 analog_reserved7[7]; 107 u32 analog_pll_enet; /* 0x40e0 */ 108 u32 analog_pll_enet_set; 109 u32 analog_pll_enet_clr; 110 u32 analog_pll_enet_tog; 111 u32 analog_pfd_480; /* 0x40f0 */ 112 u32 analog_pfd_480_set; 113 u32 analog_pfd_480_clr; 114 u32 analog_pfd_480_tog; 115 u32 analog_pfd_528; /* 0x4100 */ 116 u32 analog_pfd_528_set; 117 u32 analog_pfd_528_clr; 118 u32 analog_pfd_528_tog; 119 }; 120 #endif 121 122 /* Define the bits in register CCR */ 123 #define MXC_CCM_CCR_RBC_EN (1 << 27) 124 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) 125 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 126 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 127 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) 128 #define MXC_CCM_CCR_COSC_EN (1 << 12) 129 #define MXC_CCM_CCR_OSCNT_MASK 0xFF 130 #define MXC_CCM_CCR_OSCNT_OFFSET 0 131 132 /* Define the bits in register CCDR */ 133 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) 134 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) 135 136 /* Define the bits in register CSR */ 137 #define MXC_CCM_CSR_COSC_READY (1 << 5) 138 #define MXC_CCM_CSR_REF_EN_B (1 << 0) 139 140 /* Define the bits in register CCSR */ 141 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) 142 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) 143 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) 144 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) 145 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) 146 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) 147 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) 148 #define MXC_CCM_CCSR_STEP_SEL (1 << 8) 149 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 150 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 151 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 152 153 /* Define the bits in register CACRR */ 154 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 155 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 156 157 /* Define the bits in register CBCDR */ 158 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) 159 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 160 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) 161 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) 162 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) 163 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 164 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) 165 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 166 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 167 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 168 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 169 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 170 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) 171 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) 172 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) 173 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 174 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) 175 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 176 177 /* Define the bits in register CBCMR */ 178 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) 179 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 180 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) 181 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 182 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) 183 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 184 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) 185 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 186 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) 187 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) 188 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 189 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) 190 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 191 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 192 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 193 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) 194 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 195 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) 196 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) 197 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) 198 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 199 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) 200 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 201 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) 202 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) 203 204 /* Define the bits in register CSCMR1 */ 205 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) 206 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 207 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) 208 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 209 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) 210 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 211 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) 212 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 213 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) 214 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) 215 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) 216 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) 217 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) 218 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 219 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 220 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 221 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) 222 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 223 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F 224 225 /* Define the bits in register CSCMR2 */ 226 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) 227 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 228 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) 229 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) 230 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) 231 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 232 233 /* Define the bits in register CSCDR1 */ 234 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) 235 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 236 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) 237 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 238 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) 239 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 240 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) 241 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 242 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) 243 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 244 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 245 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 246 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 247 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 248 #ifdef CONFIG_MX6SL 249 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F 250 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) 251 #else 252 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F 253 #endif 254 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 255 256 /* Define the bits in register CS1CDR */ 257 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) 258 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 259 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) 260 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 261 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) 262 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 263 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 264 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 265 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F 266 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 267 268 /* Define the bits in register CS2CDR */ 269 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) 270 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 271 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) 272 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) 273 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 274 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) 275 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) 276 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 277 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16) 278 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) 279 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 280 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) 281 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 282 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 283 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 284 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F 285 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 286 287 /* Define the bits in register CDCDR */ 288 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) 289 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 290 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) 291 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 292 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 293 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) 294 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 295 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) 296 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 297 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) 298 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 299 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) 300 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 301 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) 302 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 303 304 /* Define the bits in register CHSCCDR */ 305 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 306 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 307 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) 308 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 309 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) 310 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 311 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 312 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 313 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) 314 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 315 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) 316 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 317 318 #define CHSCCDR_CLK_SEL_LDB_DI0 3 319 #define CHSCCDR_PODF_DIVIDE_BY_3 2 320 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 321 322 /* Define the bits in register CSCDR2 */ 323 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) 324 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 325 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 326 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 327 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) 328 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 329 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) 330 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 331 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 332 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 333 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) 334 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 335 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 336 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 337 338 /* Define the bits in register CSCDR3 */ 339 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) 340 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 341 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) 342 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 343 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) 344 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 345 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) 346 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 347 348 /* Define the bits in register CDHIPR */ 349 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 350 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 351 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) 352 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) 353 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) 354 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) 355 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 356 357 /* Define the bits in register CLPCR */ 358 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) 359 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) 360 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) 361 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) 362 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) 363 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) 364 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) 365 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) 366 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) 367 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) 368 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) 369 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 370 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 371 #define MXC_CCM_CLPCR_VSTBY (1 << 8) 372 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) 373 #define MXC_CCM_CLPCR_SBYOS (1 << 6) 374 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) 375 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 376 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 377 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) 378 #define MXC_CCM_CLPCR_LPM_MASK 0x3 379 #define MXC_CCM_CLPCR_LPM_OFFSET 0 380 381 /* Define the bits in register CISR */ 382 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) 383 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) 384 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) 385 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) 386 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) 387 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) 388 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) 389 #define MXC_CCM_CISR_COSC_READY (1 << 6) 390 #define MXC_CCM_CISR_LRF_PLL 1 391 392 /* Define the bits in register CIMR */ 393 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) 394 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) 395 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) 396 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) 397 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) 398 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) 399 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) 400 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) 401 #define MXC_CCM_CIMR_MASK_LRF_PLL 1 402 403 /* Define the bits in register CCOSR */ 404 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) 405 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 406 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 407 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 408 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 409 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 410 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 411 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 412 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF 413 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 414 415 /* Define the bits in registers CGPR */ 416 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 417 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) 418 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 419 420 /* Define the bits in registers CCGRx */ 421 #define MXC_CCM_CCGR_CG_MASK 3 422 423 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 424 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) 425 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 426 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) 427 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 428 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) 429 #define MXC_CCM_CCGR0_ASRC_OFFSET 6 430 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) 431 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 432 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) 433 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 434 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) 435 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 436 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) 437 #define MXC_CCM_CCGR0_CAN1_OFFSET 14 438 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) 439 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 440 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) 441 #define MXC_CCM_CCGR0_CAN2_OFFSET 18 442 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) 443 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 444 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) 445 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 446 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) 447 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24 448 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) 449 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 450 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) 451 #define MXC_CCM_CCGR0_DTCP_OFFSET 28 452 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) 453 454 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 455 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) 456 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 457 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) 458 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 459 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) 460 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 461 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) 462 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 463 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) 464 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 465 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) 466 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 467 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) 468 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 469 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) 470 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 471 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) 472 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 473 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) 474 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 475 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) 476 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 477 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) 478 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 479 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) 480 481 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 482 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) 483 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 484 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) 485 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 486 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) 487 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 488 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) 489 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 490 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) 491 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 492 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) 493 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 494 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) 495 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 496 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) 497 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 498 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) 499 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 500 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) 501 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 502 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) 503 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 504 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) 505 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 506 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) 507 508 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 509 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) 510 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 511 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) 512 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 513 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) 514 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 515 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) 516 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 517 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) 518 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 519 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) 520 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 521 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) 522 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 523 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) 524 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 525 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) 526 #define MXC_CCM_CCGR3_MLB_OFFSET 18 527 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) 528 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 529 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) 530 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 531 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) 532 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 533 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) 534 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 535 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) 536 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 537 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) 538 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 539 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) 540 541 #define MXC_CCM_CCGR4_PCIE_OFFSET 0 542 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) 543 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 544 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) 545 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 546 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) 547 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 548 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) 549 #define MXC_CCM_CCGR4_PWM1_OFFSET 16 550 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) 551 #define MXC_CCM_CCGR4_PWM2_OFFSET 18 552 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) 553 #define MXC_CCM_CCGR4_PWM3_OFFSET 20 554 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) 555 #define MXC_CCM_CCGR4_PWM4_OFFSET 22 556 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) 557 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 558 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) 559 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 560 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) 561 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 562 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) 563 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 564 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) 565 566 #define MXC_CCM_CCGR5_ROM_OFFSET 0 567 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) 568 #define MXC_CCM_CCGR5_SATA_OFFSET 4 569 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) 570 #define MXC_CCM_CCGR5_SDMA_OFFSET 6 571 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) 572 #define MXC_CCM_CCGR5_SPBA_OFFSET 12 573 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) 574 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14 575 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) 576 #define MXC_CCM_CCGR5_SSI1_OFFSET 18 577 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) 578 #define MXC_CCM_CCGR5_SSI2_OFFSET 20 579 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) 580 #define MXC_CCM_CCGR5_SSI3_OFFSET 22 581 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) 582 #define MXC_CCM_CCGR5_UART_OFFSET 24 583 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) 584 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 585 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) 586 587 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 588 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) 589 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2 590 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) 591 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 592 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) 593 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 594 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) 595 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 596 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) 597 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 598 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) 599 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 600 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) 601 602 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 603 #define BP_ANADIG_PLL_SYS_RSVD0 20 604 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 605 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ 606 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) 607 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 608 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 609 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 610 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 611 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 612 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 613 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ 614 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) 615 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 616 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 617 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 618 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 619 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 620 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 621 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 622 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 623 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 624 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 625 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 626 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0 627 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F 628 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ 629 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) 630 631 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 632 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 633 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 634 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ 635 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) 636 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 637 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 638 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 639 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ 640 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) 641 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 642 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 643 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 644 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 645 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 646 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 647 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 648 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 649 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 650 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 651 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 652 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 653 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 654 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 655 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C 656 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ 657 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) 658 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 659 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 660 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ 661 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) 662 663 #define BM_ANADIG_PLL_528_LOCK 0x80000000 664 #define BP_ANADIG_PLL_528_RSVD1 19 665 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 666 #define BF_ANADIG_PLL_528_RSVD1(v) \ 667 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) 668 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 669 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 670 #define BM_ANADIG_PLL_528_BYPASS 0x00010000 671 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 672 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 673 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ 674 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) 675 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 676 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 677 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 678 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 679 #define BM_ANADIG_PLL_528_ENABLE 0x00002000 680 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 681 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 682 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 683 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200 684 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 685 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080 686 #define BP_ANADIG_PLL_528_RSVD0 1 687 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E 688 #define BF_ANADIG_PLL_528_RSVD0(v) \ 689 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) 690 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 691 692 #define BP_ANADIG_PLL_528_SS_STOP 16 693 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 694 #define BF_ANADIG_PLL_528_SS_STOP(v) \ 695 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) 696 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 697 #define BP_ANADIG_PLL_528_SS_STEP 0 698 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF 699 #define BF_ANADIG_PLL_528_SS_STEP(v) \ 700 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) 701 702 #define BP_ANADIG_PLL_528_NUM_RSVD0 30 703 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 704 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ 705 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) 706 #define BP_ANADIG_PLL_528_NUM_A 0 707 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF 708 #define BF_ANADIG_PLL_528_NUM_A(v) \ 709 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) 710 711 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30 712 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 713 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ 714 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) 715 #define BP_ANADIG_PLL_528_DENOM_B 0 716 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF 717 #define BF_ANADIG_PLL_528_DENOM_B(v) \ 718 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) 719 720 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 721 #define BP_ANADIG_PLL_AUDIO_RSVD0 22 722 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 723 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ 724 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) 725 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 726 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 727 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 728 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ 729 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) 730 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 731 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 732 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 733 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 734 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 735 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ 736 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) 737 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 738 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 739 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 740 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 741 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 742 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 743 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 744 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 745 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 746 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 747 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 748 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 749 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F 750 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ 751 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) 752 753 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 754 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 755 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ 756 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) 757 #define BP_ANADIG_PLL_AUDIO_NUM_A 0 758 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF 759 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ 760 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) 761 762 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 763 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 764 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ 765 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) 766 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 767 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF 768 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ 769 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) 770 771 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 772 #define BP_ANADIG_PLL_VIDEO_RSVD0 22 773 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 774 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ 775 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) 776 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 777 #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 778 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 779 #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ 780 (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) 781 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 782 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 783 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 784 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 785 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 786 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ 787 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) 788 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 789 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 790 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 791 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 792 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 793 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 794 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 795 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 796 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 797 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 798 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 799 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 800 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F 801 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ 802 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) 803 804 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 805 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 806 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ 807 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) 808 #define BP_ANADIG_PLL_VIDEO_NUM_A 0 809 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF 810 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ 811 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) 812 813 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 814 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 815 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ 816 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) 817 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 818 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF 819 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ 820 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) 821 822 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000 823 #define BP_ANADIG_PLL_ENET_RSVD1 21 824 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 825 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ 826 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) 827 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 828 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 829 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 830 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 831 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 832 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 833 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 834 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ 835 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) 836 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 837 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 838 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 839 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 840 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 841 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 842 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 843 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 844 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 845 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 846 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 847 #define BP_ANADIG_PLL_ENET_RSVD0 2 848 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C 849 #define BF_ANADIG_PLL_ENET_RSVD0(v) \ 850 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) 851 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 852 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 853 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ 854 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) 855 856 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 857 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 858 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 859 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 860 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ 861 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) 862 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 863 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 864 #define BP_ANADIG_PFD_480_PFD2_FRAC 16 865 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 866 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ 867 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) 868 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 869 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 870 #define BP_ANADIG_PFD_480_PFD1_FRAC 8 871 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 872 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ 873 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) 874 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 875 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 876 #define BP_ANADIG_PFD_480_PFD0_FRAC 0 877 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F 878 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ 879 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) 880 881 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 882 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 883 #define BP_ANADIG_PFD_528_PFD3_FRAC 24 884 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 885 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ 886 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) 887 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 888 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 889 #define BP_ANADIG_PFD_528_PFD2_FRAC 16 890 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 891 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ 892 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) 893 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 894 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 895 #define BP_ANADIG_PFD_528_PFD1_FRAC 8 896 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 897 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ 898 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) 899 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 900 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 901 #define BP_ANADIG_PFD_528_PFD0_FRAC 0 902 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F 903 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ 904 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) 905 906 #define PLL2_PFD0_FREQ 352000000 907 #define PLL2_PFD1_FREQ 594000000 908 #define PLL2_PFD2_FREQ 400000000 909 #define PLL2_PFD2_DIV_FREQ 200000000 910 #define PLL3_PFD0_FREQ 720000000 911 #define PLL3_PFD1_FREQ 540000000 912 #define PLL3_PFD2_FREQ 508200000 913 #define PLL3_PFD3_FREQ 454700000 914 #define PLL3_80M 80000000 915 #define PLL3_60M 60000000 916 917 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ 918