1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 */ 19 20 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 21 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 22 23 #define CCM_CCGR0 0x020C4068 24 #define CCM_CCGR1 0x020C406c 25 #define CCM_CCGR2 0x020C4070 26 #define CCM_CCGR3 0x020C4074 27 #define CCM_CCGR4 0x020C4078 28 #define CCM_CCGR5 0x020C407c 29 #define CCM_CCGR6 0x020C4080 30 31 #define PMU_MISC2 0x020C8170 32 33 #ifndef __ASSEMBLY__ 34 struct mxc_ccm_reg { 35 u32 ccr; /* 0x0000 */ 36 u32 ccdr; 37 u32 csr; 38 u32 ccsr; 39 u32 cacrr; /* 0x0010*/ 40 u32 cbcdr; 41 u32 cbcmr; 42 u32 cscmr1; 43 u32 cscmr2; /* 0x0020 */ 44 u32 cscdr1; 45 u32 cs1cdr; 46 u32 cs2cdr; 47 u32 cdcdr; /* 0x0030 */ 48 u32 chsccdr; 49 u32 cscdr2; 50 u32 cscdr3; 51 u32 cscdr4; /* 0x0040 */ 52 u32 resv0; 53 u32 cdhipr; 54 u32 cdcr; 55 u32 ctor; /* 0x0050 */ 56 u32 clpcr; 57 u32 cisr; 58 u32 cimr; 59 u32 ccosr; /* 0x0060 */ 60 u32 cgpr; 61 u32 CCGR0; 62 u32 CCGR1; 63 u32 CCGR2; /* 0x0070 */ 64 u32 CCGR3; 65 u32 CCGR4; 66 u32 CCGR5; 67 u32 CCGR6; /* 0x0080 */ 68 u32 CCGR7; 69 u32 cmeor; 70 u32 resv[0xfdd]; 71 u32 analog_pll_sys; /* 0x4000 */ 72 u32 analog_pll_sys_set; 73 u32 analog_pll_sys_clr; 74 u32 analog_pll_sys_tog; 75 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ 76 u32 analog_usb1_pll_480_ctrl_set; 77 u32 analog_usb1_pll_480_ctrl_clr; 78 u32 analog_usb1_pll_480_ctrl_tog; 79 u32 analog_reserved0[4]; 80 u32 analog_pll_528; /* 0x4030 */ 81 u32 analog_pll_528_set; 82 u32 analog_pll_528_clr; 83 u32 analog_pll_528_tog; 84 u32 analog_pll_528_ss; /* 0x4040 */ 85 u32 analog_reserved1[3]; 86 u32 analog_pll_528_num; /* 0x4050 */ 87 u32 analog_reserved2[3]; 88 u32 analog_pll_528_denom; /* 0x4060 */ 89 u32 analog_reserved3[3]; 90 u32 analog_pll_audio; /* 0x4070 */ 91 u32 analog_pll_audio_set; 92 u32 analog_pll_audio_clr; 93 u32 analog_pll_audio_tog; 94 u32 analog_pll_audio_num; /* 0x4080*/ 95 u32 analog_reserved4[3]; 96 u32 analog_pll_audio_denom; /* 0x4090 */ 97 u32 analog_reserved5[3]; 98 u32 analog_pll_video; /* 0x40a0 */ 99 u32 analog_pll_video_set; 100 u32 analog_pll_video_clr; 101 u32 analog_pll_video_tog; 102 u32 analog_pll_video_num; /* 0x40b0 */ 103 u32 analog_reserved6[3]; 104 u32 analog_pll_vedio_denon; /* 0x40c0 */ 105 u32 analog_reserved7[7]; 106 u32 analog_pll_enet; /* 0x40e0 */ 107 u32 analog_pll_enet_set; 108 u32 analog_pll_enet_clr; 109 u32 analog_pll_enet_tog; 110 u32 analog_pfd_480; /* 0x40f0 */ 111 u32 analog_pfd_480_set; 112 u32 analog_pfd_480_clr; 113 u32 analog_pfd_480_tog; 114 u32 analog_pfd_528; /* 0x4100 */ 115 u32 analog_pfd_528_set; 116 u32 analog_pfd_528_clr; 117 u32 analog_pfd_528_tog; 118 }; 119 #endif 120 121 /* Define the bits in register CCR */ 122 #define MXC_CCM_CCR_RBC_EN (1 << 27) 123 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) 124 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 125 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 126 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) 127 #define MXC_CCM_CCR_COSC_EN (1 << 12) 128 #define MXC_CCM_CCR_OSCNT_MASK 0xFF 129 #define MXC_CCM_CCR_OSCNT_OFFSET 0 130 131 /* Define the bits in register CCDR */ 132 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) 133 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) 134 135 /* Define the bits in register CSR */ 136 #define MXC_CCM_CSR_COSC_READY (1 << 5) 137 #define MXC_CCM_CSR_REF_EN_B (1 << 0) 138 139 /* Define the bits in register CCSR */ 140 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) 141 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) 142 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) 143 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) 144 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) 145 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) 146 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) 147 #define MXC_CCM_CCSR_STEP_SEL (1 << 8) 148 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 149 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 150 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 151 152 /* Define the bits in register CACRR */ 153 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 154 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 155 156 /* Define the bits in register CBCDR */ 157 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) 158 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 159 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) 160 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) 161 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) 162 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 163 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) 164 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 165 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 166 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 167 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 168 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 169 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) 170 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) 171 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) 172 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 173 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) 174 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 175 176 /* Define the bits in register CBCMR */ 177 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) 178 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 179 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) 180 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 181 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) 182 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 183 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) 184 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 185 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) 186 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) 187 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 188 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) 189 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 190 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 191 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 192 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) 193 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 194 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) 195 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) 196 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) 197 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 198 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) 199 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 200 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) 201 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) 202 203 /* Define the bits in register CSCMR1 */ 204 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) 205 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 206 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) 207 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 208 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) 209 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 210 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) 211 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 212 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) 213 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) 214 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) 215 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) 216 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) 217 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 218 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 219 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 220 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) 221 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 222 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F 223 224 /* Define the bits in register CSCMR2 */ 225 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) 226 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 227 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) 228 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) 229 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) 230 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 231 232 /* Define the bits in register CSCDR1 */ 233 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) 234 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 235 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) 236 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 237 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) 238 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 239 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) 240 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 241 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) 242 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 243 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 244 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 245 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 246 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 247 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F 248 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 249 250 /* Define the bits in register CS1CDR */ 251 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) 252 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 253 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) 254 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 255 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) 256 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 257 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 258 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 259 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F 260 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 261 262 /* Define the bits in register CS2CDR */ 263 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) 264 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 265 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) 266 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 267 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) 268 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 269 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) 270 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 271 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) 272 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 273 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 274 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 275 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F 276 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 277 278 /* Define the bits in register CDCDR */ 279 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) 280 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 281 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) 282 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 283 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 284 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) 285 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 286 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) 287 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 288 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) 289 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 290 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) 291 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 292 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) 293 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 294 295 /* Define the bits in register CHSCCDR */ 296 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 297 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 298 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) 299 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 300 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) 301 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 302 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 303 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 304 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) 305 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 306 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) 307 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 308 309 #define CHSCCDR_CLK_SEL_LDB_DI0 3 310 #define CHSCCDR_PODF_DIVIDE_BY_3 2 311 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 312 313 /* Define the bits in register CSCDR2 */ 314 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) 315 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 316 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 317 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 318 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) 319 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 320 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) 321 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 322 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 323 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 324 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) 325 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 326 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 327 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 328 329 /* Define the bits in register CSCDR3 */ 330 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) 331 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 332 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) 333 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 334 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) 335 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 336 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) 337 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 338 339 /* Define the bits in register CDHIPR */ 340 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 341 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 342 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) 343 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) 344 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) 345 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) 346 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 347 348 /* Define the bits in register CLPCR */ 349 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) 350 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) 351 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) 352 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) 353 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) 354 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) 355 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) 356 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) 357 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) 358 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) 359 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) 360 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 361 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 362 #define MXC_CCM_CLPCR_VSTBY (1 << 8) 363 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) 364 #define MXC_CCM_CLPCR_SBYOS (1 << 6) 365 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) 366 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 367 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 368 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) 369 #define MXC_CCM_CLPCR_LPM_MASK 0x3 370 #define MXC_CCM_CLPCR_LPM_OFFSET 0 371 372 /* Define the bits in register CISR */ 373 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) 374 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) 375 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) 376 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) 377 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) 378 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) 379 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) 380 #define MXC_CCM_CISR_COSC_READY (1 << 6) 381 #define MXC_CCM_CISR_LRF_PLL 1 382 383 /* Define the bits in register CIMR */ 384 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) 385 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) 386 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) 387 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) 388 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) 389 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) 390 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) 391 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) 392 #define MXC_CCM_CIMR_MASK_LRF_PLL 1 393 394 /* Define the bits in register CCOSR */ 395 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) 396 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 397 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 398 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 399 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 400 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 401 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 402 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 403 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF 404 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 405 406 /* Define the bits in registers CGPR */ 407 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 408 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) 409 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 410 411 /* Define the bits in registers CCGRx */ 412 #define MXC_CCM_CCGR_CG_MASK 3 413 414 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 415 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) 416 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 417 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) 418 #define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4 419 #define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA) 420 #define MXC_CCM_CCGR0_ASRC_OFFSET 6 421 #define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET) 422 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 423 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) 424 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 425 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) 426 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 427 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) 428 #define MXC_CCM_CCGR0_CAN1_OFFSET 14 429 #define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET) 430 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 431 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) 432 #define MXC_CCM_CCGR0_CAN2_OFFSET 18 433 #define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET) 434 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 435 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) 436 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 437 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) 438 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24 439 #define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET) 440 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 441 #define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET) 442 #define MXC_CCM_CCGR0_DTCP_OFFSET 28 443 #define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET) 444 445 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 446 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET) 447 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 448 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET) 449 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 450 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET) 451 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 452 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET) 453 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 454 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET) 455 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 456 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) 457 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 458 #define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET) 459 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 460 #define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET) 461 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 462 #define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET) 463 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 464 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET) 465 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 466 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) 467 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 468 #define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET) 469 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 470 #define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET) 471 472 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 473 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) 474 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 475 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) 476 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 477 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) 478 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 479 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) 480 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 481 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) 482 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 483 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) 484 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 485 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) 486 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 487 #define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET) 488 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 489 #define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET) 490 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 491 #define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET) 492 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 493 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) 494 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 495 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) 496 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 497 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) 498 499 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 500 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET) 501 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 502 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) 503 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 504 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) 505 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 506 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET) 507 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 508 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) 509 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 510 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) 511 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 512 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET) 513 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 514 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET) 515 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 516 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) 517 #define MXC_CCM_CCGR3_MLB_OFFSET 18 518 #define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET) 519 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 520 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) 521 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 522 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) 523 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 524 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) 525 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 526 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) 527 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 528 #define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET) 529 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 530 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) 531 532 #define MXC_CCM_CCGR4_PCIE_OFFSET 0 533 #define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET) 534 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 535 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) 536 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 537 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) 538 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 539 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) 540 #define MXC_CCM_CCGR4_PWM1_OFFSET 16 541 #define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET) 542 #define MXC_CCM_CCGR4_PWM2_OFFSET 18 543 #define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET) 544 #define MXC_CCM_CCGR4_PWM3_OFFSET 20 545 #define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET) 546 #define MXC_CCM_CCGR4_PWM4_OFFSET 22 547 #define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET) 548 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 549 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) 550 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 551 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) 552 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 553 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) 554 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 555 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) 556 557 #define MXC_CCM_CCGR5_ROM_OFFSET 0 558 #define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET) 559 #define MXC_CCM_CCGR5_SATA_OFFSET 4 560 #define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET) 561 #define MXC_CCM_CCGR5_SDMA_OFFSET 6 562 #define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET) 563 #define MXC_CCM_CCGR5_SPBA_OFFSET 12 564 #define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET) 565 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14 566 #define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET) 567 #define MXC_CCM_CCGR5_SSI1_OFFSET 18 568 #define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET) 569 #define MXC_CCM_CCGR5_SSI2_OFFSET 20 570 #define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET) 571 #define MXC_CCM_CCGR5_SSI3_OFFSET 22 572 #define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET) 573 #define MXC_CCM_CCGR5_UART_OFFSET 24 574 #define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET) 575 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 576 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET) 577 578 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 579 #define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET) 580 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2 581 #define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET) 582 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 583 #define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET) 584 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 585 #define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET) 586 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 587 #define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET) 588 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 589 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET) 590 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 591 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET) 592 593 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 594 #define BP_ANADIG_PLL_SYS_RSVD0 20 595 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 596 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ 597 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) 598 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 599 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 600 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 601 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 602 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 603 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 604 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ 605 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) 606 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 607 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 608 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 609 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 610 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 611 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 612 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 613 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 614 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 615 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 616 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 617 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0 618 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F 619 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ 620 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) 621 622 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 623 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 624 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 625 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ 626 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) 627 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 628 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 629 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 630 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ 631 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) 632 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 633 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 634 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 635 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 636 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 637 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 638 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 639 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 640 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 641 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 642 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 643 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 644 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 645 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 646 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C 647 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ 648 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) 649 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 650 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 651 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ 652 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) 653 654 #define BM_ANADIG_PLL_528_LOCK 0x80000000 655 #define BP_ANADIG_PLL_528_RSVD1 19 656 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 657 #define BF_ANADIG_PLL_528_RSVD1(v) \ 658 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) 659 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 660 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 661 #define BM_ANADIG_PLL_528_BYPASS 0x00010000 662 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 663 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 664 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ 665 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) 666 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 667 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 668 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 669 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 670 #define BM_ANADIG_PLL_528_ENABLE 0x00002000 671 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 672 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 673 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 674 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200 675 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 676 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080 677 #define BP_ANADIG_PLL_528_RSVD0 1 678 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E 679 #define BF_ANADIG_PLL_528_RSVD0(v) \ 680 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) 681 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 682 683 #define BP_ANADIG_PLL_528_SS_STOP 16 684 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 685 #define BF_ANADIG_PLL_528_SS_STOP(v) \ 686 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) 687 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 688 #define BP_ANADIG_PLL_528_SS_STEP 0 689 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF 690 #define BF_ANADIG_PLL_528_SS_STEP(v) \ 691 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) 692 693 #define BP_ANADIG_PLL_528_NUM_RSVD0 30 694 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 695 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ 696 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) 697 #define BP_ANADIG_PLL_528_NUM_A 0 698 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF 699 #define BF_ANADIG_PLL_528_NUM_A(v) \ 700 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) 701 702 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30 703 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 704 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ 705 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) 706 #define BP_ANADIG_PLL_528_DENOM_B 0 707 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF 708 #define BF_ANADIG_PLL_528_DENOM_B(v) \ 709 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) 710 711 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 712 #define BP_ANADIG_PLL_AUDIO_RSVD0 22 713 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 714 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ 715 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) 716 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 717 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 718 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 719 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ 720 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) 721 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 722 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 723 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 724 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 725 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 726 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ 727 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) 728 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 729 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 730 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 731 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 732 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 733 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 734 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 735 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 736 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 737 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 738 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 739 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 740 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F 741 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ 742 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) 743 744 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 745 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 746 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ 747 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) 748 #define BP_ANADIG_PLL_AUDIO_NUM_A 0 749 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF 750 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ 751 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) 752 753 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 754 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 755 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ 756 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) 757 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 758 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF 759 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ 760 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) 761 762 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 763 #define BP_ANADIG_PLL_VIDEO_RSVD0 22 764 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 765 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ 766 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) 767 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 768 #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 769 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 770 #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ 771 (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) 772 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 773 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 774 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 775 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 776 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 777 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ 778 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) 779 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 780 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 781 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 782 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 783 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 784 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 785 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 786 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 787 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 788 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 789 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 790 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 791 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F 792 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ 793 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) 794 795 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 796 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 797 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ 798 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) 799 #define BP_ANADIG_PLL_VIDEO_NUM_A 0 800 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF 801 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ 802 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) 803 804 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 805 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 806 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ 807 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) 808 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 809 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF 810 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ 811 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) 812 813 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000 814 #define BP_ANADIG_PLL_ENET_RSVD1 21 815 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 816 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ 817 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) 818 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 819 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 820 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 821 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 822 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 823 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 824 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 825 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ 826 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) 827 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 828 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 829 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 830 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 831 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 832 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 833 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 834 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 835 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 836 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 837 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 838 #define BP_ANADIG_PLL_ENET_RSVD0 2 839 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C 840 #define BF_ANADIG_PLL_ENET_RSVD0(v) \ 841 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) 842 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 843 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 844 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ 845 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) 846 847 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 848 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 849 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 850 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 851 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ 852 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) 853 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 854 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 855 #define BP_ANADIG_PFD_480_PFD2_FRAC 16 856 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 857 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ 858 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) 859 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 860 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 861 #define BP_ANADIG_PFD_480_PFD1_FRAC 8 862 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 863 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ 864 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) 865 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 866 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 867 #define BP_ANADIG_PFD_480_PFD0_FRAC 0 868 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F 869 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ 870 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) 871 872 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 873 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 874 #define BP_ANADIG_PFD_528_PFD3_FRAC 24 875 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 876 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ 877 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) 878 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 879 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 880 #define BP_ANADIG_PFD_528_PFD2_FRAC 16 881 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 882 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ 883 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) 884 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 885 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 886 #define BP_ANADIG_PFD_528_PFD1_FRAC 8 887 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 888 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ 889 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) 890 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 891 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 892 #define BP_ANADIG_PFD_528_PFD0_FRAC 0 893 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F 894 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ 895 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) 896 897 #define PLL2_PFD0_FREQ 352000000 898 #define PLL2_PFD1_FREQ 594000000 899 #define PLL2_PFD2_FREQ 400000000 900 #define PLL2_PFD2_DIV_FREQ 200000000 901 #define PLL3_PFD0_FREQ 720000000 902 #define PLL3_PFD1_FREQ 540000000 903 #define PLL3_PFD2_FREQ 508200000 904 #define PLL3_PFD3_FREQ 454700000 905 #define PLL3_80M 80000000 906 #define PLL3_60M 60000000 907 908 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ 909